Post on 15-Jan-2022
65W Active Clamp Flyback Adaptor for PD Solution
Mike Chen
Application Development Manager
Industrial Power & Energy Competence Center
AP Region, STMicroelectronics
Agenda
2
1 USB PD adaptor development
2Topology used in USB PD adaptor
3
4 ST 65W ACF USB PD Adaptor
5Gallium Nitride (GaN) used in power supply
6 ST MasterGaN Introduction
765W Demo key test result and design considerations
8 ST Solutions with MasterGaN
ACF Control method
USB PD adaptor development
3
Power Level Increasing 5W 65W 120W
Power Density Increasing 5W/in3 20W/in3 30W/in3
Switching frequency Increasing 60kHz 150kHz 350kHz
*Latest Extended Power Range: Up to 48V 240W
Topology used in USB PD adaptor
4
Topology
Traditional Flyback Active Clamp Flyback
Operation
Stage1: Q1 turn on, Q2(SR) turn off, magnetic inductance current
increase to store energy
Stage2: Q1 turn off, Q2(SR) turn on, the magnetic inductance energy
transfer to output; the leakage inductance energy be absorbed by
R2/C2
Stage1: S1 turn on, S2 and Qsr turn off, magnetic inductance current
increase to store energy
Stage2: S1 turn off, Qsr turn on, the magnetic inductance energy
transfer to output; at same time, S2 turn on and the leakage inductance
energy transfer to C2
Stage3: S2 turn on, energy stored in C2 will discharge S1 Coss to
achieve ZVS for S1
PROs• Low cost
• Easy design
• The energy of the leakage inductance is recycled
• ZVS is achieved and switching losses are minimized → High
efficiency and high switching frequency achievable
CONs
• High power loss and spike caused by leakage inductance of the
transformer
• High switching loss of the main MOSFET due to the spike
𝑷 ሻ𝐒𝐖−𝐎𝐍(𝑪𝒐𝒔𝒔 = 𝒇𝑺𝑾න𝟎
𝑽 ሻ𝐃𝐒(𝑶𝑭𝑭
𝑪𝑶𝑺𝑺(𝑽𝒅𝒔ሻ𝑽𝒅𝒔𝐝𝑽𝒅𝒔
• Additional clamp power switch with dedicated high-side driver
• Increases the complexity of the controller
Topology used in USB PD adaptor
5
45W 65W 100W
*To comply with EN61000-3-2 European standard, PFC is required for power supply rated at >=75W
Topology normally
adoptedQR Flyback
ACF
QR Flyback
• PFC+LLC
• PFC+ACF
• PFC+AHB
Output type1C
1A1C
1C
1A1C
2A1C
2C1A
2A1C
2A2C
……..
Power density 0.3W~1W/CC 0.7W~1.5W/CC 0.5W-1W/CC
ACF control method
6
Typical Waveform
Control theory ComplementaryClassics
Non-Complementary
ST adopted new
Non-Complementary
OperationClamp Switch & Main switch turn
on complementary with dead time
Clamp Switch turn on one time:
while secondary current zero
crossing
Clamp switch turn on two times:
• After main switch turn off
• Secondary zero crossing
7Features • ZVS
• ZVS
• Lower RMS current to clamp
switch
• ZVS
• Lower RMS current to clamp
switch
• Reduce reverse conduction loss
of clamp switch
• Especially suitable for GaN
application
65W ACF with MasterGaN2
7
• High switching frequency to achieve high
power density >30W/inch3
• Bill of material reduction
• Very compact and simplified PCB Layout
• Input Voltage: Universal AC from 90 VAC to 264 VAC with 47 Hz up to 63 Hz
• Output Voltage: Single Type-C output 5 VDC-20 VDC
• Output power: 65W Max.
• Efficiency: Meets CoC Tier 2 and DoE Level 6 efficiency requirements
• EMC Compliance: CISPR22B / EN55022B
• Support for USB-PD, PPS, SCP, FCP & QC protocols
Key Products
ACF
Controller
digital controller
dedicated for ACF
MasterGaN2IC integrated with 2pcs
GaN and gate driver
STL90N10F7PowerFLAT 5x6
package SR MOSFET
STL260N4LF7PowerFLAT 5x6
package loading switch
65W Active Clamp Flyback with planar transformer
Final Release: Q4/21
65W ACF main topology
8
225mΩ
150mΩ
ST ACF Controller
MasterGan2
GaN vs. Silicon based transistors
9
• Gallium Nitride (GaN) - wide-bandgap (WBG) material
• GaN HEMT - High Electron Mobility Transistor, represents a
major step forward in power electronics
• For higher frequency operation
• Increased efficiency
• Higher power density compared to silicon-based transistors
Characteristic GaN Silicon Comments
Qg-Gate charge Lower Higher Lower driver loss for higher frequency & efficiency
Coss-Output capacitance Lower HigherLower switching loss fpr higher frequency &
efficiency
Qrr-Reverse recovery charge Lower Higher GaN suitable for higher frequency & efficiency
Vgs- gate voltage Difficult Easy GaN needs better gate drive circuit and PCB layout
Vsd-body diode conduction Higher Lower GaNs needs better control of deadtime
System-in-package/ System-on-chipapplication advantages
10
Gate drive loop stray inductance
causes gate ringing and increases
likelihood of false turn-on
Power loop stray inductance
causes higher voltage spikes
A gate dumping resistor and a
multilayer-PCB with optimized layout are
necessary to reduce above effects.
Discrete GaN Solution
LDRIVER_VDD
LDRIVER_OUT
LDRIVER_GND
LG_PCB
LS_PCB
LG_GaN
LD
LSLKS
IN
DRAIN
SOURCE
Power loop inductance
in Half Bridge (HB) configurationGate drive loop inductance
Including Kelvin pin
Switching waveforms
9 A / 1 MHz
Integrated GaN Solution
Gate drive loop inductance
LDRIVER_VDD
LDRIVER_GND
LG
LGS
LD
LS
IN
DRAIN
SOURCE
Extremely low gate drive loop stray inductance
drastically reduces Vgs ringing:
Lower stress on Gate structure → improved
reliability
Reduced damping resistance on driver output →
faster switching, lower switching losses
Lower stray inductance in the power loop
drastically reduces Vds spikes:
Lower switching losses
Lower EMI
Lower Vds voltage stress
Power loop inductance
in Half Bridge configuration
Very flat near emission spectrum
Switching waveforms
15 A / 1 MHz
LG_GaN
LD
DRAIN
LG_GaN
LS
SOURCE
LS_PCB
Higher
power densityHigher switching speed helps reduce
systems size and cost
Faster
go-to-marketPackaged solution simplifies design
and improves performance
Higher efficiencyReduced power losses, reduced
power consumption, exceeding the
most stringent energy requirements
Smart GaN: Integrating GaN with driver
11
MASTERGAN2
12
• Integrated power GaN
• Embedded gate driver
easily supplied by the
integrated bootstrap diode
• UVLO protection on both the lower and upper driving sections, preventing the
power switches from operating in low efficiency or dangerous conditions, and
the interlocking function avoids cross-conduction conditions
• Over temperature protection
• Smart solution in GQFN 9x9 mm2 package
• Input pins extended range -3.3 to 15 V with hysteresis and pull-down- allows
easy interfacing with microcontrollers, DSP units or Hall effect sensors
• Dedicated pin for shutdown functionality
• Accurate internal timing match
Compact
Robust
Easy
Design
Advanced power solution integrating a gate driver and two
enhancement mode GaN transistors in half-bridge configuration
VDS 600 V
RDSON 150 mΩ (LS)
+ 225 mΩ (HS)
IDSMAX 10 A (LS) + 6.5 A (HS) (@25C)
Mass production
GQFN 9x9 mm2,
pin-to-pin scalable
MASTERGAN* platform
13
The world first solution combining 600 V half-bridge driver
with GaN HEMT: compact, robust & easy to design
* registered and/or unregistered trademarks of STMicroelectronics International NV or its affiliates in the EU and/or elsewhere
MasterGaN1
Up to 400W
MasterGaN3
Up to 45 W
MasterGaN2
Up to 65 W
MasterGaN5
Up to 100 W
MasterGaN4
Up to 200 W
Usually Active Clamp Flyback
200mΩ + 500mΩ
Asymmetrical HB
150mΩ + 200mΩ
Asymmetrical HB
500mΩ + 500mΩ
Symmetrical HB
200mΩ + 200mΩ
Symmetrical HB
150mΩ + 150mΩ
Symmetrical HB
Mass ProductionMass Production
Usually LLC Resonant and Active Clamp Flyback
Mass ProductionMass Production Mass Production
MASTERGAN pinout
14
65W ACF application example
15
Suggested 6V typ
Suggested 10ohm
Shunt is very common: LS driving is guaranteed
until the voltage difference between PGND and
GND is within +/-2V
Hi performance Ceramic Cap to be as close
as possible between HV and Sense and
between HV and VS
RC network for OTP
extended time constant
(*)
(*)
(*) External 6.2V Zener is suggested to protect the
GaNs from transient high voltage stresses
(**) In case of very small Duty cycles, external,
Low RD, high speed Bootstrap Diode is
recommended .. In case of intense negative
voltage on OUT, even Linear regulator is possible
(**)
Controller
65W ACF USB PD adaptor efficiency
16
% Loading 5V 9V 12V 15V 20V
EU CoC Rev.05-Tier2 Limit
for 10% Loading 72.48% 77.30% 78.30% 78.85% 78.85%
115Vac 60Hz Input
10% 84.53% 85.54% 86.32% 86.24% 85.62%
25% 87.07% 89.32% 89.42% 89.60% 89.18%
50% 88.82% 89.99% 90.59% 91.28% 89.89%
75% 88.92% 91.31% 91.93% 92.48% 91.19%
100% 88.15% 91.02% 91.69% 92.50% 91.94%
Result-4 Points Average 88.24% 90.41% 90.91% 91.47% 90.55%
EU CoC Rev.05-Tier2 Limit
Of 4 points average efficiency 81.84% 87.30% 88.30% 88.85% 88.85%
80.00%
82.00%
84.00%
86.00%
88.00%
90.00%
92.00%
94.00%
10% 25% 50% 75% 100%
Efficiency at 115Vac Input
5V 9V 12V 15V 20V
Efficiency performance at low Line 115Vac
65W ACF USB PD adaptor efficiency
17
80.00%
82.00%
84.00%
86.00%
88.00%
90.00%
92.00%
94.00%
10% 25% 50% 75% 100%
Efficiency at 230Vac Input
5V 9V 12V 15V 20V
% Loading 5V 9V 12V 15V 20V
EU CoC Rev.05-Tier2 Limit
for 10% Loading 72.48% 77.30% 78.30% 78.85% 78.85%
230Vac 50Hz Input
10% 81.32% 85.51% 86.21% 85.32% 84.74%
25% 85.01% 87.68% 88.36% 88.90% 88.56%
50% 86.25% 89.32% 89.83% 90.66% 90.22%
75% 86.82% 90.74% 91.40% 92.05% 92.19%
100% 87.68% 90.68% 92.34% 92.90% 93.31%
Result-4 Points Average 86.44% 89.60% 90.48% 91.13% 90.99%
EU CoC Rev.05-Tier2 Limit
Of 4 points average efficiency 81.84% 87.30% 88.30% 88.85% 88.85%
Efficiency performance at high Line 230Vac
65W ACF USB PD adaptor efficiency
18
70.00%
73.00%
76.00%
79.00%
82.00%
85.00%
88.00%
91.00%
94.00%
5V 9V 12V 15V 20V
10% Loading Efficiency
EU CoC Rev.05-Tier2 Limit 230Vac Input 115Vac Input
78.00%
80.00%
82.00%
84.00%
86.00%
88.00%
90.00%
92.00%
94.00%
5V 9V 12V 15V 20V
4 Points Average Efficiency
EU CoC Rev.05-Tier2 Limit 230Vac Input 115Vac Input
Efficiency performance VS. EU CoC Rev 05- Tier2 Limitation
65W ACF USB PD adaptor typical waveform
19
Normal Operation Valley Skipping Burst Mode
From full load to light load
ACF work in valley skipping and Burst mode for light load efficiency
improvement
65W ACF USB PD adaptor typical waveform
20
Primary GaN waveformxs Primary GaN ZVS operation
230VAC 20V/1.5A
65W ACF USB PD adaptor typical waveform
21CH1: SR-VDS CH2: Primary VDS
• No oscillation to SR
MOSFET
• max. stress is
Vin*𝜋/n + Vout=82V
• 100Vds MOSFET
can be used
230VAC 20V/3.25A
MASTERGAN gate drive logic inputs – truth table
22
Disabled input port
Normal Operation
Configurations
Interlocking
Normal Operation Interlock Input disabled
HIN
LIN
GH
GL
SD/OD
Logic inputs – interlocking
23
HIN
LIN
GL
OUT
HIN and LIN high never occurs, normal condition HIN and LIN high in black square → Interlock
GL and GH are both low• When Interlock condition is applied to the input, the active
driver is shut down after T(OFF)
• When Interlock condition is removed from the input, the new
input configuration is applied on the output after T(OFF)
MASTERGAN interlocking feature prevents simultaneous activation
of high side and low side
Tips of noise prevent in PCB layout
24
• VCC Filter caps placed to close VCC-GND Pins
Preventing noise in PCB layout
25• Keep signals traces away from OUT trace
• Keep bulk voltage—transformer-OUT-SENSE-GND loop as small as possible
dv/dt adjustment
26
• During the design of power converters, the adjustment of middle point
dv/dt of OUT pin is important to:
• Reduce EMI
• To avoid undesired oscillations when parasitic elements cannot be further minimized
• Reduce secondary side stress
dv/dt adjustment - adding cap on GaN’s gate
27
• Adding a capacitor between GL (GH) and PGND (OUTb),
is equivalent to increase GaN’s Gate Charge
• Maximum value must be found to avoid driver’s dynamical
overstress and considering the operating frequency Fsw
• CGx<80mW/(Pvcc^2*Fsw)-(330pF)
PROs CONs
Fine tuning of the obtained effect
High repeatability of the effect thanks to the
accuracy of the available discrete components
Effect is also on EMI associated with normal
operation
Additional operating consumption to PVCC and Vbo,
especially at high frequency
Not suitable for very high frequency solutions
Cpvcc CGL
Cboot CGH
Adding a resistor on PVCC
28
• A resistor in series with
PVCC or VBO
decreases the driving
current. A very short
drop is evident on PVCC
/ VBO at driver turn on
PROs CONs
Fine tuning of the obtained effect
High repeatability of the effect thanks to the
accuracy of the available discrete components
Effect is also on EMI associated with normal
operation
PVCC / VBO drop can increase the propagation delay
Short-on time can result into worse Rdson because of the
reduced Gan’s gate overdrive voltage (i.e., PVCC-Vgsth)
Duration of VBO drop must be shorter than 2 µs to
prevent UVLO activation Cpvcc
CbootRbo
Rpvcc
RGON
H
RGOFF
H
0
20
40
60
80
100
120
140
0 20 40 60 80 100 120 140 160 180 200 220
Slo
pe
(V
/ns)
RPVCC (or RVBO)
dV/dt turn on slope
Tj=0°C
Tj=25°C
Tj=100°C
Tj=125°C
• An RC network feedback can be added between
OUT node and GL in order to reduce the GL voltage
in case of intense negative dv/dt.
• Consider using PCB, especially for thin PCBs,
instead of the added Ck
• Example
• 0.8mm 4-layer PCB, 0.1mm inner core thickness, εr=4.4
• 10pF -> 30mm2: can fit below MasterGaN
dv/dt adjustment - adding dv/dt killer
29
PROs CONs
Acts on high dV/dt only: the dV/dt value is then
balanced over entire operating conditionsHigh voltage component needed
Cpvcc
Ck
CbootCGH
Rdamp
• The value of the Capacitor (Ck) limits the dv/dt during hard switching thanks to
Miller effect
• During turn on the rate is limited to ~𝑉𝑃𝑉𝐶𝐶−𝑉𝑇𝐻
𝑅𝑂𝑁𝐺𝐶𝑘=
𝑉𝑃𝑉𝐶𝐶−1.7
50∙𝐶𝑘
• During turn off, it is limited to ~𝑉𝑇𝐻
𝑅𝑂𝐹𝐹𝐺𝐶𝑘=
0.85
𝐶𝑘
• A resistor in series is required to avoid oscillations due to stray inductance
• 𝑅𝐷𝐴𝑀𝑃 ≫𝐿𝑠𝑡𝑟𝑎𝑦
𝐶𝑘
• Capacitor required is typically 5pF to 10pF (600V rated)
• E.g.: Using PVCC = 6V and max dv/dt = 10V/ns → Ck = 8.6pF
Adding dv/dt limiter – design tips
30
Waveform comparison with dv/dt killer
31
Originaldv/dt equal to 37V/ns
With dv/dt limiter cap 10pF / 200Ω
dv/dt limited to 6V/ns
Startup waveform for 230Vac
Original dv/dt of 37V/ns falls to 6V/ns
dv/dt adjustment – typical waveforms
32
Turn on: 1.85V/nS Turn off: 6.6V/nS
Example of 65W demo: Rpvcc=15Ω, Cg=470pF, R43=200Ω, C57=10pF
220V/50Hz input, 20V/3.25A output
ST solutions with MasterGaN
MASTERGAN1
NO Heat Sink REQUIRED!
L6599A
24Vout
3.8 cm2 1.53 cm2
-60% space occupation
200W TM PFC+LLC
Gaming AdaptorSTCMB1 + MasterGaN1
EVLMG1-250WLLC evaluation board
350W+150W Ultra Slim LLC
OLED TV ApplicationL6599A + MasterGaN1
33
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