© 2005 Altera Corporation

SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs

SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs

Kerry VeenstraWorkshop on Architecture Research

using FPGA Platforms, 2005

Kerry VeenstraWorkshop on Architecture Research

using FPGA Platforms, 2005

© 2005 Altera Corporation

Altera’s SOPC BuilderAltera’s SOPC Builder

Supports Rapid System Prototyping Performs the Mundane Tasks of System

Integration Allows Focus on the System Architecture Generates Verilog & VHDL Systems That

Run on ModelSim and FPGAs Generated Interconnect is Correct by Design

© 2005 Altera Corporation

Embedded System IntegrationEmbedded System IntegrationProcessor

(Bus Master) 32-Bit

© 2005 Altera Corporation

Embedded System IntegrationEmbedded System IntegrationProcessor

(Bus Master) 32-Bit

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

© 2005 Altera Corporation

Embedded System IntegrationEmbedded System Integration

Ad

dress

Processor (Bus Master)

32-Bit

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

© 2005 Altera Corporation

Embedded System IntegrationEmbedded System Integration

Ad

dress

Address Decoder

Processor (Bus Master)

32-Bit

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

© 2005 Altera Corporation

Data

Embedded System IntegrationEmbedded System Integration

Ad

dress

Address Decoder

Processor (Bus Master)

32-Bit

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

© 2005 Altera Corporation

Data

Embedded System IntegrationEmbedded System Integration

Ad

dress

Address Decoder

Processor (Bus Master)

32-Bit

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

Width-Match Width-MatchWidth-MatchWidth-Match Width-Match

© 2005 Altera Corporation

Data

Embedded System IntegrationEmbedded System Integration

Ad

dress

Address Decoder

Processor (Bus Master)

32-BitInterrupt

Controller

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

Width-Match Width-MatchWidth-MatchWidth-Match Width-Match

© 2005 Altera Corporation

Data

Embedded System IntegrationEmbedded System Integration

Ad

dress

Address Decoder

Processor (Bus Master)

32-BitInterrupt

Controller

Ad

dress

Data

Ethernet (Bus Master)

32-Bit

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

Width-Match Width-MatchWidth-MatchWidth-Match Width-Match

© 2005 Altera Corporation

Data

Embedded System IntegrationEmbedded System Integration

Ad

dress

Address Decoder

Processor (Bus Master)

32-BitInterrupt

Controller

Ad

dress

Data

Ethernet (Bus Master)

32-Bit

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

Arbiter

Width-Match Width-MatchWidth-MatchWidth-Match Width-Match

© 2005 Altera Corporation

Data

Embedded System IntegrationEmbedded System Integration

Ad

dress

Address Decoder

Processor (Bus Master)

32-BitInterrupt

Controller

Ad

dress

Data

Ethernet (Bus Master)

32-Bit

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

Arbiter

Width-Match Width-MatchWidth-MatchWidth-Match Width-Match

Clock 1 Clock 2

© 2005 Altera Corporation

Data

Embedded System IntegrationEmbedded System Integration

Ad

dress

Address Decoder

Processor (Bus Master)

32-BitInterrupt

Controller

Ad

dress

Data

Ethernet (Bus Master)

32-Bit

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

Arbiter

Bus Interface Bus InterfaceBus InterfaceBus Interface Bus Interface

Bus Interface Bus Interface

DesignedManually

© 2005 Altera Corporation

SOPC Builder IntegrationSOPC Builder IntegrationProcessor

(Bus Master) 32-Bit

Ethernet (Bus Master)

32-Bit

© 2005 Altera Corporation

SOPC Builder IntegrationSOPC Builder IntegrationProcessor

(Bus Master) 32-Bit

Ethernet (Bus Master)

32-Bit

Slave 18-Bit

Slave 232-Bit

Slave 316-Bit

Slave 432-Bit

Slave 564-Bit

© 2005 Altera Corporation

Width-Match

Interrupt Controller

Address Decoder

Arbiter

Width-Match

Arbiter

Width-Match

Arbiter

Width-Match

Arbiter

Width-Match

Arbiter

SOPC Builder- GeneratedAvalon™

Switch Fabric

Wait-State Generation

Data Multiplexing

SOPC Builder IntegrationSOPC Builder IntegrationProcessor

(Bus Master) 32-Bit

Ethernet (Bus Master)

32-Bit

Slave 18-Bit

Slave 232-Bit

Slave 316-Bit

Slave 432-Bit

Slave 564-Bit

© 2005 Altera Corporation

DevelopmentBoard

SOPC Builder: Design Flow

17

Verilogor

VHDL

Quartus II

IntegratedDevelopmentEnvironment

SystemDescription

SOPC Builder

ModelSim

C/C++Header

perMaster

GenerateImport

SOF

Hex

Debug

© 2005 Altera Corporation

DevelopmentBoard

SOPC Builder & IDE

18

Verilogor

VHDL

Quartus II

IntegratedDevelopmentEnvironment

SystemDescription

SOPC Builder

ModelSim

C/C++Header

perMaster

GenerateImport

SOF

Hex

Debug

© 2005 Altera Corporation

DevelopmentBoard

Targets: ModelSim & FPGA

19

Verilogor

VHDL

Quartus II

IntegratedDevelopmentEnvironment

SystemDescription

SOPC Builder

ModelSim

C/C++Header

perMaster

GenerateImport

SOF

Hex

Debug

© 2005 Altera Corporation

DevelopmentBoard

SOPC Builder System Editor

20

Verilogor

VHDL

Quartus II

IntegratedDevelopmentEnvironment

SystemDescription

SOPC Builder

ModelSim

C/C++Header

perMaster

GenerateImport

SOF

Hex

Debug

© 2005 Altera Corporation

SOPC Builder System EditorSOPC Builder System Editor

© 2005 Altera Corporation

SOPC Builder System EditorSOPC Builder System Editor

Component

© 2005 Altera Corporation

SOPC Builder System EditorSOPC Builder System Editor

Connection Panel

Component

© 2005 Altera Corporation

SOPC Builder System EditorSOPC Builder System Editor

Address MapConnection Panel Address Map

Component

© 2005 Altera Corporation

SOPC Builder System EditorSOPC Builder System EditorIRQ Priorities

Address Map

Clock Domains

Connection Panel Address Map

Component

© 2005 Altera Corporation

DevelopmentBoard

Import HDL (Optional)

26

Verilogor

VHDL

Quartus II

IntegratedDevelopmentEnvironment

SystemDescription

SOPC Builder

ModelSim

C/C++Header

perMaster

GenerateImport

SOF

Hex

Debug

© 2005 Altera Corporation

DevelopmentBoard

Generate HDL and C/C++ Headers

27

Verilogor

VHDL

Quartus II

IntegratedDevelopmentEnvironment

SystemDescription

SOPC Builder

ModelSim

C/C++Header

perMaster

GenerateImport

SOF

Hex

Debug

© 2005 Altera Corporation

DevelopmentBoard

Compile Software & Run on ModelSim

28

Verilogor

VHDL

Quartus II

IntegratedDevelopmentEnvironment

SystemDescription

SOPC Builder

ModelSim

C/C++Header

perMaster

GenerateImport

SOF

Hex

Debug

© 2005 Altera Corporation

DevelopmentBoard

DevelopmentBoard

Compile HDL into FPGA

29

Verilogor

VHDL

Quartus II

IntegratedDevelopmentEnvironment

SystemDescription

SOPC Builder

ModelSim

C/C++Header

perMaster

GenerateImport

SOF

Hex

Debug

© 2005 Altera Corporation

DevelopmentBoard

DevelopmentBoard

Compile Software & Run on FPGA

30

Verilogor

VHDL

Quartus II

IntegratedDevelopmentEnvironment

SystemDescription

SOPC Builder

ModelSim

C/C++Header

perMaster

GenerateImport

SOF

Hex

Debug

© 2005 Altera Corporation

Component InterfaceComponent Interface

© 2005 Altera Corporation

Width-Match

Interrupt Controller

Address Decoder

Arbiter

Width-Match

Arbiter

Width-Match

Arbiter

Width-Match

Arbiter

Width-Match

Arbiter

SOPC Builder- GeneratedAvalon™

Switch Fabric

Wait-State Generation

Data Multiplexing

SOPC Builder Component InterfaceSOPC Builder Component InterfaceProcessor

(Bus Master) 32-Bit

Ethernet (Bus Master)

32-Bit

Slave 18-Bit

Slave 232-Bit

Slave 316-Bit

Slave 432-Bit

Slave 564-Bit

© 2005 Altera Corporation

AvalonAvalon

AvalonAvalon Avalon Avalon Avalon

SOPC Builder Component InterfaceSOPC Builder Component InterfaceProcessor

(Bus Master) 32-Bit

Ethernet (Bus Master)

32-Bit

Slave 18-Bit

Slave 232-Bit

Slave 316-Bit

Slave 432-Bit

Slave 564-Bit

© 2005 Altera Corporation

Dynamic Port ConnectionsDynamic Port ConnectionsAvalon Port Types

resetchipselectaddress

byteenableread

readdatawrite

writedatadata

waitrequestreadyfordatadataavailable

datavalidflush

begintransferendofpacket

irqirqnumber

clkresetrequest

All Signals AvailableIn Negative Form

Avalon Port Typesreset

chipselectaddress

byteenableread

readdatawrite

writedatadata

waitrequestreadyfordatadataavailable

datavalidflush

begintransferendofpacket

irqirqnumber

clkresetrequest

All Signals AvailableIn Negative Form

Avalon Is a Superset of Bus Interfaces

ISA, Wishbone

Many Port Types Supported

Peripheral Uses Only the Ports It Needs

Any Combination of Ports Is Possible

Avalon Switch Logic Controls Signal Timing

Supports Arbitrary Setup Time, Hold Time &

Wait States

Simplifies Peripheral Design

© 2005 Altera Corporation

Traditional Buses: Master ArbitrationTraditional Buses: Master Arbitration

System CPU(Master 1)

I/O1Program

Memory

Slaves

Shared BusShared Bus

DataMemory

ArbiterArbiter

DataMemory

DSP(Master 2)

I/O1

Masters

Slaves

I/O CPU(Master 3)

I/O3

ProgramMemory

DataMemory

CustomAccelerator Peripheral

SystemBottleneck

© 2005 Altera Corporation

SOPC Builder: Slave-Side ArbitrationSOPC Builder: Slave-Side Arbitration

System CPU(Master 1)

I/O1Program

Memory

Slaves DataMemory

ArbiterArbiter

DataMemory

AribiterAribiter

DSP(Master 2)

I/O1

Masters

Slaves

Switch Fabric

I/O CPU(Master 3)

I/O3

ProgramMemory

DataMemory

ArbiterArbiter

CustomAccelerator Peripheral

© 2005 Altera Corporation

SOPC Builder: Slave-Side ArbitrationSOPC Builder: Slave-Side Arbitration

System CPU(Master 1)

I/O1Program

Memory

Slaves DataMemory

ArbiterArbiter

DataMemory

AribiterAribiter

DSP(Master 2)

I/O1

Masters

Slaves

Switch Fabric

I/O CPU(Master 3)

I/O3

ProgramMemory

DataMemory

ArbiterArbiter

Simultaneous Operation for All Masters

CustomAccelerator Peripheral

© 2005 Altera Corporation

Altera’s SOPC BuilderAltera’s SOPC Builder

Supports Rapid System Prototyping Performs the Mundane Tasks of System

Integration Allows Focus on the System Architecture Generates Verilog & VHDL Systems That

Run on ModelSim and FPGAs Generated Interconnect is Correct by Design

© 2005 Altera Corporation

System Interconnect

Connecting Masters & SlavesConnecting Masters & Slaves

DynamicBus

Sizing

Master

Master

Arbiter

Master

Clock Domain

Xing

Streaming

Master

Arbiter

Latency

SlaveArbiter

32-b

it16

-bit

16-b

it

Clock 1

Clock 2