© 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry...

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© 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA Platforms, 2005

Transcript of © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry...

Page 1: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs

SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs

Kerry VeenstraWorkshop on Architecture Research

using FPGA Platforms, 2005

Kerry VeenstraWorkshop on Architecture Research

using FPGA Platforms, 2005

Page 2: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

Altera’s SOPC BuilderAltera’s SOPC Builder

Supports Rapid System Prototyping Performs the Mundane Tasks of System

Integration Allows Focus on the System Architecture Generates Verilog & VHDL Systems That

Run on ModelSim and FPGAs Generated Interconnect is Correct by Design

Page 3: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

Embedded System IntegrationEmbedded System IntegrationProcessor

(Bus Master) 32-Bit

Page 4: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

Embedded System IntegrationEmbedded System IntegrationProcessor

(Bus Master) 32-Bit

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

Page 5: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

Embedded System IntegrationEmbedded System Integration

Ad

dress

Processor (Bus Master)

32-Bit

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

Page 6: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

Embedded System IntegrationEmbedded System Integration

Ad

dress

Address Decoder

Processor (Bus Master)

32-Bit

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

Page 7: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

Data

Embedded System IntegrationEmbedded System Integration

Ad

dress

Address Decoder

Processor (Bus Master)

32-Bit

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

Page 8: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

Data

Embedded System IntegrationEmbedded System Integration

Ad

dress

Address Decoder

Processor (Bus Master)

32-Bit

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

Width-Match Width-MatchWidth-MatchWidth-Match Width-Match

Page 9: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

Data

Embedded System IntegrationEmbedded System Integration

Ad

dress

Address Decoder

Processor (Bus Master)

32-BitInterrupt

Controller

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

Width-Match Width-MatchWidth-MatchWidth-Match Width-Match

Page 10: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

Data

Embedded System IntegrationEmbedded System Integration

Ad

dress

Address Decoder

Processor (Bus Master)

32-BitInterrupt

Controller

Ad

dress

Data

Ethernet (Bus Master)

32-Bit

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

Width-Match Width-MatchWidth-MatchWidth-Match Width-Match

Page 11: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

Data

Embedded System IntegrationEmbedded System Integration

Ad

dress

Address Decoder

Processor (Bus Master)

32-BitInterrupt

Controller

Ad

dress

Data

Ethernet (Bus Master)

32-Bit

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

Arbiter

Width-Match Width-MatchWidth-MatchWidth-Match Width-Match

Page 12: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

Data

Embedded System IntegrationEmbedded System Integration

Ad

dress

Address Decoder

Processor (Bus Master)

32-BitInterrupt

Controller

Ad

dress

Data

Ethernet (Bus Master)

32-Bit

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

Arbiter

Width-Match Width-MatchWidth-MatchWidth-Match Width-Match

Clock 1 Clock 2

Page 13: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

Data

Embedded System IntegrationEmbedded System Integration

Ad

dress

Address Decoder

Processor (Bus Master)

32-BitInterrupt

Controller

Ad

dress

Data

Ethernet (Bus Master)

32-Bit

Slave 316-Bit

Slave 18-Bit

Slave 564-Bit

Slave 432-Bit

Slave 232-Bit

Arbiter

Bus Interface Bus InterfaceBus InterfaceBus Interface Bus Interface

Bus Interface Bus Interface

DesignedManually

Page 14: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

SOPC Builder IntegrationSOPC Builder IntegrationProcessor

(Bus Master) 32-Bit

Ethernet (Bus Master)

32-Bit

Page 15: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

SOPC Builder IntegrationSOPC Builder IntegrationProcessor

(Bus Master) 32-Bit

Ethernet (Bus Master)

32-Bit

Slave 18-Bit

Slave 232-Bit

Slave 316-Bit

Slave 432-Bit

Slave 564-Bit

Page 16: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

Width-Match

Interrupt Controller

Address Decoder

Arbiter

Width-Match

Arbiter

Width-Match

Arbiter

Width-Match

Arbiter

Width-Match

Arbiter

SOPC Builder- GeneratedAvalon™

Switch Fabric

Wait-State Generation

Data Multiplexing

SOPC Builder IntegrationSOPC Builder IntegrationProcessor

(Bus Master) 32-Bit

Ethernet (Bus Master)

32-Bit

Slave 18-Bit

Slave 232-Bit

Slave 316-Bit

Slave 432-Bit

Slave 564-Bit

Page 17: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

DevelopmentBoard

SOPC Builder: Design Flow

17

Verilogor

VHDL

Quartus II

IntegratedDevelopmentEnvironment

SystemDescription

SOPC Builder

ModelSim

C/C++Header

perMaster

GenerateImport

SOF

Hex

Debug

Page 18: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

DevelopmentBoard

SOPC Builder & IDE

18

Verilogor

VHDL

Quartus II

IntegratedDevelopmentEnvironment

SystemDescription

SOPC Builder

ModelSim

C/C++Header

perMaster

GenerateImport

SOF

Hex

Debug

Page 19: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

DevelopmentBoard

Targets: ModelSim & FPGA

19

Verilogor

VHDL

Quartus II

IntegratedDevelopmentEnvironment

SystemDescription

SOPC Builder

ModelSim

C/C++Header

perMaster

GenerateImport

SOF

Hex

Debug

Page 20: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

DevelopmentBoard

SOPC Builder System Editor

20

Verilogor

VHDL

Quartus II

IntegratedDevelopmentEnvironment

SystemDescription

SOPC Builder

ModelSim

C/C++Header

perMaster

GenerateImport

SOF

Hex

Debug

Page 21: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

SOPC Builder System EditorSOPC Builder System Editor

Page 22: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

SOPC Builder System EditorSOPC Builder System Editor

Component

Page 23: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

SOPC Builder System EditorSOPC Builder System Editor

Connection Panel

Component

Page 24: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

SOPC Builder System EditorSOPC Builder System Editor

Address MapConnection Panel Address Map

Component

Page 25: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

SOPC Builder System EditorSOPC Builder System EditorIRQ Priorities

Address Map

Clock Domains

Connection Panel Address Map

Component

Page 26: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

DevelopmentBoard

Import HDL (Optional)

26

Verilogor

VHDL

Quartus II

IntegratedDevelopmentEnvironment

SystemDescription

SOPC Builder

ModelSim

C/C++Header

perMaster

GenerateImport

SOF

Hex

Debug

Page 27: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

DevelopmentBoard

Generate HDL and C/C++ Headers

27

Verilogor

VHDL

Quartus II

IntegratedDevelopmentEnvironment

SystemDescription

SOPC Builder

ModelSim

C/C++Header

perMaster

GenerateImport

SOF

Hex

Debug

Page 28: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

DevelopmentBoard

Compile Software & Run on ModelSim

28

Verilogor

VHDL

Quartus II

IntegratedDevelopmentEnvironment

SystemDescription

SOPC Builder

ModelSim

C/C++Header

perMaster

GenerateImport

SOF

Hex

Debug

Page 29: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

DevelopmentBoard

DevelopmentBoard

Compile HDL into FPGA

29

Verilogor

VHDL

Quartus II

IntegratedDevelopmentEnvironment

SystemDescription

SOPC Builder

ModelSim

C/C++Header

perMaster

GenerateImport

SOF

Hex

Debug

Page 30: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

DevelopmentBoard

DevelopmentBoard

Compile Software & Run on FPGA

30

Verilogor

VHDL

Quartus II

IntegratedDevelopmentEnvironment

SystemDescription

SOPC Builder

ModelSim

C/C++Header

perMaster

GenerateImport

SOF

Hex

Debug

Page 31: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

Component InterfaceComponent Interface

Page 32: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

Width-Match

Interrupt Controller

Address Decoder

Arbiter

Width-Match

Arbiter

Width-Match

Arbiter

Width-Match

Arbiter

Width-Match

Arbiter

SOPC Builder- GeneratedAvalon™

Switch Fabric

Wait-State Generation

Data Multiplexing

SOPC Builder Component InterfaceSOPC Builder Component InterfaceProcessor

(Bus Master) 32-Bit

Ethernet (Bus Master)

32-Bit

Slave 18-Bit

Slave 232-Bit

Slave 316-Bit

Slave 432-Bit

Slave 564-Bit

Page 33: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

AvalonAvalon

AvalonAvalon Avalon Avalon Avalon

SOPC Builder Component InterfaceSOPC Builder Component InterfaceProcessor

(Bus Master) 32-Bit

Ethernet (Bus Master)

32-Bit

Slave 18-Bit

Slave 232-Bit

Slave 316-Bit

Slave 432-Bit

Slave 564-Bit

Page 34: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

Dynamic Port ConnectionsDynamic Port ConnectionsAvalon Port Types

resetchipselectaddress

byteenableread

readdatawrite

writedatadata

waitrequestreadyfordatadataavailable

datavalidflush

begintransferendofpacket

irqirqnumber

clkresetrequest

All Signals AvailableIn Negative Form

Avalon Port Typesreset

chipselectaddress

byteenableread

readdatawrite

writedatadata

waitrequestreadyfordatadataavailable

datavalidflush

begintransferendofpacket

irqirqnumber

clkresetrequest

All Signals AvailableIn Negative Form

Avalon Is a Superset of Bus Interfaces

ISA, Wishbone

Many Port Types Supported

Peripheral Uses Only the Ports It Needs

Any Combination of Ports Is Possible

Avalon Switch Logic Controls Signal Timing

Supports Arbitrary Setup Time, Hold Time &

Wait States

Simplifies Peripheral Design

Page 35: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

Traditional Buses: Master ArbitrationTraditional Buses: Master Arbitration

System CPU(Master 1)

I/O1Program

Memory

Slaves

Shared BusShared Bus

DataMemory

ArbiterArbiter

DataMemory

DSP(Master 2)

I/O1

Masters

Slaves

I/O CPU(Master 3)

I/O3

ProgramMemory

DataMemory

CustomAccelerator Peripheral

SystemBottleneck

Page 36: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

SOPC Builder: Slave-Side ArbitrationSOPC Builder: Slave-Side Arbitration

System CPU(Master 1)

I/O1Program

Memory

Slaves DataMemory

ArbiterArbiter

DataMemory

AribiterAribiter

DSP(Master 2)

I/O1

Masters

Slaves

Switch Fabric

I/O CPU(Master 3)

I/O3

ProgramMemory

DataMemory

ArbiterArbiter

CustomAccelerator Peripheral

Page 37: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

SOPC Builder: Slave-Side ArbitrationSOPC Builder: Slave-Side Arbitration

System CPU(Master 1)

I/O1Program

Memory

Slaves DataMemory

ArbiterArbiter

DataMemory

AribiterAribiter

DSP(Master 2)

I/O1

Masters

Slaves

Switch Fabric

I/O CPU(Master 3)

I/O3

ProgramMemory

DataMemory

ArbiterArbiter

Simultaneous Operation for All Masters

CustomAccelerator Peripheral

Page 38: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

Altera’s SOPC BuilderAltera’s SOPC Builder

Supports Rapid System Prototyping Performs the Mundane Tasks of System

Integration Allows Focus on the System Architecture Generates Verilog & VHDL Systems That

Run on ModelSim and FPGAs Generated Interconnect is Correct by Design

Page 39: © 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

© 2005 Altera Corporation

System Interconnect

Connecting Masters & SlavesConnecting Masters & Slaves

DynamicBus

Sizing

Master

Master

Arbiter

Master

Clock Domain

Xing

Streaming

Master

Arbiter

Latency

SlaveArbiter

32-b

it16

-bit

16-b

it

Clock 1

Clock 2


Introduction to the Altera SOPC Builder Using Verilog Designs · Introduction to the Altera SOPC ... in the tutorial were obtained using the Quartus II version ... to the Altera SOPC

Introduction to the Altera SOPC Builder Using Verilog Designs · Introduction to the Altera SOPC ... in the tutorial were obtained using the Quartus II version ... to the Altera SOPC

07b SOPC Nios HW Tutorial - iet.unipi.it

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tut sopc introduction vhdl - University of Nebraska–Lincolncse.unl.edu/.../document/altera/start/tut_sopc_introduction_vhdl.pdf · Introduction to the Altera SOPC Builder Using

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Cible matérielle ASIC-FPGA-SOPC

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Introduction to the Altera SOPC Builder Using Verilog …people.ece.cornell.edu/.../Introduction_to_the_Altera_SOPC_Builder.pdfIntroduction to the Altera SOPC Builder Using Verilog

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System on Programmable Chip SoPC for High Performance ... · for High Performance System Applications TM © 2001 Altera Corporation 2 Agenda! Altera SoPC Roadmap ... SOPC Builder

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Developing Peripherals for SOPC Builder

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Introduction to the Altera SOPC Builder Using VHDL … · Introduction to the Altera SOPC Builder Using VHDL Design This tutorial presents an introduction to Altera’s SOPC Builder

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1 SOPC Builder - waveshare

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Veenstra Kenneth__1094__scanned

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DE Conferentie 2008 - Mettina Veenstra

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Jeff Sopc Framework

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Introduction to the Altera SOPC Builder

Introduction to the Altera SOPC Builder

Sopc Booklet

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e2i3 Tp1 Cod Sopc Builder 2012

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11 SOPC Nios Avalon ST - unipi.it Qsys/SOPC&Builder&withoutinserJng&adapters,& Qsys/SOPC&Builder&generates&error&messages& ... 11_SOPC_Nios_Avalon_ST.pptx Author: Federico Baronti

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Connecting a CCD camera to SOPC

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4. SOPC Builder Components - Faculty Websites · Altera Corporation 4 1 May 2006 4. SOPC Builder Components Introduction This chapter describes in detail what an SOPC Builder component

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Introduction to SOPC Buildertqvinh/Lectures/Training_SOPC...Introduction to SOPC Builder Truong Quang Vinh. IT-SoC Lab Truong Quang Vinh Syllabus Class content SOPC VDP system block

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