Simulations of sub-100nm strained Si MOSFETs with high- gate stacks Lianfeng Yang, Jeremy Watling *, Fikru Adamu-Lema, Asen Asenov and John Barker Device.
An Efficient Linear Time Triple Patterning Solver Haitong Tian Hongbo Zhang Zigang Xiao Martin D.F. Wong ASP-DAC’15.
University of Michigan Electrical Engineering and Computer Science 1 StageNet: A Reconfigurable CMP Fabric for Resilient Systems Shantanu Gupta Shuguang.
Triple Patterning Aware Detailed Placement With Constrained Pattern Assignment Haitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D.F. Wong.
Impact of Nanotopography on STI CMP in Future Technologies D. Boning and B. Lee, MIT N. Poduje, ADE Corp. J. Valley, ADE Phase-Shift W. Baylies, Baytech.
8/16/06 1 JEOL JBX-9300FS Electron Beam Lithography System Georgia Tech Microelectronics Research Center Enabling Nanotechnology.
Amplitude and Phase Noise in Nano-scale RF Circuits
Outline
Simulations of sub-100nm strained Si MOSFETs with high- gate stacks
HUBzero™ Cyberinfrastructure for Outreach, Dissemination, and Collaboration Michael McLennan Senior Research Scientist and Hub Software Architect Rosen.
Overview of the HUBzero Platform Michael McLennan Senior Research Scientist and Hub Software Architect Rosen Center for Advanced Computing Purdue University.
Graphene paper
