Zhijie Chen, Masaya Miyahara, and
Akira Matsuzawa
Tokyo Institute of Technology, Japan
A stability-improved single-opamp third-order ΣΔ modulator by using a
fully-passive noise-shaping SAR ADC and passive adder
Matsuzawa
& Okada LabMatsuzawa Lab.Tokyo Institute of Technology
2
Outline
• Motivation
• Traditional implementation
• Proposed architecture
• Circuit and Measurement Results
• Conclusion
3
Outline
• Motivation
• Traditional implementation
• Proposed architecture
• Circuit and Measurement Results
• Conclusion
Motivation
4
• Noise shaping for achieving high resolution
• Usually, 1 opamp --- 1 integrator
• Most of power comes from opamp
• Target: how to reduce power? Reduce No. of opamp?
A sigma delta modulator (SDM) architecture:
X
-Integrators
Y
Quantizer
DAC
101 102 103 104 105 106-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0PSD of Sigma-Delta Modulator
Frequency [Hz]P
SD
[d
B]
Order of Noise
Shaping
Bandwidth
Over-sampling
Rate
Noise shaping
5
Outline
• Motivation
• Traditional implementation
• Proposed architecture
• Circuit and Measurement Results
• Conclusion
Φ1
C1i
C2
Vip
A
Φ1 Φ1
Φ2 Φ1 Φ2
DAC1
VOP
Φ1 Φ2
Φ1
Φ2
Φ2
C4iVOP Φ1 Φ1
DAC1
C3
C5Φ2 Φ2
First Integrator
Second Integrator
Feed-forward
Ф2a Ф2b
Ф2b Ф2a
Ф2a Ф2bФ2b Ф2cФ2c Ф2a
DAC3
Ф1a Ф1b
Ф1b Ф1a
Ф1a Ф1bФ1b Ф1a
Φ1 Φ1
Φ2 C3
DAC2
Φ2 -z-1
1
Ф2Ф1 Ф2Ф1Ф2
n n+1Ф1
n-1
Ф1a Ф1a
Ф1b
Ф2b
Ф2a
Ф2c
An
alo
g:
1-Z
-1
Analog:
1
Analog:
Z-1
DAC1
DAC2
DAC3
RDAC
Single-opamp third-order
6A. Pena-Perez, et al., JSSC 2012
Opamp sharing and error feedback
7
Φ1
C1i
C2
Vip
A
Φ1 Φ1
Φ2 Φ1 Φ2
DAC1
VOP
Φ1 Φ2
Φ1
Φ2
Φ2
C4iVOP Φ1 Φ1
DAC1
C3
C5Φ2 Φ2
First Integrator
Second Integrator
Feed-forward
Ф2a Ф2b
Ф2b Ф2a
Ф2a Ф2bФ2b Ф2cФ2c Ф2a
DAC3
Ф1a Ф1b
Ф1b Ф1a
Ф1a Ф1bФ1b Ф1a
Φ1 Φ1
Φ2 C3
DAC2
Φ2 -z-1
1
Ф2Ф1 Ф2Ф1Ф2
n n+1Ф1
n-1
Ф1a Ф1a
Ф1b
Ф2b
Ф2a
Ф2c
An
alo
g:
1-Z
-1
Analog:
1
Analog:
Z-1
DAC1
DAC2
DAC3
RDAC
Complex clock gen.
RDAC, extra power
Stability during non-overlapped time
8
Φ1
C1i
C2
Vip
A
Φ1 Φ1
Φ2 Φ1 Φ2
DAC1
VOP
Φ1 Φ2
Φ1
Φ2
Φ2
C4iVOP Φ1 Φ1
DAC1
C3
C5Φ2 Φ2
First Integrator
Second Integrator
Feed-forward
Ф2a Ф2b
Ф2b Ф2a
Ф2a Ф2bФ2b Ф2cФ2c Ф2a
DAC3
Ф1a Ф1b
Ф1b Ф1a
Ф1a Ф1bФ1b Ф1a
Φ1 Φ1
Φ2 C3
DAC2
Φ2 -z-1
1
Ф2Ф1 Ф2Ф1Ф2
n n+1Ф1
n-1
Ф1a Ф1a
Ф1b
Ф2b
Ф2a
Ф2c
An
alo
g:
1-Z
-1
Analog:
1
Analog:
Z-1
Non-overlapped
Φ1 Φ2
X X
X X
Unstable issue
3rd order, stability?
Opamp :Open-loop state
9
Outline
• Motivation
• Traditional implementation
• Proposed architecture
• Circuit and Measurement Results
• Conclusion
Architecture
10
Feed-forward architecture
5-bit FPNS SAR ADC, embedded with 1st order NS
A single opamp is shared to realize 2nd order NS
A Passive adder to realize FF addition
NTF(z)Q
X
-Y
DAC DWA
Shaped Quantization Noise
1st
integrator 2nd
integrator
1-z -1=
2z-10.8z
-1
1-z -1=
Qf
A single opamp
5-bit
FPNS SAR
:passive additionNTF(z)=1+0.5z
-11 - 0.5z
-1
-
1st order FPNS SAR ADC
11
Fully passive noise shaping (FPNS) SAR
Suppress non-ideal effects
1st order NS
ФS
N-1
ФNS1
N
ФNS2
ФNS3
X Фs
C1 C2
ФNS1
+
-
C-DAC
+
ФNS3
C3ФNS2
C1=C2=C3
Y
NTF(z)=1+0.5z
-11 - 0.5z
-1
Noise transfer function (NTF):
Z. Chen, et al., VLSIC 2015
NTF(z)Q
X
-Y
DAC
Shaped Quantization Noise
1st
integrator 2nd
integratorQ
f
A single opamp
5-bit
FPNS SAR
-
A single-opamp 2nd order NS
12
An opamp sharing technique:
Additional SC:
Solve stability issue
X
-
1st
integrator 2nd
integrator
A single opamp
-
Y
Φ1
C4
C5
X
A
Φ1 Φ1
Φ2 Φ1 Φ2
Φ1 Φ2
Y
VOP
Φ1 Φ2
Φ1
Φ2
Φ2
C7VOP Φ1 Φ1
Y
C6
C8Φ2 Φ2
First Integrator
Second Integrator
Feed-forward Additional SC
Non-overlapped
Φ1 Φ2 Φ1 Φ2
C4 & C5: 1st integrator
C7 & C8: 2nd integrator
C6: Feed-forward
A passive adder
13
A passive adder by capacitor:
Passive, save power
Differential signal:
Input: XP & XN;
Opamp output: VOP,P & VOP,N;
XN
VOP,P
=VOP,P-XN
XP
VOP,N
=VOP,N-XP
VOP,P+XP=VOP,P-XN VOP,N+XN=VOP,N-XP
X
VOP
XP + VOP,P
XN+ VOP,N
Z. Chen, et al., A-SSCC 2012
14
Outline
• Motivation
• Traditional implementation
• Proposed architecture
• Circuit and Measurement Results
• Conclusion
The schematic
15
Y(z)=X(z)+(1+0.5z
-1)(1+0.6z
-2)
(1 - 0.5z-1
)(1-z-1
)2No RDAC, save power
Only two non-overlapped clocks
No stability issue
FPi&Φ1
C4i
C5
Vip
A
Φ1 Φ1
Φ2 Φ1 Φ2
Φ1 Φ2
REFP REFN
FNi&Φ1
VOP
Φ1 Φ2
Φ1
Φ2
FPi&Φ2
C7iVOP Φ1 Φ1
REFP REFN
FNi&Φ2
C6
C8Φ2 Φ2
First Integrator
Second Integrator
Feed-forward Additional SC
Non-overlapped
Φ1 Φ2 Φ1 Φ2
ANALOG DIGITAL
+
-+
Φ2
5-bit FPNS SAR ADC Th
erm
om
ete
r
De
co
de
r
DW
A
FPi
FNi
i=1,2,…,30,31
REFP REFN
VOP,P
XN
REFP REFN
VOP,N
XP
Passive addition
The opamp
16
Current mirror opamp:
1
1
4
3
2
3
1
2 1
/
/
/
/
m out
m
L
BGain g R
g BGBW
C
W LB
W L
W L
W L
Single stage, save power
[J. Roh, et al., JSSC 2008]
AVDD
I0
VipVOP VON
CMFB
Vin
AVSS
M1 M1
M2M3 M3
M4 M4
M5 M5M9
M8
M7M6
VB
Chip photo
• CMOS 65 nm, core area: 0.097 mm2
17336.6 µm
28
7.9
µm
CL
KFPNS SAR ADC
Op
am
p
DW
A
1
6
2 5
43
6
5
4
1: 1st
sample cap
2: 2nd
sample cap
3: Feed-forward cap
4: 1st
int. cap
5: 2nd
int. cap
6: additional SC
1 2
3
The measured PSD
18
Peak SNDR: 74.9 dB; DR: 78 dB
103 104 105 106-140
-120
-100
-80
-60
-40
-20
0
PS
D (
dB
)
Frequency (Hz)
Power Spectral Density
BW = 100 kHz
60dB/Dec
SNDR = 74.94 dB ENOB = 12.16 bits
Fin = 9.95 kHz
OSR = 16 Fs = 3.2 MHz
-80 -60 -40 -20 0
0
10
20
30
40
50
60
70
DR=78 dB
Input signal @ 10kHz
-3 dBFS
Full scale = 1 V
SN
DR
(d
B)
Input amplitude (dBFS)
Analog power supply: 0.7 V; Digital power supply: 0.85 V
Performance Comparison
19[1] A. Pena-Perez, et al., JSSC 2012
[4] C. Briseno-Vidrios, et al., VLSIC 2015
[5] T. Kim, et al., VLSIC 2015
The fewer No. of opamp is, the lower power is.
20
Outline
• Motivation
• Traditional implementation
• Proposed architecture
• Circuit and Measurement Results
• Conclusion
Conclusion
• A single-opamp third-order SDM is introduced
– 74.9 dB SNDR, 3.2-MHz Fs, 50 fJ/Con.-step
FoMW, 168 dB FoMS
– An opamp is sharing to realize 2nd order noise
shaping
– Stability is improved
– Power efficiency is enhanced
21
Acknowledgement
22
This work was partially supported by MIC,
HUAWEI, Mentor Graphics for the use of the
Analog FastSPICE(AFS) Platform, and VDEC in
collaboration with Cadence Design Systems,
Inc, Synopsys, Inc.
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