Static Timing Analysis Overview

Static timing analysis is a method of validating the timing performance of a design by checking all possible

paths for timing violations. PrimeTime checks for violations in the same way that you would do it manually, but

with much greater speed and accuracy.

To check a design for violations, PrimeTime breaks the design down into a set of timing paths, calculates the

signal propagation delay along each path, and checks for violations of timing constraints inside the design and

at the input/output interface.

Another way to perform timing analysis is to use dynamic simulation, which determines the full behavior of the

circuit for a given set of input stimulus vectors. Compared with dynamic simulation, static timing analysis is

much faster because it is not necessary to simulate the logical operation of the circuit. It is also more thorough

because it checks all timing paths, not just the logical conditions that are sensitized by a particular set of test

vectors. However, static timing analysis can only check the timing, not the functionality, of a circuit design.

Timing Paths

The first step performed by PrimeTime for timing analysis is to break the design down into a set of timing

paths. Each path has a startpoint and an endpoint. The startpoint is a place in the design where data is launched

by a clock edge. The data is propagated through combinational logic in the path and then captured at the

endpoint by another clock edge.

The startpoint of a path is a clock pin of a sequential element, or possibly an input port of the design (because

the input data can be launched from some external source). The endpoint of a path is a data input pin of a

sequential element, or possibly an output port of the design (because the output data can be captured by some

external sink).

Figure 1-4 shows an example of a simple design and the data paths contained in that design.

Figure 1-4 Timing Paths

In this figure, each logic cloud represents a combinational logic network. Each path starts at a data launch point,

passes through some combinational logic, and ends at a data capture point:

Path 1 starts at an input port and ends at the data input of a sequential element.

Path 2 starts at the clock pin of a sequential element and ends at the data input of a sequential element.

Path 3 starts at the clock pin of a sequential element and ends at an output port.

Path 4 starts at an input port and ends at an output port.

A combinational logic cloud might contain multiple paths, as illustrated in Figure 1-5. PrimeTime uses the

longest path to calculate a maximum delay or the shortest path to calculate a minimum delay.

Figure 1-5 Multiple Paths Through Combinational Logic

In addition to the data paths just described, PrimeTime considers other types of paths for timing analysis, such

as the following:

Clock path (a path from a clock input port or cell pin, through one or more buffers or inverters, to the

clock pin of a sequential element) for data setup and hold checks

Clock-gating path (a path from an input port to a clock-gating element) for clock-gating setup and hold

checks

Asynchronous path (a path from an input port to an asynchronous set or clear pin of a sequential

element) for recovery and removal checks

Figure 1-6 shows some examples of these types of paths.

Figure 1-6 Path Types

Delay Calculation

After breaking down a design into a set of timing paths, PrimeTime calculates the delay along each path. The

total delay of a path is the sum of all cell and net delays in the path.

The method of delay calculation depends on whether chip layout has been completed. Before layout, the chip

topography is unknown, so PrimeTime must estimate the net delays using wire load models.

After layout, an external tool can accurately determine the delays and write them to a Standard Delay Format

(SDF) file. PrimeTime can read the SDF file and back-annotate the design with the delay information for

layout-accurate timing analysis. PrimeTime can also accept a detailed description of parasitic capacitors and

resistors in the interconnection network, and then accurately calculate net delays based on that information.

Cell Delay

Cell delay is the amount of delay from input to output of a logic gate in a path. In the absence of back-annotated

delay information from an SDF file, PrimeTime calculates the cell delay from delay tables provided in the

technology library for the cell.

Typically, a delay table lists the amount of delay as a function of one or more variables, such as input transition

time and output load capacitance. Based on these table entries, PrimeTime calculates each cell delay. When

necessary, PrimeTime uses interpolation or extrapolation of table values to obtain a delay value for the current

conditions specified for the design.

Net Delay

Net delay is the amount of delay from the output of a cell to the input of the next cell in a timing path. This

delay is caused by the parasitic capacitance of the interconnection between the two cells, combined with net

resistance and the limited drive strength of the cell driving the net.

PrimeTime can calculate net delays by the following methods:

By using specific time values back-annotated from an SDF file

By using detailed parasitic resistance and capacitance data back-annotated from file in RSPF, SPEF, or

SBPF format

By estimating delays from a wire load model

A wire load model attempts to predict the capacitance and resistance of nets in the absence of back-annotated

delay information or parasitic data. The technology library provides statistical wire load models for estimating

parasitic resistance and capacitance based on the number of fanout pins on each net.

Constraint Checking

After PrimeTime determines the timing paths and calculates the path delays, it can check for violations of

timing constraints, such as setup and hold constraints.

A setup constraint specifies how much time is necessary for data to be available at the input of a sequential

device before the clock edge that captures the data in the device. This constraint enforces a maximum delay on

the data path relative to the clock path.

A hold constraint specifies how much time is necessary for data to be stable at the input of a sequential device

after the clock edge that captures the data in the device. This constraint enforces a minimum delay on the data

path relative to the clock path.

In addition to setup and hold constraints, PrimeTime can also check recovery/removal constraints, data-to-data

constraints, clock-gating setup/hold constraints, and minimum pulse width for clock signals.

The amount of time by which a violation is avoided is called the slack. For example, for a setup constraint, if a

signal must reach a cell input at no later than 8 ns and is determined to arrive at 5 ns, the slack is 3 ns. A slack

of 0 means that the constraint is just barely satisfied. A negative slack indicates a timing violation.

Setup and Hold Checking for Flip-Flops

Figure 1-7 shows how PrimeTime checks setup and hold constraints for a flip-flop in the absence of timing

exceptions that apply to the data path.

Figure 1-7 Setup and Hold Checks

For this example, assume that the flip-flops are defined in the technology library to have a minimum setup time

of 1.0 time units and a minimum hold time of 0.0 time units. The clock period is defined in PrimeTime to be 10

time units. (The time unit size, such as ns or ps, is specified in the technology library.)

By default, PrimeTime assumes that signals are to be propagated through each data path in one clock cycle.

Therefore, when PrimeTime performs a setup check, it verifies that the data path delay is small enough so that

the data launched from FF1 reaches FF2 within one clock cycle, and arrives at least 1.0 time unit before the data

gets captured by the next clock edge at FF2. If the data path delay is too long, it is reported as a timing

violation. For this setup check, PrimeTime considers the longest possible delay along the data path and the

shortest possible delay along the clock path between FF1 and FF2.

When PrimeTime performs a hold check, it verifies that the data launched from FF1 reaches FF2 no sooner than

the capture clock edge for the previous clock cycle. This check ensures that the data already existing at the input

of FF2 remains stable long enough after the clock edge that captures data for the previous cycle. For this hold

check, PrimeTime considers the shortest possible delay along the data path and the longest possible delay along

the clock path between FF1 and FF2. A hold violation can occur if the clock path has a long delay.

Note:

For more examples of setup and hold calculations, including paths that use different clocks at the path startpoint

and endpoint, see Chapter 9, “Timing Exceptions.”

Setup and Hold Checking for Latches

Latch-based designs typically use two-phase, nonoverlapping clocks to control successive registers in a data

path. In these cases, PrimeTime can use time borrowing to lessen the constraints on successive paths. For

example, consider the two-phase, latch-based path shown in Figure 1-8. All three latches are level-sensitive,

with the gate active when the G input is high. L1 and L3 are controlled by PH1, and L2 is controlled by PH2. A

rising edge launches data from the latch output, and a falling edge captures data at the latch input. For this

example, consider the latch setup and delay times to be zero.

Figure 1-8 Latch-Based Paths

Figure 1-9 shows how PrimeTime performs setup checks between these latches. For the path from L1 to L2, the

rising edge of PH1 launches the data. The data must arrive at L2 before the closing edge of PH2 at time=20.

This timing requirement is labeled Setup 1. Depending on the amount of delay between L1 and L2, the data

might arrive either before or after the opening edge of PH2 (at time=10), as indicated by the dashed-line arrows

in the timing diagram. Arrival after time=20 would be a timing violation.

Figure 1-9 Time Borrowing in Latch-Based Paths

If the data arrives at L2 before the opening edge of PH2 at time=10, the data for the next path from L2 to L3

gets launched by the opening edge of PH2 at time=10, just as a synchronous flip-flop would operate. This

timing requirement is labeled Setup 2a.

If the data arrives after the opening edge of PH2, the first path (from L1 to L2) borrows time from the second

path (from L2 to L3). In that case, the launch of data for the second path occurs not at the opening edge, but at

the data arrival time at L2, at some time between the opening and closing edges of PH2. This timing

requirement is labeled Setup 2b. When borrowing occurs, the path originates at the D pin rather than the G pin

of L2.

For the first path (from L1 to L2), PrimeTime reports the setup slack as zero if borrowing occurs. The slack is

positive if the data arrives before the opening edge at time=10, or negative (a violation) if the data arrives after

the closing edge at time=20.

To perform hold checking, PrimeTime considers the launch and capture edges relative to the setup check. It

verifies that data launched at the startpoint does not reach the endpoint too quickly, thereby ensuring that data

launched in the previous cycle is latched and not overwritten by the new data. This is depicted in Figure 1-10.

Figure 1-10 Hold Checks in Latch-Based Paths

Timing Exceptions

When certain paths are not intended to operate according to the default setup/hold behavior assumed by

PrimeTime, you should specify those paths as timing exceptions. Otherwise, PrimeTime might incorrectly

report those paths as having timing violations.

PrimeTime lets you specify the following types of timing exceptions:

False path – A path that is never sensitized due to the logic configuration, expected data sequence, or

operating mode.

Multicycle path – A path designed to take more than one clock cycle from launch to capture.

Minimum/maximum delay path – A path that must meet a delay constraint that you specify explicitly as

a time value.

Learning to Use PrimeTime

For a basic introduction to using PrimeTime, read this chapter and the next chapter of this manual.

If you need help while using PrimeTime, information is readily available by using the help and man commands,

by consulting the PrimeTime manuals, and by searching through the Web-based SolvNet article database. For

more information about getting help, see “PrimeTime Documentation and Online Help”.