Static Timing Analysis -Maharshi

8/6/2019 Static Timing Analysis -Maharshi

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Advanced VLSI Design Laboratory

Static Timing Analysis & Synthesis

Maharshi Bhattacharya


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Dynamic Vs. Static Timing

Analysis

Dynamic timing analysis is not exhaustive and do not

cover all critical paths .

Static timing analysis is highly exhaustive and fast.

STA may include false paths into consideration as

critical path.

In DTA there is no chance of false path beinginterpreted.

Main Objective in STA is meeting setup and hold

requirements.


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Typical Chip Component

Memory

Cells

Control Logic

Custom

Block

Interco-

nnects

Leaf cells

Optimized core


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STA Tool Requirements

Every block must have a timing model.

Synthesized logic is represented in terms of basiccells ( NAND , NOR etc ) and delay information is inthe tech-library.

Custom blocks are instantiated in the design andthey dont have any netlist representation. Stamp

Modeling is used for these blocks. Interconnects are wires and delay of wires are

calculated from wire-load models.


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Latches

clock

D

q

-q

When Clock = 1

When Clock = 0

Clock to Q delay when enabled

= It1 + It2

Delay = It1

Delay = It2

So this explains why latch is transparent


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Setup and Hold of Flops

clock

D

Clock = 0

-QM

Clock = 1

-Q

Setup Time = 1st stage

inverter delay ( only one )

Hold = 2nd stage inverter

delay

Clock 2-q = Switch delay +

2nd stage inverter delay

Q


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Understanding clocks

Clock Sources: Sources can beinput

ports or internal pins .Period and Waveform: These are

mentioned by create_clock command.Example :

create_clock clk period 10 waveform (2, 6 }

0 2 6 10 12 16 20

clk


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Clock Network

Clock Uncertainty: Also called the skew.

Flop Flopclk

Clock reaches

At time TClock reaches at

Time T + t

Flop

set_clock_uncertainty 0.1 clk

Flopclka clkb

Uncertainty between two

Clocks : set_clock_uncertainty

-from clka to clkb


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Clock Network ( cont )

Clock Latency:

Source Latency: Propagation time fromoriginal waveform to the clock definition pointin circuit.

Network Latency: Propagation time fromclock definition point to the register clock pin.

Clock latency is specified byset_clock_latency command.

set_clock_latency source 2.0 clk


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Input and Output delays

A B

Output delay

Clk-to-q delay

Output delay = clock latency+ clk-to-q delay + combo delay A + port delay

Input delay = port delay + combo delay B

Input setup time = input delay intrinsic setup

Total path delay : Output delay + input delay = Td

Input delay


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Input and Output delays

( cont)

Launch edge Capture edge

Intrinsic setup

Max. Time for logic propagation = Tp

Td = 0

Note: For the capture edge clock skew will be considered.

Not shown here for simplicity.


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Summary of clock definitions

Commands used for clock definitions

create_clock set_dont_touch_network

set_clock_latency

set_clock_uncertainty set_input_delay

set_output_delay


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Wire-load models ( cont )Wire Load mode selection

Top enclosed segmented

Top level wire-load = w1

Lower

Modules

Wire load

= w2


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Wire-Load Models ( Example )

wire_load("R1_3M_AVERAGE") {resistance : 1;capacitance : 0.000140 ;slope : 212 ;

fanout_length(1, 102);fanout_length(2, 255);fanout_length(3, 425);

fanout_length(4, 680);fanout_length(5, 935);

}


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Design Rule Constraints

Maximum Transition: This is the longesttime for a net required for its driving pin to

change logic values. In tech-lib this is defined as max_transition.

In design this value can be defined usingset_max_transition command.

If there are both constraints defined designcompiler tries to meet the more restrictiveone.


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Design Rule Constraints ( cont

)

Maximum Capacitance:This is also DRC and allowsto control the capacitance of the nets directly.

To set the capacitance use set_max_capacitancecommand.

Max transition and max load control the cap valuesindirectly and has higher priorities thanmax_capacitance .


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Timing Exceptions

False Path: These are valid paths which are

not simulated or executed.1

01

0

SEL

set_false_path from to


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Case Study: Timing Loop

module test ( b , c , out2 );

input b , c ;

output out2 ;

wire out ;

wire out1;

wire out2 ;

assign out = (b & c );

assign out1 = ~ (out | b ) ;

assign out2 = out1 & c & out2 ;

endmodule

Loading design 'test'Information: Timing loop

detected. (OPT-150)S_4/B S_4/ZWarning: Disabling timingarc between pins 'B' and 'Zon cell 'S_4' to break

a timing loop (OPT-314)


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Timing Exceptions

Multicyle PathsD Huge Combinational Logic

Clock

set_multicylcle_path -2 from ff1 to ff2


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Design Flow

DESIGN ENTRY

SIMULATION

SYNTHESYS

STA

BACK ANNOTATION

NETLIST SDF

SCRIPTDesign Compiler

Prim

etime

Sdf file

Ready for backend


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Back Annotation

Standard Delay Format ( SDF ) : This is the file

containing delay information on any circuit after

successful timing. SDF file contains two types of delay information:

1. Combinational Delays ( Point to Point )

2. Timing Check Delays ( Setup , Hold etc. )

Every Delay information has pattern like

{min:typ:max}


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Back Annotation ( Cont )(CELL

(CELLTYPE "INT_NOT")

(INSTANCE U168)

(DELAY

(ABSOLUTE

(IOPATH A Z (0.512:0.512:0.512)

(0.568:0.568:0.568))

)

)

)

(CELL(CELLTYPE "INT_FDPC")(INSTANCE out_reg}

(DELAY(ABSOLUTE(IOPATH (posedge CP) Q

(1.954:1.954:1.954) (1.612:1.612:1.612))

(IOPATH (negedge CLR) Q ()

(1.112:1.112:1.112))(IOPATH (negedge PRE) Q

(2.074:2.074:2.074) ()))

))

Example : SDF File


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Back Annotation ( Cont )

What is Back Annotation ? This is the process of verification of the delays those

have been extracted in the sdf. Method:

Open Primetime

Read in the design netlist setting proper paths

Read in the sdf.

Report Annotated delays. ( report_annotated_delay and

report_annotated_check ) Note: Only internal nets are annotated. Nets connected to ports

are not annotated.

Write sdf file from primetime.


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Stamp Models

Why Required ?

Modeling timing of custom blocksComponents:

Model File: This file describes the ports,

modes, and interface timing arcs.

Data File:This file describes timing data with

respect to the mentioned timing arcs.


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Stamp Models

New Terms ?

Timing Arcs:

1. Min/Max arcs: Specifies combinational pathdirectly.

2. Timing Check arcs: Setup/Hold , Clock period ,clock latency etc.

Every arc has a label and this label isreferenced in the data file.


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Stamp Models ( Cont)

Timing Mode: Modes are labels that may

activate some set of timing arcs.Example MODE: read ( COND : rw =1 )

activate the read timing path and associated

models.

Please See the Primetime Modeling UserGuide for example.


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Concluding

Do not synthesize any circuit withoutconstraints.

Clock is a global constraint. Must mention wire-load and operating

conditions.

Back-Annotation is a must looking into post-layout simulation.

THANKS

Static Timing Analysis -Maharshi

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