Download - Laptops not included - TECNOS · • Alterra Cyclone FPGA with single cycle access memory, 18X18 multipliers for dedicated DSP & programmable general logic elements. Disclaimer: Images

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Page 1: Laptops not included - TECNOS · • Alterra Cyclone FPGA with single cycle access memory, 18X18 multipliers for dedicated DSP & programmable general logic elements. Disclaimer: Images

COGNITIVE RADIO WIRELESS COMMUNICATION LAB CRL04

Description:

A cognitive radio is an intelligent radio that can be programmed and configured dynamically. Its transceiver is designed to use the best wireless channels in its vicinity. Such a radio automatically detects available channels in wireless spectrum, then accordingly changes its transmission or reception parameters to allow more concurrent wireless communications in a given spectrum band at one location. This process is a form of dynamic spectrum management. The burden on faculty is lowered by using courseware designed at IITD. Lab technicians are eased by integrated hardware and software from same source for trouble free performance.

The system is ideally suited for applications requiring high RF performance and great bandwidth such as physical layer prototyping, dynamic spectrum access and cognitive radio, spectrum monitoring and even networked sensor deployment.

The Superspeed USB 3.0 interface at 5Gbps serves as the connection between the transceivers and the mobile workstation. This enables the user to realize 40 MS/s of real-time bandwidth in the receive and transmit directions, simultaneously (full duplex). FPGA is autoloading so hardware is plug and play as a pen drive! No need to program the FPGA for most cases!

Features:

• Courseware designed at Indian Institute of Technology Delhi• Define Number of Primary users• Define Number of Secondary users• Learn Spectrum Sensing Techniques: Co-operative, Non- cooperative, Interference based• Learn Primary transmitter detection: Energy based detection, Covariance based detection, Waveform based detection, any proprietary algorithm implementation Co-operative detection: Central server, Distributed• Create Adaptive Power Allocation• Create Adaptive Coding• Enable Frequency Hopping• Create Adaptive Waveform• Works with Linux GnuRadio, Compatible to LabVIEW™, MATLAB Simulink™ but does not need one!• ASIC Architecture: 0.4-4 GHz combines LNA, PA driver, RX/TX Mixers, RX/TX Filters, Synthesizers, RX Gain control, TX power control • +5dBm Transmit power & -120dBm Sensitivity Receiver• FPGA program transmit & receive for high performance• Modulation Bandwidth Programmable upto 30 MHZ• Supports both TDD &FDD Full Duplex upto 30MHz• Calibrated +1ppm TCXO• Dual 40 MS/s, 12-bit ADC & Dual 40 MS/s, 12-bit DAC• Up to 5GbpS/s USB 3.0 Data Streaming to Computer• Alterra Cyclone FPGA with single cycle access memory, 18X18 multipliers for dedicated DSP & programmable general logic elements.

Disclaimer: Images shown are Indicative only. Color or Model may differ from the picture shown Features will remain same or More). Specifications are subject to change without notice

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Laptops not included

Page 2: Laptops not included - TECNOS · • Alterra Cyclone FPGA with single cycle access memory, 18X18 multipliers for dedicated DSP & programmable general logic elements. Disclaimer: Images

Hardware Technical SpecificationsTransceiver:Number of Primary users CustomizableNumber of Secondary users CustomizableSpectrum Sensing Techniques Co-operative, Non-cooperative, Interference basedPrimary transmitter detection Energy based detection, Covariance based detection, Waveform based detection, any proprietary algorithm implementationCo-operative detection Central server, DistributedPower Allocation AdaptiveCoding AdaptiveHopping FrequencyWaveform AdaptiveTx/Rx Frequency Range 0.3-4GHzMode Full Duplex/TDD/FDDArchitecture ASIC/FPGA/Zero IFBaseband Bandwidth <1-15MHzFrequency Resolution <3HzMaximum RF Output power +5dBmReceiver Sensitivity -120dBmPLL Phase Noise -125dBc/Hz at 1MHzSpurious Output -50dBcTx/Rx Gain Control Range >50dBTx/Rx Gain Control Step 1/3 dBTx/Rx IO Impedance 50 Ohms SMARx Noise Figure <5dBIQ Phase Error 3 degreeIQ Amplitude Error 0.5dBPLL Settling time 20usADC/DAC Sample Rate upto 40 MS/sADC/DAC Resolution 12 bitsADC/DAC Wideband SFDR 60 dBcI/O Amplitude 1Vp/p /250mV p/p differentialHost Sample Rate 50/25 MS/sFrequency Accuracy 2.5 ppmSSB/LO Suppression >40 dBcFPGA Altera CycloneIntegrated Transceiver 3 GbpsLogic Elements 40,000M9K Memory Blocks >400Embedded Memory >2000 Kbits18bit X18bit Multipliers >100PLL 4Maximum User I/Os >500Maximum Channels >200 DifferentialCurrent Consumption <500mA, USB drivenCable High Speed USB 3.0 Serial Cable, RG316 SMA-SMA X8, Antennas Directional LPDA 0.4-6 Ghz X4, Omni Directional Dipole 0.4-6 GHz X4

Upgrade 3 years auto upgrade of new experiments/training videos/ operation manuals/ firmware /support over internetShipping List Deliverable SDR X4 pcs, Antennas X8 SMA-SMA Cables X8 pcs USB3.0 Cable X4, Attenuator 20dBX4pcs

Software GUI features Boolean, Byte Operators, Channelizers, Channel Models, Coding, Control Port, Debug Tools Deprecated, Equalizers, Error Coding, File Operators, Filters, Fourier Analysis, GUI Widgets, Impairment Models, Instrumentation, Level Controllers, Math Operators, Measurement Tools, Message Tools, Misc, Modulators, Networking Tools, OFDM, Packet Operators, Pager, Peak Detectors, Resamplers, Sinks, Sources, Stream Operators, Stream Tag Tools, Symbol Coding, Synchronizers, Trellis Coding, Type Converters, Variables, Waveform Generators,

Scope of Experimentation

* Introduction to CRL04 Hardware and Software environment

* Define Number of Primary users

* Define Number of Secondary users

* Learn Spectrum Sensing Techniques: Co-operative, Non-cooperative, Interference based

* Learn Primary transmitter detection: Energy based detection, Covariance based detection, Waveform based detection, any proprietary algorithm implementationCo-operative detection: Central server, Distributed

* Create Adaptive Power Allocation

* Create Adaptive Coding

* Enable Frequency Hopping

* Create Adaptive Waveform

* On air transmission & reception using Digital Modulation & Demodulation techniques like ASK, FSK, BPSK, DBPSK, MSK, GMSK, DQPSK, QPSK, OQPSK, pi/4QPSK, 8PSK,16QAM, 64QAM, 256QAM, CPFSK, GFSK, and other variants,

* Spread spectrum techniques like CSS, DSSS, FHSS, THSS

* Multiplexing techniques like TDM, FDM/WDM,SDM, Polarization, Spatial, Packet Switching, MC-SS, OFDM etc

* Analog Channel Models like Noise (Uniform, Linear, Laplacian, Gaussian, Phase noise), Interference (Cross talk, Co-channel, Inter symbol), Distortion (Inter modulation), Frequency response (Attenuation & phase shift), Group delay, Propagation Doppler shift, Fading modeling slow, fast, selective/dispersive, Multipath, Rayleigh, Rician),

Disclaimer: Images shown are Indicative only. Color or Model may differ from the picture shown Features will remain same or More). Specifications are subject to change without notice

Mfd by: Amitec Electronics Ltd.Regd. Off: 504, Nilgiri, Barakhamba Road, New Delhi-110001, India, Works: 4/32, Site-4, Industrial Estate Sahibabad, NCR-201010, India, [email protected], www.sdr-lab.com, www.amitec.co+91-120-4371276, +91-9971-663434, 98101-93153, 98118-39949,

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Page 3: Laptops not included - TECNOS · • Alterra Cyclone FPGA with single cycle access memory, 18X18 multipliers for dedicated DSP & programmable general logic elements. Disclaimer: Images

Scope of Experimentation Contd.

*Channel Coding & decoding-Convolutional, Viterbi,Trellis,

* Channel performance measurements (spectral bandwidth, Symbol Rate, Bit Rate, Channel Capacity, Channel Utilization, Signal to noise ratio, Bit Error Rate BER, Latency, Jitter, Eye Diagram, Constellation diagram, Oscilloscope, Spectrum Analyser, Waterfall display

*Coginitive Radio Experiments in Power Control, Spectrum Sensing, Transmitter Detection, Matched Filter Detection, Energy Detection, Cyclostationary feature detection, Single Cycle detector, Multi Cycle detector, Moment based detectorWideband Spectrum Sensing,

* Line Coding & Decoding Digital Baseband

* Filters-IIR, FIR, Pulse Shaping-RRC root raised cosine, High pass, Low pass, Bandpass, Band stop, FFT, frequency translating filter,

* Equalizer adaptive-CMA , Kurtotic, LMS DD

* Synchronizers-Costas Loop, Clock Recovery, Frequency locked loop, phase locked loop, correlate and sync, carrier acquisition,

* Modeling mathematical equations

* Networking- TCP, UDP, Socket, Broadcasting,

* Encoding decoding for data, voice & video-PSK31, MPEG, CVSD and more

* On air link for Voice, Data, Video,

Student projects Research And more.....

Cognitive Radio Block Diagram

Cognitive Radio Architecture

Transceiver Architecture

IITD

Cognitive Radio Benefits

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Page 4: Laptops not included - TECNOS · • Alterra Cyclone FPGA with single cycle access memory, 18X18 multipliers for dedicated DSP & programmable general logic elements. Disclaimer: Images

Mfd by: Amitec Electronics Ltd.Regd. Off: 504, Nilgiri, Barakhamba Road, New Delhi-110001, India, Works: 4/32, Site-4, Industrial Estate Sahibabad, NCR-201010, India, [email protected], www.amitec.co+91-11-41505510, 9810193153, 9971663434, 9811839949

Graphical Programming Environment OFDM Signal Captured on air at 1GHz

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QAM 256 Received Signal Spectral Display at 1GHz GMSK FFT

QPSK Scope QAM 256 on air capture at 1GHz

QPSK combined windows on MATLAB OFDM Time Domain captured on air at 1GHz

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Disclaimer: Images shown are Indicative only. Color or Model may differ from the picture shown (Features will remain same or More). Specifications are subject to change without notice due to continuous improvement of product.