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Student ID: ____________
ICS 151 Digital Logic Design, Fall Quarter2005, Final Page 1
ICS 151Final
Name : _________________ , _________________(Last Name) (First Name)
Student ID : _______________
Signature : ________________
Instructions:
1. Please verify that your paper contains 15 pages including this cover.
2. Write down your Student-Id on the top of each page of this quiz.
3. This exam is closed book . No notes or other materials are permitted.
4. Total credits of this final are 80 points + 10 EXTRA CREDIT. 5. To receive credit you must show your work clearly.
6. No re-grades will be entertained if you use a pencil.
7. Calculators are NOT allowed.
Q1 Q2 Q3 Q4 Q5 Q6[ExtraCredit]
Total Credit 15 10 15 10 30 10
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Question 1. [Multiple choice] Select the correct answer:
[NO CREDIT UNLSESS YOU SHOW YOUR COMPLETE WORK]
a. What is -75 in 2s complement? [3 points]
2. (B5) 16
75 = 01001011-75 = 10110100 + 1 = 10110101 = B5
b. How many 4-to-1 multiplexers should be used to make a 64-to-1 multiplexer?what is the critical-path-delay of a 64-to-1 multiplexer in terms of the number oftwo-input gates?
[3 points]
3. 21, 12
16+4+1 = 21 MUXEach MUX has:1 level of 3 input AND + 1 level of 4 input OR => 4 levels of 2-input gate
3 levels of MUX * 4 levels of 2-input gates = 12
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Student ID: ____________
ICS 151 Digital Logic Design, Fall Quarter2005, Final Page 3
c.
What is the result of Boolean expression simplification for :BC + D (A + B) + BCD + ABC
[5 points]3. B + D
Use K-MAP
d. How many 2k*4-bit RAM modules do we need to compose a 64k*12 RAMmodule? What should be the size of decoder?
2. 96, 5-to-32[4 points]
(64/2) * (12/4) = 96 ram modules32 rows of ram modules => 5-to-32 decoder
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Student ID: ____________
ICS 151 Digital Logic Design, Fall Quarter2005, Final Page 4
Question 2 [Mealy machine design] [10 points]
Draw the FSM diagram for a Mealy machine that can detect the pattern 1011 on a streamof binary values arriving as input x and generating output z=1 when the pattern isdetected. Your model should also be able to detect overlapping sequences.
Input/Output
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ICS 151 Digital Logic Design, Fall Quarter2005, Final Page 5
Question 3 [Sequential circuit analysis] [15 points]
Analyze the circuit given below ( x is input and z is output):
a. Write the equation for flip-flops inputs (D1, D0) and the circuit output (z) [3points]
D1 = S1S0X + XS0D0 = X(S1 + S0)Z = S1S0
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b. Fill the state table based on the input equation for flip-flops: [6 points]
Present state Input Next state OutputS100001111
S000110011
X01010101
D1(n1)00100110
D0(n0)01010100
Z00000011
c. Draw the FSM of the circuit based on the state table driven in part (b) [5 points]
d. Guess the functionality of the circuit. [1 points]101 Detector
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Question 4 [C to RTL transformation] [10 points]
Here is a C program that computes the square root of an integer number x:
temp = 0;While (temp * temp < x)
temp++;sqrtx = temp;
Convert this C program to an FSMD (high-level behavioral state machine)(Note: Just draw the FSMD, no need for any other step)
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ICS 151 Digital Logic Design, Fall Quarter2005, Final Page 8
Question 5 [RTL-based design] [30 points]
We want to design a circuit that finds an 8-bit input value X inside a 1024*8 memoryand return the index of the value when it is found in memory otherwise it returns -1. Thecircuit begins when a START signal is set to 1 and asserts a DONE signal atcompletion.
a. Capture a high-level state machine [10 points]
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ICS 151 Digital Logic Design, Fall Quarter2005, Final Page 9
b. Create the datapath using the components (as many as needed) listed below:
a. RAMb. Adderc. Comparatord. Register
[10 points]
Two notes:1. cnt_reg is a 10-bit register. Ret_reg is an 11-bit register. Adder is a 10-bit adder.2. You can remove MUX, by using a register that has PRESET input and activatethe PRESET in initialization cycle that makes ret_reg=111 1111 1111
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ICS 151 Digital Logic Design, Fall Quarter2005, Final Page 10
c. Connect the datapath to controller [5 points]
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d.
Derive the controllers FSM diagram [5 points]
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Question 6 [Pipeline utilization] [10 points: EXTRA CREDIT]
a . Using Adder, Subtractor, and Multiplier, design a circuit that performs the followingoperation: [1 point]
Z = (A+B)*(C+D) (E+F)*(H+G)
A, B, C, D, E, F, G, H and Z are 8 bit registers.
b . If addition/subtraction takes 10 ns and multiplication takes 25 ns, what is the fastestclock frequency for the above circuit? [1 points]
freq = 1/45ns = 22.2 MHz
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ICS 151 Digital Logic Design, Fall Quarter2005, Final Page 13
c. Add pipeline registers to your design in part (a) to make your design as fast aspossible. [2 points]
d . What is the fastest clock frequency for the pipelined version in part (c)? What islatency for this circuit? [2 points]
freq = 1/25 = 40 MHzlatency = 3 * 25 = 75 nS
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ICS 151 Digital Logic Design, Fall Quarter2005, Final Page 14
e. Consider the schedule below for computing Z = (A+B)*(C+D) (E+F)*(H+G) that
uses 5 adder/subtractors and 2 multipliers:
Draw a new schedule that uses only 2 adders/subtractor and 1 multiplier. How manycycles it will take to compute a new value for Z? [2 points]
4 cycles
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ICS 151 Digital Logic Design, Fall Quarter2005, Final Page 15
f.
Draw the new datapath based on the schedule in part (e) [Hint: Add the requiredmultiplexers] [2 points]
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