Paul Timans, Gary Xing, Silke Hamm, Steve McCoy, Joseph Cibere, Greg Stuart, and David Camm
Flat-Top Flash AnnealingTM For Advanced CMOS Processing
Innovation • Speed • Solutions7/18/2012 -- 1
Outline
• Introduction– Key Annealing Requirements for Advanced Devices– The Flash-Assisted RTPTM Approach for Millisecond Annealing
• Advanced Doping Requirements– The Balancing Act:
• Diffusion, Activation & Defect Annealing vs. Integration Issueso Opportunities through long-pulse millisecond annealing
• Limits on Millisecond Anneal Duration– Bulk Wafer Heating– Total Energy Requirement
• Process Benefits– Improving Kinetic Trade-off by Controlling the T-t profile– Dopant Activation Improvements - As & B Doping
• Conclusions
Innovation • Speed • Solutions7/18/2012 -- 2
Key Annealing Processes for Advanced CMOS
STI STI
GATE
Ni(Pt)Si / SiGe contacts - low RC with minimal silicon consumptionLow T soak/spike RTA & ms-Anneal
HALO
SOURCE DRAIN
Shallow, Abrupt S/D Extensions with high activationSpike Anneal → ms-Anneal
Contact junction - High activationSpike Anneal → ms-Anneal
High-K anneal / Work-function engineeringRTA &/or ms-Anneal
Selective RTCVD
Si/SiGe/Ge for S/D
Heavily-doped abrupt S/D extensions
Metal Gate
Smooth channel surfaces & corner
shape control
Interface layer & High-k dielectric
Silicides
Buried Oxide or Bulk Si
Source Drain
Gate
• Optimized dopant activation– High Activation: Decrease REXT - for both ion-implanted & deposited dopants– Control diffusion: Optimize gate overlap & placement of junction relative to
interfaces/defects– Sufficient defect annealing
• Optimize integration of strain and new materials– Low thermal budget Ni(Pt)Si : Improve RC, prevent “piping defects”– Low thermal budget anneals for high-K film– Maintaining channel strain (SiGe & Si:C)– Annealing for new channel materials Ge, InGaAs, ....
Many thermal budget constraints
Reduce T?and/or
Shorten Time?
Innovation • Speed • Solutions7/18/2012 -- 3
Millisecond Annealing with Flash-Assisted RTPTM
T
Q
Hot Device SideColder Back Side
T
Q
T
Q
2 Arc Lamps below wafer to heat to intermediate temperature
Flash Lamps
Arc Lamps
4 Flash Lamps above wafer, exposing device side to an intense flash
t
TBulk heating
of wafer
Fast ramp byflash heating
Rapid cooling byradiation and thermal
conduction to bulk
Radiative coolingof wafer
Ti
600700800900
10001100120013001400
4.5 5.0 5.5 6.0
Temperature (°C)
Time (s)
600
700
800
9001000
11001200
1300
4.835 4.840 4.845 4.850 4.855
Top TempBot Temp
Time (s)
• For anneals of < 0.5 s, surface-specific heating is essential:– Requires a pulsed energy source (>10 kW/cm2)⇒ Flash-lamps or scanned lasers
• Flash-Assisted RTPTM (fRTPTM):– Fast ramp (150 K/s) to Ti
– Pulsed surface heating with proprietary water-wall arc lamps– Millios® tool provides real-time T measurement and control on
front & back of wafer
Innovation • Speed • Solutions7/18/2012 -- 4
The Whole Wafer Can be Uniformly Processed in Just One Flash
• Process Uniformity: 3σ < 5K ; Range < 9K• Fast ramp rates & whole-wafer flash exposure provide very cost-
effective processing
Innovation • Speed • Solutions7/18/2012 -- 5
The Ultra-Shallow Junction “Balancing Act”
0.00010.0010.010.1
110
1001000
10000100000
600 700 800 900 1000 1100 1200 1300 1400Temperature (ºC)
Tim
e (s
)
Time for DiffusionTime for Activation (50%)
1 nm
2 nm
5 nm
10 nm
20 nm
Furn
ace
RTP
ms-
anne
al
Diffusion Length
20 nm
R.A. Camillo-Castillo et al. APL 88(1), 2006H.W. Kennel et al.,
RTP 2006 Conference
R. B. MacKnight et al., in RTP 2004, (IEEE, 2004) p. 3.
H.W. Kennel, RTP 2010 Conference
• Millisecond annealing greatly improves activation compared to conventional RTA
• BUT....USJ needs a careful balance between diffusion, activation & defect annealing
– Conventional MSA heating duration is too short for complete defect annealing: Longer pulses needed?
• Also: Many integration factors........
Innovation • Speed • Solutions7/18/2012 -- 6
XjXj
RsRs
DefectsDefects
AbruptAbrupt
Integration Also Imposes (Dominant?) Requirements
• Activation, diffusion & defect annealing are just the starting point
R. Lindsay (Infineon)., “Realisation of Advanced Junctions in 32nm Products” IIT 2008 Conference
XjXj
RsRs
Defects*Defects*
AbruptAbruptJn CapacitanceJn Capacitance
OverlapOverlap
Stress relaxationStress relaxation
Gox leakageGox leakage
Gox reliability / trapsGox reliability / traps SegregationSegregation
Poly DepletionPoly Depletion
GIDLGIDL
*Defects affect: Thermal stability, Jn leakage, Halo deactivation…Manufacturability: Throughput, Repeatability, Pattern Uniformity
Vt mismatchVt mismatch
Stress-enhanceddiffusion
Stress-enhanceddiffusion
Channel MobilityChannel Mobility
Hf-based High-K with TaN/TiN gate
M. Cho et al., “Interface/Bulk Trap Recovery After SubmeltLaser Anneal and the Impact to NBTI Reliability”, IEEE Electron Dev. Lett., 31 (2010) 606.
S. Govindaraju et al. (Intel) - “Advanced (Millisecond) Annealing in Silicon Based Semiconductor Manufacturing”, ECS 2010 Spring Meeting
• Many additional integration issues affect the choice of doping/annealing conditions
– Some materials systems impose peak T limitations
• Sophisticated optimization of annealing conditions is required
– Spike anneal / MSA integration– Process conditions: ramp rates, preheat T, peak
temperatures, pulse durations……– Flexibility of anneal conditions is very valuable!
Innovation • Speed • Solutions7/18/2012 -- 7
Extending the Length of Millisecond Anneal Duration Opens Up New Opportunities
• Motivation to explore the “long pulse” MSA regime– “Traditional MSA” < tanneal < Spike RTA – MSA without the need for a separate spike anneal– Longer pulse allows lower peak temperatures: More “integration friendly”
• Junction objectives:– Adequate defect annealing– Controlled nm-level diffusion
(e.g. gate overlap control)– Maintain high activation
• Integration aspects:– Compatibility with strain scheme– Compatibility with gate dielectric
approach 750
800
850
900
950
1000
1050
1100
0 5 10 15 20Time (ms)
Tem
pera
ture
(°C
)
Top Bottom
950
975
1000
1025
1050
1075
3 4 5 6 7 8 9
4ms within 50°C of TPEAK
• Motivation for a “few ms” anneal at temperatures <1250°C
Innovation • Speed • Solutions7/18/2012 -- 8
600
700
800
900
1000
1100
1200
1300
1400
-1 0 1 2 3 4 5
Top (12.5 ms)Bottom (12.5 ms)Top (22.5 ms)Bottom (22.5 ms)Top (37.5 ms)Bottom (37.5 ms)Top (62.5 ms)Bottom (62.5 ms)
Tem
pera
ture
(°C
)
Time (s)
Millisecond Annealing Can Be Extended to ~10 ms
• T-t models holding the device side at a constant yet elevated temperature for longer times
• If time at temperature >10 ms the bulk of the wafer approaches temperatures where excessive diffusion and deactivation may occur
Beyond 10 ms, MSA looks more & more like spike annealingPractical range of a long ms flash
— Peak temp up to 1300ºC— Duration up to 10 ms
700
800
900
1000
1100
1200
1300
1400
0 20 40 60 80 100
Top (12.5 ms)Bottom (12.5 ms)Top (22.5 ms)Bottom (22.5 ms)Top (37.5 ms)Bottom (37.5 ms)Top (62.5 ms)Bottom (62.5 ms)
Tem
pera
ture
(°C
)
Time (ms)
Innovation • Speed • Solutions7/18/2012 -- 9
Extending Pulse Length Increases Wafer Processing Energy Requirement
• Keeping the Si surface hot for longer increases in total energy requirement• Calculations illustrate the effect for a increasing anneal duration (T-50K)
– Assume semi-infinite wafer, so that heat-sinking remains effective– The flat-top profile minimizes the total energy requirement, less energy is wasted during preheat– Laser scanning at low scan velocity increases energy requirement
• Heat loss parallel to the wafer surface as well as down into the bulk of the wafer• Very challenging for wafer throughput, especially given strong scan overlap requirement
400
600
800
1000
1200
0 5 10 15 20 25
Flat-Top PulseGaussian PulseScanned Laser
Tem
pera
ture
(°C
)
Time (ms)
0.0
0.5
1.0
1.5
2.0
2.5
0.1 1 10
Gaussian Pulse
Flat Top (1 ms Ramp)
Laser Scan
Tota
l Ene
rgy
Req
uire
d (M
J/m
2 )
Pulse Duration (Tpeak
-50K) (ms)
Innovation • Speed • Solutions7/18/2012 -- 10
Improving Kinetic Trade-Off with Flat-Top Profile
• MSA can exploit kinetics to optimize the trade-off between competing processes: e.g. One desired process & one undesired process
– e.g. Activation of B implants:• EA (Diffusion) ~ 3.5 eV• EA (Activation) ~ 5 eV
– Short anneals at high T are very useful for activation/diffusion trade-off
• C. Hill - MRS 83, 381 (1983) ; T. Fiory - Appl. Phys. Lett. 74, 2658 (1999) ; A. Mokhbehri - IEEE Trans. Electron Dev. 49, 1183 (2002)
• The effect of the anneal cycle can be summarized in teff
• Maximize:
• The flat-top profile is most effective, because a larger fraction of the anneal is spent close to the peak temperature∫ ′
⎭⎬⎫
⎩⎨⎧
⎟⎟⎠
⎞⎜⎜⎝
⎛−
′−=
t
REF
Aeff td
TtTkEt
0
1)(
1exp
processundesiredeff
processdesiredeff
tt
_
_
−
−6.5
7.0
7.5
8.0
8.5
9.0
9.5
0.1 1 10
Gaussian Pulse
Flat Top (1 ms Ramp)
Laser Scan
τ eff(5
eV
)/τef
f(3.5
eV
)
Pulse Duration (Tpeak
-50K) (ms)
TREF=1000°C
Innovation • Speed • Solutions7/18/2012 -- 11
Dopant Profile Tuning with the Flat-Top Flash: As
• Extended pulse duration at ~1200°C allows profile tuning• Longer time reduces RS and increases profile abruptness
1017
1018
1019
1020
1021
1022
0 5 10 15 20 25 30
As-Implanted
Pulse A
Pulse B
Pulse C
As
Con
cent
ratio
n (c
m-3
)Depth (nm)
564 Ω/sq.3.6 nm/dec.
511 Ω/sq.3.4 nm/dec.
442 Ω/sq.2.4 nm/dec.
As: 2.5 keV, 2x1015/cm2
900
950
1000
1050
1100
1150
1200
1250
-2 0 2 4 6 8 10 12 14
Pulse APulse BPulse C
Tem
pera
ture
(°C
)
Time (ms)
Innovation • Speed • Solutions7/18/2012 -- 12
1018
1019
1020
1021
1022
0 10 20 30 40 50
As-Implanted
Pulse A
Pulse B
Pulse C
B C
once
ntra
tion
(cm
-3)
Depth (nm)
Dopant Profile Tuning with the Flat-Top Flash: B
• Once again, we see improved activation and profile abruptness as pulse length at 1200°C is extended
497 Ω/sq.
381 Ω/sq.
335 Ω/sq.
B: 1 keV, 2x1015/cm2
900
950
1000
1050
1100
1150
1200
1250
-2 0 2 4 6 8 10 12 14
Pulse APulse BPulse C
Tem
pera
ture
(°C
)
Time (ms)
Innovation • Speed • Solutions7/18/2012 -- 13
Improving Dopant Activation
• Increasing the pulse duration demonstrated improved activation with a small increase in junction depth
• As: Concentration-enhanced diffusion and increased abruptness improves RS
• B: BIC dissolution combined with concentration-enhanced diffusion improves RS
300
350
400
450
500
550
600
10 15 20 25 30 35 40
2x1015 As/cm2, 2.5 keV2x1015 B/cm2, 1 keV
She
et R
esis
tanc
e (Ω
/sq.
)
Junction Depth (5x1018 cm-3) (nm)
Increasing annealduration
(1 to 4 ms)
Innovation • Speed • Solutions7/18/2012 -- 14
Millios® Flat-Top Flash Anneal Provides Device Benefits Compared to Spike RTA+Laser Annealing
Long ms-flash was compared with a “combo process” of Spike-RTA + Laser Anneal (SOI process, poly/SiON gate)Id-Vgs and Vt(sat) roll-off were very similarLong ms-flash NFETs needed only ~ ½ of
the B halo dose and exhibit no anomalous corner leakage which is sometime found in spike RTA+laser NFETs. (Better B halo localization)
K.L. Lee et al. (IBM) and S. McCoy et al. (Mattson), IWJT 2010
Innovation • Speed • Solutions7/18/2012 -- 15
Conclusions
• Pulsed anneals at <1250°C for times up to ~ 10 ms can help overcome integration issues with new device structures– Beyond 10ms, the benefits of fast surface cooling are lost and the
processing becomes very costly
• Extending the annealing time for millisecond anneals opens up a new regime for dopant activation & damage annealing combined with controlled diffusion
• The Flat-Top Flash AnnealingTM method brings additional advantages to millisecond annealing– Increasing the fraction of the anneal time spent at peak temperature can
improve kinetic trade-offs– Most effective use of heat source energy, together with high wafer throughput– Significant improvements in doping profile shapes and activation
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