Eindhoven, June 11th, 2015
Facing Moore’s Law with Model-Driven R&D
Markus Matthes
Executive Vice President Development and Engineering, ASML
• Introducing ASML
• Lithography, the driving force behind Moore’s Law
• How to continue driving Moore’s law?
• Summary and conclusions
Contents June 2015
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Introducing ASML
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It’s hard to imagine a world without chipsGlobal market 2014: 221 billion chips, $333 billion
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ASML makes the machines for making those chips
• Lithography is the critical
tool for producing chips
• All of the world’s top chip
makers are our customers
• 2014 sales: €5.9 bln
• People: ~14,000 FTEs
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Founded in 1984 as a spin-off from Philips…
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…with global presence!
3,100 employees
Source: ASML Q1 2015Over 70 sales and service offices located worldwide
8,600 employees 2,400 employees
Moore’s law
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Driving the semiconductor industry: Moore’s Law
Gordon Moore (1965):
Number of transistors per
chip doubles every year.
Later adjusted to two years,
the trend has held for half a
century
0,1
1
10
100
1000
2004Total
2005Total
2006Total
2007Total
2008Total
2009Total
2010Total
2011Total
2012Total
2013Total
2014 Est.Total
NAND Flash price 1 GB [$]
Moore’s Law makes chips cheaper…
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Fla
sh
pri
ce p
er
GB
(in
do
lla
rs)
$110 for 1 GB
$0.46 for 1 GB
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… and more energy-efficient
Source: Jonathan Koomey, Lawrence Berkeley National Laboratory and Stanford University, 2009
Dell Optiplex GXI
486/25 and 486/33 Desktops
IBM PC-ATIBM PC-XT
Commodore 64
DEC PDP-11/20
Cray 1 supercomputer
IBM PC
SDS 920
Univac I
EniacEDVAC
Univac II
Univac III (transistors)
Regression results:N = 76Adjusted R-squared = 0.983Comps/kWh = exp(0.440243 x year – 849.259)Average doubling time (1946 to 2009) = 1.57 years
IBM PS/2E + Sun SS1000
Gateway P3. 733 MHz
Dell Dimension 2400
SiCortex SC5832
2008 + 2009 laptops1.E+16
1.E+15
1.E+14
1.E+13
1.E+12
1.E+11
1.E+10
1.E+09
1.E+08
1.E+07
1.E+06
1.E+05
1.E+04
1.E+03
1.E+02
1.E+01
1.E+00
Co
mp
uta
tio
ns p
er
kW
h
1940 1950 1960 1970 1980 1990 2000 2010
Computations per Kilowatt hour double every 1.5 years
Lithography, the driving force
behind Moore’s Law
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A chip is made of dozens of layers
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The manufacturing loop
Exposure
(the Lithography step)
Developing
Etching
Ion implantationStripping
Deposition
Photoresist coating
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Lithography is critical for shrinking transistors
Like a photo enlarger of old,
lithography forms the image of
chip patterns on a wafer
The ASML ecosystem makes this happen
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Open Innovation from design to manufacturing
Virtual innovation network
Academia, technology providers, research institutes
Co-solution network
Mask, Resist, Wafer track
Wafer processing
Customers
Semiconductor producers
Supplier and
partner network
Optics, measurement
systems, parts, subsystems
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Open Innovation from design to manufacturing
Academia
Customers
Technology
partners
Co-solution
partners
Suppliers
Advanced Research Center
for Nanolithography
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Increasing complexity, increasing challenges
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Scanner functionality and hardware become
increasingly more complex
The world is far from perfect at (sub-)nanometer level
• Flat is no longer flat, straight is no longer straight
• Variations due to flow, temperature and humidity variations
• Sensitivity to dynamics, magnetics, and pressure differences
Physics, mathematics and software correct
hardware imperfections at (sub-)nanometer level June 2015
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Reticle
stage
Example: Lens Model
• Laser beam heats up lens
• A sensor measures the lens aberrations
• The lens model calculates how to adjust the lens (within 12 ms)
• Lens is adjusted and wafer is exposed in optimum state
Reticle
WaferWafer
stage
Projection
Lens
Laser
Beam
• Lens model implemented in
MATLAB
• Timing constraints met by code
optimization together with
MathWorks: 39% speed gain
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ASML software development reflects increasing complexity
• TWINSCAN software consists of
40 million lines of code
• More than 500,000 lines of MATLAB
code in TwinScan archive
• 20+ computing nodes running
more than 200 processes
• Our software supports old as well as new systems
• SW archive embeds > 10 years of development history, thousands of man years of work
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How to continue driving Moore’s law?
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The other side of Moore’s medal…
How to continue driving Moore’s law and ensure customer profitability,
while keeping R&D cost under control?
Development & engineering costs rapidly growing
1980s:
PAS 2000/5000
R&D: 50 mln €
1990s:
PAS 5500
R&D: 400 mln €
2000s:
TWINSCAN
R&D: 1500 mln €
2010s:
NXE EUV
R&D: > 2000 mln €
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Investing in early development phase leads to gain in
product maturing phase and earlier customer profitability June 2015
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Quarters
Effort vs. time
Early development
phaseProduct maturing
phase
Less issues at integration,
less redesigns to meet spec;
availability, good dies/day…
But how to invest more in the early development phase?
Let us look at a Development and Engineering work flow
design
validation
integration
validation
realization
validation
model
realization
integration
component
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Different approach needed to reduce development effort
paradigms, models,
technology and
tools
solution
implementation,
testing and
maintenance
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Define
RequirementsComplete
Integration
and Test
System-Level
Integration
and Test
Subsystem
Integration
and Test
System-Level
Specification
Subsystem
Design
TPD / Code
Generation
Simulink
Plant Model
Subsystem
Implementation
Model in the Loop
(Simulation) Subsystem
ValidationProperty Proving
Standards
Checking
Requirements
TracingHardware
in the Loop
System
Validation
Module
Validation
Models i.s.o. Documents
Model Driven Engineering vision
Formal Verification
Software in the Loop
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Summary and conclusions
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Summary and Conclusions
• Moore’s Law has shaped the world as we know it
• Lithography has enabled and driven Moore’s Law
• “Moore’s law for product development” is not sustainable
• To continue driving Moore’s law, the R&D way of working needs to evolve towards a system-wide model driven engineering approach
• Directions pursued are: higher abstraction levels, executable specifications (models instead of documents), formal model verification and design time validation, automatic code generation
• Further elaboration of industry standards is desirable to easily connect solutions across the development chain
• Strategic partnerships, such as between ASML and MathWorks, are instrumental to achieve this
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