Continuing Moore’s law - Intel Newsroom · Continuing Moore’s law MARK BOHR INTEL SENIOR...

TECHNOLOGY AND MANUFACTURING DAY

ContinuingMoore’s lawMARK BOHRINTEL SENIOR FELLOW, TECHNOLOGY AND MANUFACTURING GROUPDIRECTOR, PROCESS ARCHITECTURE AND INTEGRATIONSEPTEMBER 19, 2017


Legal DisclaimerDISCLOSURES

China Tech and Manufacturing Day 2017 occurs during Intel’s “Quiet Period,” before Intel announces its 2017 third quarter financial and operating results. Therefore, presenters will not be addressing third quarter information during this year’s program.

Statements in this presentation that refer to forecasts, future plans and expectations are forward-looking statements that involve a number of risks and uncertainties. Words such as “anticipates,” “expects,” “intends,” “goals,” “plans,” “believes,” “seeks,” “estimates,” “continues,” “may,” “will,” “would,” “should,” “could,” and variations of such words and similar expressions are intended to identify such forward-looking statements. Statements that refer to or are based on projections, uncertain events or assumptions also identify forward-looking statements. Such statements are based on management’s expectations as of September 19-20, 2017, and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in these forward-looking statements. Important factors that could cause actual results to differ materially from the company’s expectations are set forth in Intel’s earnings release dated July 27, 2017, which is included as an exhibit to Intel’s Form 8-K furnished to the SEC on such date. Additional information regarding these and other factors that could affect Intel’s results is included in Intel’s SEC filings, including the company’s most recent reports on Forms 10-K, 10-Q and 8-K reports may be obtained by visiting our Investor Relations website at www.intc.com or the SEC’s website at www.sec.gov.


Intel innovation leadership

Intel leads the industry by at least 3 years in introducing major process innovations

Intel 90nm 65nm 45nm 32nm 22nm 14nm 10nm

Year ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20

Others 90nm 65nm 40nm 28nm 20nm 16nm 10nm





Year ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20

>3 yearslater

StrainedSilicon

Strained Silicon






Year ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20

>3 yearslater

High-kMetal Gate

High-kMetal Gate

>3 yearslater

StrainedSilicon

Strained Silicon






Year ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20

>3 yearslater

High-kMetal Gate

High-kMetal Gate

SelfAlign Via

>3 yearslater

SelfAlign Via

>3 yearslater

StrainedSilicon

Strained Silicon






Year ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20

>3 yearslater

High-kMetal Gate

High-kMetal Gate

>3 yearslater

FinFETTransistor

FinFETTransistor

SelfAlign Via

>3 yearslater

SelfAlign Via

>3 yearslater

StrainedSilicon

Strained Silicon






Year ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20

>3 yearslater

High-kMetal Gate

High-kMetal Gate

>3 yearslater

FinFETTransistor

FinFETTransistor

SelfAlign Via

>3 yearslater

SelfAlign Via

>3 yearslater

StrainedSilicon

Strained Silicon

~3 yearslater

Hyper Scaling

Hyper Scaling






Year ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20

>3 yearslater

High-kMetal Gate

High-kMetal Gate

>3 yearslater

FinFETTransistor

FinFETTransistor

SelfAlign Via

>3 yearslater

SelfAlign Via

>3 yearslater

StrainedSilicon

Strained Silicon

~3 yearslater

Hyper Scaling

Hyper Scaling


Contact

Fin

Gate

??

HyperScaling

HyperScaling




Year ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20

>3 yearslater

High-kMetal Gate

High-kMetal Gate

>3 yearslater

FinFETTransistor

FinFETTransistor

Contact

Fin

Gate

??

HyperScaling

HyperScaling

SelfAlign Via

>3 yearslater

SelfAlign Via

>3 yearslater

StrainedSilicon

Strained Silicon

~3 yearslater

Hyper Scaling

Hyper Scaling


Intel developed all the major logic process innovations used by our industry over the past 15 years


0.01

0.1

1

2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

Logic

Area

(relative)

HVM Wafer Start Date

45nm

22nm

32nm

.49x

.45x

Logic area scaling

Traditional logic area scaling was ~0.49x per generation using a “gate pitch x cell height” metric

Logic Cell

Width

Logic

Cell

Height

Gate Pitch

Logic Area Metric


0.01

0.1

1

2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

Logic

Area

(relative)


45nm

22nm

14nm

32nm

.37x

.49x

.45x

10nm

.37x

Logic area scaling

Hyper scaling on 14 nm and 10 nm provides better than normal logic area scaling

Logic Cell

Width

Logic

Cell

Height

Gate Pitch

Logic Area Metric


Logic area scaling

… but “gate pitch x cell height” is not a comprehensive transistor density metric

Logic Cell

Width

Logic

Cell

Height

Gate Pitch

Logic Area Metric

0.01

0.1

1

2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

Logic

Area

(relative)


45nm

22nm

14nm

32nm

.37x

.49x

.45x

10nm

.37x


Logic Transistor density metric

Standard NAND+SFF metric is a more accurate estimate of logic transistor density

NAND2 Tr Count

NAND2 Cell Area

Scan Flip Flop Tr Count

Scan Flip Flop Cell Area0.6 x + 0.4 x = # Transistors / mm2

2-Input NAND Cell Complex Scan Flip-Flop Logic Cell

Cell Height

Cell Width

Cell Width


1

10

100

2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

Transistor

Density

MTr / mm2


Intel

45nm

22nm

14nm

10nm

32nm

2.7x

2.5x

2.1x

2.3x

Logic Transistor density

Hyper scaling on 14 nm and 10 nm provides better than normal transistor density

60/40 NAND+SFFDensity Metric


1

10

100

2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

Transistor

Density

MTr / mm2


Intel

45nm

22nm

14nm

10nm

32nm


Transistor density improvements continue at a rate of ~doubling every 2 years



1

10

100

2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

Transistor

Density

MTr / mm2


Intel

45nm

22nm

14nm

10nm

32nm

100.8

3.3

7.5

15.3

37.5

MTr / mm2


Transistor density improvements continue at a rate of ~doubling every 2 years


MTr/mm2

90.8 NAND

115.7 SFF

100.8 60/40


Microprocessor die area scaling

Normal microprocessor die area scaling has been ~0.62x per generation

0.62x

Logic

SRAM

IO

100 mm2

Logic

SRAM

IO

100 mm2

Logic

SRAM

IO

100 mm2

Logic

SRAM

IO

100 mm2

Logic

SRAM

IO

0.62x0.62x

0.62xArea

100 mm2

62 mm2

38.4 mm2

23.8 mm2

14.8 mm2

45 nm 32 nm 22 nm 14 nm 10 nm


Microprocessor die area scaling

Hyper scaling delivers 0.46-0.43x die area scaling on 14 nm and 10 nm

100 mm2

45 nm 32 nm 22 nm 14 nm 10 nm

62 mm2

17.7 mm2

7.6 mm2

0.62x

Logic

SRAM

IO

100 mm2

Logic

SRAM

IO

100 mm2

Logic

SRAM

IO

100 mm2

Logic

SRAM

IO

100 mm2

Logic

SRAM

IO

0.43x

0.46x

0.62xArea

38.4 mm2


45

nm

32

nm

22

nm

14

nm

10

nm

7 n

m

$ / mm2

(normalized)

45

nm

32

nm

22

nm

14

nm

10

nm

7 n

m

$ / Transistor(normalized)

x =

45

nm

32

nm

22

nm

14

nm

10

nm

7 n

m

mm2 / Transistor(normalized)

Lo

g S

ca

le

Lo

g S

ca

le

Lo

g S

ca

le

Cost per transistor

Transistor area is scaling faster than normal


45

nm

32

nm

22

nm

14

nm

10

nm

7 n

m

$ / mm2

(normalized)

45

nm

32

nm

22

nm

14

nm

10

nm

7 n

m


x =

45

nm

32

nm

22

nm

14

nm

10

nm

7 n

m


Lo

g S

ca

le

Lo

g S

ca

le

Lo

g S

ca

le

Cost per transistor

Wafer cost is increasing


45

nm

32

nm

22

nm

14

nm

10

nm

7 n

m

$ / mm2

(normalized)

45

nm

32

nm

22

nm

14

nm

10

nm

7 n

m


x =

45

nm

32

nm

22

nm

14

nm

10

nm

7 n

m


Lo

g S

ca

le

Lo

g S

ca

le

Lo

g S

ca

le

Cost per transistor

Cost per transistor continues to come down


2009 2011 2013 2015 2017 2019 2021

Dynam

ic C

ap

acitance

(lo

g s

cale

)

Process Readiness Date

22nm

14nm

10nm

32nm

Lower

Power

2009 2011 2013 2015 2017 2019 2021

Tra

nsis

tor P

erf

orm

ance

(lo

g s

cale

)


22nm

14nm

10nm

32nm

Higher

Performance

2009 2011 2013 2015 2017 2019 2021

Pe

rfo

rmance

pe

r W

att (

log

scale

)


22nm

14nm

10nm

32nm

Better

Perf/Watt

Performance Power Performance per Watt

Transistor performance and power

Scaled transistors continue to provide improved performance per watt


Future options subject to change

45 nm 32 nm 22 nm 14 nm 10 nm 7 nm 5 nm 3 nm

High-k Metal Gate FinFETs Contact over Gate

SA Double Patterning SA Quad Patterning

Manufacturing Development Research

III-V

10nm

III-V Transistors 3D Stacking Material Synthesis

2D Materials Nanowires EUV Patterning

Interconnects Beyond CMOS Dense Memory

Contact

Gat

e

Innovation Enabled technology Pipeline

Wide range of options in research to continue Moore’s Law


• Intel leads the industry in introducing innovations that enable scaling

• Hyper scaling on Intel 14 nm and 10 nm provides better-than-normal scaling while continuing to reduce cost per transistor and improve performance per watt

• Intel’s research and development groups are exploring a wide range of novel technology options to continue scaling for the foreseeable future

Summary

Moore’s Law is alive and well at Intel

Continuing Moore’s law - Intel Newsroom · Continuing Moore’s law MARK BOHR INTEL SENIOR...

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