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FIFrH SEMESTER B.TECH. (ENGINEERING) DEGREE

EXAMINATION, DECEMBER 2010

 EC/AI/IC  2K 506 D-DIGITAL SYSTEM DESIGN

(b)

(c)

(d)

(e)

(f)

(g)

(h)

II. (a)

(b)

III. (a)

(b)

IV. (a)

List the design guide lines that are to be followed while doing a FPGA based implementation.

Implement the function f  =a E B b E B c using a PLD. Also draw the standard PLD diagram.

In the MAX 7128S CPLD how many macrocells are available? What does the letter s signify ?

What are the 4 kinds of Tristate buffers and their tables?

Write a short note on general purpose interconnects.

Name the most commonly used fault models and explain about each one.

What is meant by programmability failures? Explain.

(8 x 5 = 40 marks)

Explain different methods of designing a Decade counter for FPGA implementation.

Or 

Explain how a 4 x 4 multiples can be designed and implemented using FPGA.

Draw the simplified schematic of ALTRA MAX 7000 CPLD and explain about each block .

Or 

With the help of simplified Schematic explain the structure of XILINX XC 4000 series

FPGA ship.

Design a one to two pulse generator using PLA as specified in the following .table ;-

S2 S1 No. of pulses

0 0 No pulse

0 1 One Pulse

1 0 two Pulse

1 1 don't care

81 and 82 are the two switches depending upon the setting of the switches the circuit will

generate either one pulse or two pulses and then return to the reset state.

Or 

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(b) (i) List and explain the guidelines to be followed while designing a system using FPGA.

(7 marks)

(ii) List the steps involved in the process of convecting the design into FPGA implementation.

(8 marks)

v. (a) Explain:

(i) Boundary scan.

(ii) Build in self Test.

(b) Derive a table for the circuit in Figure to show the converge of the various stuck-at-O and

stuck-at-l faults by the eight possible tests. Find a minimal test set for this circuit.