EC 2K 506 D
2
FIFrH SEMESTER B. TECH. (ENGINEERING) DEGREE EXAMINATION, DECEMBER 2010 EC /AI /IC 2K 506 D-D IG IT AL SYSTEM DESIG N ( b) (c) (d) (e) (f) (g) (h) II. (a) (b) III . (a) (b) IV. (a) List the desi gn gu ide lin es tha t are to b e fo llow ed while doi ng a FPGA bas ed imple me nta tio n. Impleme nt the func tio n f =a E B b E B c us ing a PL D. Al so dr aw the stan da rd PL D di ag ra m. In the MA X 71 28 S CP LD how ma ny ma cr oc el ls are av ai lab le ? Wha t do es th e let ter s si gn ify ? Wha t ar e th e 4 k inds of Tris tate bu ff er s and th ei r tabl es ? Wri te a short no te on genera l purpose interconnects. Na me the mos t co mm on ly used fault models an d ex pl ai n ab ou t each on e. Wh at is mea nt by progr ammability fa ilu re s? Ex pl ai n. (8 x 5 40 marks) Explain d ifferent met ho ds of de si gni ng a De cad e cou nte r for FPGA implementation . Or Ex plai n ho w a 4 x 4 mul ti pl es ca n be d esign ed an d impl emented using FPGA. Dra w th e sim pli fied sch ematic of ALTR A MA X 70 00 CPLD an d ex pl ain ab ou t ea ch bl oc k . Or With the hel p of s impli fi ed Sch ema tic ex pla in the stru ctu re of XIL INX XC 400 0 ser ies FPGA sh i p. De si gn a one to two puls e ge ner at or us ing PL A as s pe cified in th e follo wi ng .table ;- S2 S1 No . of pulses 0 0 No pulse 0 1 One Pulse 1 0 two Pul se 1 1 don 't car e 81 and 82 are th e two swit ch es de pe nd in g up on th e se tt in g of th e swit ches th e ci rc ui t will generate ei th er on e pulse or two pu ls es an d th en re tu rn to t he res et st at e. Or
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Transcript of EC 2K 506 D
5/14/2018 EC 2K 506 D - slidepdf.com
http://slidepdf.com/reader/full/ec-2k-506-d 1/2
FIFrH SEMESTER B.TECH. (ENGINEERING) DEGREE
EXAMINATION, DECEMBER 2010
EC/AI/IC 2K 506 D-DIGITAL SYSTEM DESIGN
(b)
(c)
(d)
(e)
(f)
(g)
(h)
II. (a)
(b)
III. (a)
(b)
IV. (a)
List the design guide lines that are to be followed while doing a FPGA based implementation.
Implement the function f =a E B b E B c using a PLD. Also draw the standard PLD diagram.
In the MAX 7128S CPLD how many macrocells are available? What does the letter s signify ?
What are the 4 kinds of Tristate buffers and their tables?
Write a short note on general purpose interconnects.
Name the most commonly used fault models and explain about each one.
What is meant by programmability failures? Explain.
(8 x 5 = 40 marks)
Explain different methods of designing a Decade counter for FPGA implementation.
Or
Explain how a 4 x 4 multiples can be designed and implemented using FPGA.
Draw the simplified schematic of ALTRA MAX 7000 CPLD and explain about each block .
Or
With the help of simplified Schematic explain the structure of XILINX XC 4000 series
FPGA ship.
Design a one to two pulse generator using PLA as specified in the following .table ;-
S2 S1 No. of pulses
0 0 No pulse
0 1 One Pulse
1 0 two Pulse
1 1 don't care
81 and 82 are the two switches depending upon the setting of the switches the circuit will
generate either one pulse or two pulses and then return to the reset state.
Or
5/14/2018 EC 2K 506 D - slidepdf.com
http://slidepdf.com/reader/full/ec-2k-506-d 2/2
(b) (i) List and explain the guidelines to be followed while designing a system using FPGA.
(7 marks)
(ii) List the steps involved in the process of convecting the design into FPGA implementation.
(8 marks)
v. (a) Explain:
(i) Boundary scan.
(ii) Build in self Test.
(b) Derive a table for the circuit in Figure to show the converge of the various stuck-at-O and
stuck-at-l faults by the eight possible tests. Find a minimal test set for this circuit.
