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(Approved by A.I.C.T.E.New Delhi & Affiliated to J.N.T.U.Hyderabad.)
Be ide !o"#t opera$ Near %a o'i il City$Hayath Na ar $%.%.Di t.Hyderabad* +,-+- A./.
DEPARTMENT OF
ELECTRONICS AND COMMUNICATIONS ENGINEERING
VLSI SIMULATION LAB MANUAL
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ARJUN COLLEGE OF TECHNOLOGY & SCIENCES
(Approved by A.I.C.T.E.New Delhi & Affiliated to J.N.T.U.Hyderabad.)
Be ide !o"#t opera$ Near %a o'i il City$Hayath Na ar $%.%.Di t.Hyderabad* +,-+-A./.
DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
LAB MANUAL
TOOLS REQUIRED: 1.PC
2. Front End Tool (Xilinx, etc.
!. P"#$ic%l De$i&n Tool (C%dence, 'entor r%)"ic$, S#no)$#$, etc.
Prepared By:
Mr.upendar SapatiAssoc.Prof,
M.Tech (VSD
Dept. of ECE.
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*+o t t"e l%+or%tor#:
Design and i p!e entation of the fo!!o"ing CM#S digita! $ana!og circuits using Cadence $Mentaor
%raphics$%EDA$E&ui'a!ent CAD too!s . The design sha!! inc!ude %ate )e'e! design, Transistor !e'e! design,
*ierarchica! design, Veri!og *D)$V*D) design. )ogic Synthesis, Si u!ation and 'erification ,Sca!ing of
CM#S +n'erter fir different techno!ogies, Study of secondary effects ( te perature, po"er supp!y and process
corners ,Circuit #pti i-ation "ith respect to area, perfor ance and $ or po"er ,)ayout , E traction of parasitic
and /ac0 annotation, odification in circuit para eters and !ayout consu ption , DC $transient ana!ysis,
Verification of !ayouts(D1C,)VS .
E CAD progra s can /e done using any co pi!er. Do"n !oad the progra s on 2P%A$CP)D
/oards and perfor ance testing ay /e done using pattern generator (34 channe!s and !ogic ana!y-er apart
fro 'erification /y si u!ation "ith any one of the front end too!s.
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Li$t o- Ex)eri ent$:
E/C*D Pro&r% $: P%&e 0o.
5. *D) Code to rea!i-e a!! the !ogic gates.
4. Design of 4 to 6 decoder
3. Design of 7 to 3 encoder ("ithout and "ith priority
6. Design of 7 to 5 u!tip!e er
8. Design of 6 /it Binary to %ray code con'erter
9. Design of Mu!tip!e er$ De u!tip!e er , co parator
. Design of 2u!! Adder using 3 ode!ing sty!es
7. Design of 2!ip 2!ops: S1, D, ;. 2inite State Machine Design
LSI Pro&r% $:
5. +ntroduction to )ay out design ru!es
4. )ayout, Physica! 'erification ,p!ace ent ? route for co p!e design, state ti ing ana!ysis
+1 drop ana!ysis and crossta!0 ana!ysis of the fo!!o"ing:
Basic )ogic %ates
CM#S +n'erter
CM#S @#1$@A@D gates
CM#S #1 and M gates
CM#S 5 /it fu!! adder
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Static$Dyna ic !ogic circuit
!atch
pass transistor
3. !ayout of any co /inationa! circuit
6. introduction to SP+CE si u!ation and coding of @M#S$CM#S circuit
8. SP+CE si u!ation of /asic ana!og circuits: +n'erter $Differentia! A p!ifier
9. Ana!og Circuits si u!ation(AC Ana!ysis CS ? CD A p!ifier
. Syste )e'e! Design using P))
@ote: Any S+ of the a/o'e e peri ents fro each part are to /e conducted (Tota! 54 .
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1Schematic Diagram:
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2
Exp.No:1 Logic Gates Date:-----------------------------------------------------------------------------------------------------------------------------
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Aim 0 To De i # 1o i2 3ate " i# 4HD1 a#d i "late the a e " i# 5ili#6 I7E 7i "lator
Tools Require : -./C
. 5ili#6 I7E
!"DL #o e:
library IEEE8
" e IEEE.7TD91:3IC9--;A AND B8
:%-=>A :% B8
N:T-=>N:T A8
5:%-=>A 5:% B8
NAND-=> A NAND B8
N:%-=>A N:% B8
5N:%-=>A 5N:% B8
e#d Behavioral8
$
S%&thesis Report
A' (i&al Report:
i#al %e "lt
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%T1 Top 1evel :"tp"t ile Na e 0 lo i29 ate .# r
Top 1evel :"tp"t ile Na e 0 lo i29 ate
:"tp"t or at 0 N3C
:pti i?atio# 3oal 0 7peed
@eep Hierar2hy 0 N:
)' Desig& Statistics
I: 0 #ell *sage 0
BE17 0
IN4 0 -
1UT 0 ;
I: B"ffer 0
IBU 0
:BU 0
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>De+ice utili,atio& summar%:
7ele2ted Devi2e 0 +,eft +;*+
N" ber of 7li2e 0 < o"t of
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(other >G , )8
7I3NA1 0 td9lo i29ve2tor( dow#to ,)8
BE3IN""t0 de2oder /:%T !A/(
E# >G E#$
I >G I$
>G
)8
E#=> - after -,# 8
I=> ,- after ,# $ -, after ,# $ -- after
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END8
Result:*To*< De2oder i de i #ed " i# 4HD1 a#d i "lated the a e " i# 5ili#6 I7E
7i "lator
11
Simulatio& Results:
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-
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-
Schematic Diagram:
S%&thesis Report
(i&al Report:
i#al %e "lt%T1 Top 1evel :"tp"t ile Na e 0 e#2oder9witho"t9priority.# rTop 1evel :"tp"t ile Na e 0 e#2oder9witho"t9priority:"tp"t or at 0 N3C:pti i?atio# 3oal 0 7peed@eep Hierar2hy 0 N:Desig& Statistics
I: 0 -#ell *sage :
BE17 0 -+ 1UT 0 ; 1UT< 0 I: B"ffer 0 - IBU 0 :BU T 0
De+ice utili,atio& summar%:7ele2ted Devi2e 0 +,eft +;*+N" ber of 7li2e 0 o"t of ;) 7o"r2e0 I=,G (/AD) De ti#atio#0 = G (/AD) Data /ath0 I=,G to = G 3ate Net Cell0i#*Go"t fa#o"t Delay Delay 1o i2al Na e (Net Na e)
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**************************************** ************ IBU 0I*G: < -.-,; ,.;+- I9,9IBU (I9,9IBU ) 1UT 0I,*G: ,.;- ,.+ 9 "6,,,,=,G , the# => 555 8
el e
2a e I i whe# ,,,,,,,- >G => ,,, 8
whe# ,,,,,,-, >G => ,,- 8
whe# ,,,,,-,, >G => ,-, 8
whe# ,,,,-,,, >G => ,-- 8
whe# ,,,-,,,, >G => -,, 8
whe# ,,-,,,,, >G => -,- 8
whe# ,-,,,,,, >G => --, 8
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whe# -,,,,,,, >G => --- 8
whe# other >G => KKK 8
e#d 2a e8
e#d if8
e#d pro2e 8
e#d Behavioral8
-+
Simulatio& Results:
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-;
!"DL Test e&ch:
1IB%A% ieee8
U7E ieee. td9lo i29--; , 87I3NA1 I 0 td9lo i29ve2tor( dow#to ,) 0> (other >G , )8
7I3NA1 0 td9lo i29ve2tor( dow#to ,)8
BE3IN
""t0 e#2oder9witho"t9priority /:%T !A/(
E# >G E#$
I >G I$
>G )8
E#=> - after -,# 8
I=> ,,,,,,-, after -,# $ ,,,,-,,, after ,# $ ,-,,,,,, after ,# 8
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Result: 3-To-$ E&co er 8ithout /riorit% i de i #ed " i# 4HD1 a#d i "lated the a e " i#5ili#6 I7E 7i "lator
-
Schematic Diagram:
S%&thesis Report(i&al Report:
i#al %e "lt%T1 Top 1evel :"tp"t ile Na e 0 E#2oder9with9priority.# rTop 1evel :"tp"t ile Na e 0 E#2oder9with9priority:"tp"t or at 0 N3C:pti i?atio# 3oal 0 7peed@eep Hierar2hy 0 N:Desig& Statistics
I: 0 -#ell *sage :
BE17 0 1UT 0 - 1UT< 0 + !U5 + 0 I: B"ffer 0 -- IBU 0 :BU 0
De+ice utili,atio& summar%:7ele2ted Devi2e 0 +,eft +;*+N" ber of 7li2e 0 o"t of
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:BU 0I*G: .-; 9-9:BU ( =-G) ****************************************************************************** Total ;.
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-
Simulatio& Results:
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,
!"DL Test e&ch:
1IB%A% ieee8
U7E ieee. td9lo i29--; , 8
7I3NA1 I 0 td9lo i29ve2tor( dow#to ,) 0> (other >G , )8
7I3NA1 0 td9lo i29ve2tor( dow#to ,)8
BE3IN
""t0 e#2oder9with9priority /:%T !A/(
E# >G E#$
I >G I$
>G
)8
E#=> - after -,# 8
I=> ,,,,,,-, after -,# $ ,,,,-,,, after ,# $ ,-,,,,,, after ,# 8
Result: *To* E#2oder with /riority i de i #ed " i# 4HD1 a#d i "lated the a e " i# 5ili#6I7E 7i "lator
-
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Schematic Diagram:
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Exp.No:4 3-To-1 ultiplexer Date:-----------------------------------------------------------------------------------------------------------------------------Aim 0 To De i # 3-To-1 ultiplexer " i# 4HD1 a#d i "late the a e " i# 5ili#6 I7E 7i "lator
Tools Require : -./C
. 5ili#6 I7E
!"DL #o e:
library IEEE8
" e IEEE.7TD91:3IC9--;
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(i&al Report:
i#al %e "lt
%T1 Top 1evel :"tp"t ile Na e 0 !"69 9-.# r
Top 1evel :"tp"t ile Na e 0 !"69 9-
:"tp"t or at 0 N3C
:pti i?atio# 3oal 0 7peed
@eep Hierar2hy 0 N:
Desig& Statistics
I: 0 -
#ell *sage :
BE17 0
1UT 0 -
1UT< 0 +
!U5 + 0
I: B"ffer 0 - IBU 0 -
:BU 0 -
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
De+ice utili,atio& summar%:
7ele2ted Devi2e 0 +,eft +;*+
N" ber of 7li2e 0 o"t of ;)
7o"r2e0 7=,G (/AD)
De ti#atio#0 (/AD)
Data /ath: S96; to G 7$
I >G I$
>G
)8
E#91=> - after ,# 8
I=> -,-,-,-, after -,# 8
7=> ,,- after -,# $ ,-, after ,# $ ,-- after ,# $ -,, after
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Result: 3-To-1 ultiplexer i de i #ed " i# 4HD1 a#d i "lated the a e " i# 5ili#6 I7E7i "lator.
+
Simulatio& Results:
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;
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Schematic Diagram:
S%&thesis Report
"DL S%&thesis Report
!a2ro 7tati ti2
5or 0 -*bit 6or 0 A +a&ce "DL S%&thesis Report!a2ro 7tati ti2
5or 0 -*bit 6or 0 (i&al Report:
%T1 Top 1evel :"tp"t ile Na e 0 Bi#ary9to9 ray.# rTop 1evel :"tp"t ile Na e 0 Bi#ary9to9 ray:"tp"t or at 0 N3C:pti i?atio# 3oal 0 7peed@eep Hierar2hy 0 N:Desig& Statistics
I: 0 #ell *sage :
BE17 0 1UT 0 I: B"ffer 0 IBU 0 < :BU 0 -N" ber of 7li2e 0 o"t of
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-----------------------------------------------------------------------------------------------------------------------------Aim 0 To De i # )i&ar%-To-Gra% #o e #o&+erter " i# 4HD1 a#d i "late the a e " i# 5ili#6I7E 7i "lator
Tools Require : -./C
. 5ili#6 I7E
!"DL #o e:
library IEEE8
" e IEEE.7TD91:3IC9--;B( )8
3( )=>B( ) 5:% B( )8
3(-)=>B( ) 5:% B(-)8
3(,)=>B(-) 5:% B(,)8
e#d Behavioral8
Simulatio& Results:
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,
!"DL Test e&ch:
1IB%A% ieee8
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U7E ieee. td9lo i29--; (other >G , )8
7I3NA1 3 0 td9lo i29ve2tor( dow#to ,)8
BE3IN
""t0 Bi#ary9to9 ray /:%T !A/(
B >G B$
3 >G 3
)8
B=> -,-, after -,# $ -,,, after ,# 8
END8
Result: Bi#ary*To*3ray Code Co#verter i de i #ed " i# 4HD1 a#d i "lated the a e " i#5ili#6 I7E 7i "lator
$1
Schematic Diagram:
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S%&thesis Report
"DL S%&thesis Report!a2ro 7tati ti2
Co parator 0
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Aim 0 To De i # 4-)it #omparator " i# 4HD1 a#d i "late the a e " i# 5ili#6 I7E 7i "lator
Tools Require : -./C
. 5ili#6 I7E
!"DL #o e:
library IEEE8
" e IEEE.7TD91:3IC9--;B the# AEPB=> - 8A3TB=> , 8A1TB=> , 8
el if AGB the# AEPB=> , 8A3TB=> - 8A1TB=> , 8
el e AEPB=> , 8A3TB=> , 8A1TB=> - 8
e#d if8
e#d pro2e 8
e#d Behavioral8
Simulatio& Results:
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G7" => , 8Co"t=> , 8
whe# ,,- >G7" => - 8Co"t=> , 8
whe# ,-, >G7" => - 8Co"t=> , 8
whe# ,-- >G7" => , 8Co"t=> - 8
whe# -,, >G7" => - 8Co"t=> , 8
whe# -,- >G7" => , 8Co"t=> - 8
whe# --, >G7" => , 8Co"t=> - 8
whe# --- >G7" => - 8Co"t=> - 8 whe# other >G7" => K 8Co"t=> K 8
e#d 2a e8
e#d pro2e 8
e#d Behavioral8 , 8
7I3NA1 Ci# 0 td9lo i2 0> , 8
7I3NA1 7" 0 td9lo i28
7I3NA1 Co"t 0 td9lo i28
BE3IN
""t0 "ll9Adder9Behavioral /:%T !A/(
A >G A$B >G B$
Ci# >G Ci#$
7" >G 7" $
Co"t >G Co"t
)8
A=> - after - after ,# $ , after - after -,# $ , after ,# $ - after ,# $ , after
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, 8
el if 2lQ eve#t a#d 2lQ> - the#
P=>D8
e#d if8
e#d pro2e 8
e#d Behavioral8
++
Desig& Statistics
I: 0 >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>De+ice utili,atio& summar%:
7ele2ted Devi2e 0 +,eft +;*+
N" ber of 7li2e 0 , o"t of
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3ate Net Cell0i#*Go"t fa#o"t Delay Delay 1o i2al Na e (Net Na e) **************************************** ************ IBU 0I*G: - -.-,; ,. + D9IBU (D9IBU ) DC0D ,. ; P **************************************** Total -. -# (-.
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U7E ieee. td9lo i29"# i #ed.all8
U7E ieee.#" eri29 td.A118
ENTIT tb9D 9A y#9vhd I7
END tb9D 9A y#9vhd8
A%CHITECTU%E behavior : tb9D 9A y#9vhd I7
C:!/:NENT D 9A y#
/:%T(2lQ 0 IN td9lo i28
% t 0 IN td9lo i28
D 0 IN td9lo i28
P 0 :UT td9lo i2
)8
END C:!/:NENT8
7I3NA1 2lQ 0 td9lo i2 0> , 8
7I3NA1 % t 0 td9lo i2 0> , 8
7I3NA1 D 0 td9lo i2 0> , 8
7I3NA1 P 0 td9lo i28
BE3IN
""t0 D 9A y# /:%T !A/(
2lQ >G 2lQ$
% t >G % t$
D >G D$
P >G P )8
% t=> - after #ot 2lQ after -,# 8
D=> - after ,# 8
END8
Result: D (lip (lop 8ith As%&chro&ous @Reset i de i #ed " i# 4HD1 a#d i "lated thea e " i# 5ili#6 I7E 7i "lator +
Schematic Diagram:
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;,
Exp.No:37 ' D (lip (lop 8ith S%&chro&ous @Reset Date:-----------------------------------------------------------------------------------------------------------------------------Aim 0 To De i # D (lip (lop 8ith S%&chro&ous @Reset " i# 4HD1 a#d i "late the a e " i#5ili#6 I7E 7i "lator
Tools Require : -./C
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. 5ili#6 I7E
!"DL #o e:
library IEEE8
" e IEEE.7TD91:3IC9--;
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;
!"DL Test e&ch:
1IB%A% ieee8
U7E ieee. td9lo i29--;
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U7E ieee. td9lo i29"# i #ed.all8
U7E ieee.#" eri29 td.A118
ENTIT tb9D 97y#9vhd I7
END tb9D 97y#9vhd8
A%CHITECTU%E behavior : tb9D 97y#9vhd I7
C:!/:NENT D 97y#
/:%T(2lQ 0 IN td9lo i28
% t 0 IN td9lo i28
D 0 IN td9lo i28
P 0 :UT td9lo i2
)8
END C:!/:NENT8
7I3NA1 2lQ 0 td9lo i2 0> , 8
7I3NA1 % t 0 td9lo i2 0> , 8
7I3NA1 D 0 td9lo i2 0> , 8
7I3NA1 P 0 td9lo i28
BE3IN
""t0 D 97y# /:%T !A/(
2lQ >G 2lQ$
% t >G % t$
D >G D$
P >G P )8
% t=> - after #ot 2lQ after -,# 8
D=> - after ,# 8
END8
Result: D (lip (lop 8ith S%&chro&ous @Reset i de i #ed " i# 4HD1 a#d i "lated the a e" i# 5ili#6 I7E 7i "lator ;
Schematic Diagram:
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S%&thesis Report
"DL S%&thesis Report
!a2ro 7tati ti2
%e i ter 0 -
-*bit re i ter 0 -A +a&ce "DL S%&thesis Report
!a2ro 7tati ti2
%e i ter 0 -
lip* lop 0 -
(i&al Register Report
!a2ro 7tati ti2
%e i ter 0 -
lip* lop 0 -
(i&al Report:
i#al %e "lt
%T1 Top 1evel :"tp"t ile Na e 0 D 9A y#.# r
Top 1evel :"tp"t ile Na e 0 D 9A y#
:"tp"t or at 0 N3C
:pti i?atio# 3oal 0 7peed
@eep Hierar2hy 0 N:
;Co"#tS-8 if 2o"#t> ---- the# 2o"#t=> ,,,, 8
e#d if8
e#d if8
e#d pro2e 8
e#d Behavioral8
+
De+ice utili,atio& summar%:
7ele2ted Devi2e 0 +,eft +;*+
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N" ber of 7li2e 0 o"t of
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!a6i " o"tp"t reO"ired ti e after 2lo2Q0
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Simulatio& Results:
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!"DL Test e&ch:
1IB%A% ieee8
U7E ieee. td9lo i29--;G Co"#t)8
ClQ=> #ot 2lQ after -,# 8
% t=> - after -,# $ , after ,# $ - after ;,# 8
END8
Result: BCD Co"#ter with A y#2hro#o" %e et i de i #ed " i# 4HD1 a#d i "lated the a e" i# 5ili#6 I7E 7i "lator
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Schematic Diagram:
,
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Exp.No:57 ' )#D #ou&ter 8ith As%&chro&ous ResetDate:-----------------------------------------------------------------------------------------------------------------------------Aim 0 To De i # )#D #ou&ter 8ith S%&chro&ous Reset " i# 4HD1 a#d i "late the a e " i#5ili#6 I7E 7i "lator
Tools Require : -./C
. 5ili#6 I7E
!"DL #o e:
library IEEE8
" e IEEE.7TD91:3IC9--; ,,,, 8
el if ClQ eve#t a#d 2lQ> - the#
Co"#t=>Co"#tS-8
if 2o"#t> ---- the# 2o"#t=> ,,,, 8
e#d if8
e#d if8
e#d pro2e 8
e#d Behavioral8
-
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Simulatio& Results:
!"DL Test e&ch:
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1IB%A% ieee8
U7E ieee. td9lo i29--;G Co"#t
)8
ClQ=> #ot 2lQ after -,# 8
$ $