VLSI LAB(4)
Transcript of VLSI LAB(4)
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DEPARTMENT OFELECTRONICS & COMMUNICATION ENGINEERING
LABORATORY MANUALFOR
ECAD & VLSI LAB(IV B.Tech., I Sem)
BALAJI INSTITUTE OF TECHNOLOGY & SCIENCELaknepally, Narsampet, Warangal
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CMOS Layers
n-well process
p-well process
Twin-tub processn-well process
MOSFET Layers in an n-well process
Layer Types
p-substrate
n-well
n+
p+
Gate oxide
Gate (polycilicon)
Field Oxide
Insulated glass
Provide electrical isolation
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Interconnect Layout Example
Designing MOS Arrays
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Parallel Connected MOS Patterning
Basic Gate Design
Both the power supply and ground are routed using the Metal
layer
n+ and p+ regions are denoted using the same fill pattern. The
only difference is the n-well
Contacts are needed from Metal to n+ or p+
The CMOS NOT Gate
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Alternate Layout of NOT Gate
NAND2 Layout
NOR2 Layout
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NAND2-NOR2 Comparison
General Layout Geometry
Graph Theory: Euler Path
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Stick Diagrams
Cartoon of a layout.
Shows all components.
Does not show exact placement, transistor sizes, wire lengths,wire widths, boundaries, or any other form of compliance with
layout or design rules.
Useful for interconnect visualization, preliminary layout
compaction, power/ground routing, etc.
Stick Diagrams
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Stick Diagram - Example I
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Stick Diagram - Example II
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Design Rules
Description of digital IC
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Design rules and gate layout
CMOS Process Layers
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Intra-Layer Design Rules
Transistor Layout
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CMOS Inverter Layout
A A
np-substrate Field
Oxidep+n+
In
Out
GND V DD
(a) Layout
(b) Cross-Section along A-A
A A
A CMOS Inverter
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