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Introduction of Actel FPGA
page 2112/04/20 Presentation
Outline
OverviewActel FPGA CharacteristicActel FPGA ArchitectureActel FPGA Application
page 3112/04/20 Presentation
Introduction To FPGA
FPGAField Programmable Gate Array (FPGA)
Programmable Logic Device (PLD)
Development Bias High Density
High Performance
Low Cost
Low Power
Integrated
page 4112/04/20 Presentation
Supplier
Many FPGA suppliers have entered the market over the years
Xilinx Altera Lattice Atmel Actel ……etc
page 5112/04/20 Presentation
Actel
Flash based FPGAEncryptionDo not need to be configured each time
power is applied
Anti-fuse FPGAone time programmableSuited using on product line
page 6112/04/20 Presentation
Outline
OverviewActel FPGA CharacteristicActel FPGA ArchitectureActel FPGA Application
page 7112/04/20 Presentation
Actel FPGA Characteristic
Fuse vs. Anti-fuseFlash vs. SRAM
page 8112/04/20 Presentation
Actel FPGA Characteristic
Fuse vs. Anti-fuseFuse
Resistance changes from Low to High at high current Programmed only once
Anti-fuse Resistance changes from High to Low when high
voltage Require a very small area
– More connections than others technologies
Programmed only once
page 9112/04/20 Presentation
Actel FPGA Characteristic
Fuse vs. Anti-fuseFlash vs. SRAM
page 10112/04/20 Presentation
Actel FPGA Characteristic
SRAMAdvantage:
Re-programmable (erasable)Faster (than Flash)
Disadvantage:VolatileExtra ROMNeed time for reading programs from ROMPoor Information Security
page 11112/04/20 Presentation
Actel FPGA Characteristic
FlashAdvantage:
Re-programmable (erasable)Non-volatile Information Security
Disadvantage:Slower (than SRAM)
page 12112/04/20 Presentation
Outline
OverviewActel FPGA CharacteristicActel FPGA ArchitectureActel FPGA Application
page 13112/04/20 Presentation
Actel FPGA Architecture(AX1000)
page 14112/04/20 Presentation
Actel Programmable Gate Arrays
Rows of programmablelogic building blocks
+
rows of interconnect
Anti-fuse Technology:
Program Once
Use Anti-fuses to build
up long wiring runs from
short segments
page 15112/04/20 Presentation
Actel FPGA Architecture
Logic Module
Horizontal Track
Vertical Track
Anti-fuse
Interconnection Fabric
page 16112/04/20 Presentation
Actel FPGA Architecture(C-Cell)
page 17112/04/20 Presentation
Actel FPGA Architecture(C-Cell)
C-CellBasic multiplexer logic plus more inputs
and support for fast carry calculationCarry connections are “direct” and do not
require propagation through the programmable interconnect
page 18112/04/20 Presentation
Actel FPGA Architecture(R-Cell)
page 19112/04/20 Presentation
Actel FPGA Architecture(R-Cell)
R-CellCore is D flip-flopMuxes for altering the clock and
selecting an inputFeed back path for current value of the
flip-flop for simple holdDirect connection from one C-cell output
of logic module to an R-cell input; Eliminates need to use the programmable interconnect
page 20112/04/20 Presentation
Outline
OverviewActel FPGA CharacteristicActel FPGA ArchitectureActel FPGA Application
page 21112/04/20 Presentation
Actel FPGA Application
SpaceMilitary
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