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CONTENTS:
INTRODUCTION
DESIGN METRICS
STRUCTURE OF CMOS INVERTER
SWITCH MODELS OF CMOS INVERTER
STATIC PROPERTIES
VOLTAGE TRANSFER CHARACTERISTICS
SWITCHING THRESHOLD VOLATGE
NOISE MARGINS
POWER DISSIPATION
CONCLUSION
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Inverter is a fundamental logic gate that performs boolean
operation on single input variable .
Analysis of MOS inverters can directly applied to more complex
logic circuits such as Nand, Nor etc.
B=AA
A B
0 1
1 0
In MOS Inverter circuits both input variable and output are
represented by node voltages referenced to ground potential.
- Logic 1 represents high voltage .
- Logic 0 represents low voltage .
INTRODUCTION:
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Different design metrics are -
Cost Complexity
Area
Integrity and robustness Performance
Energy efficiency
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Structure of CMOS inverter :
Structure of CMOS inverter consists of NMOS transistor
and PMOS transistor which acts as load.
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Gates of the two transistor are shorted at the input and
drains are shorted at the output.
Source of the PMOS is connected to VDD(power supply)
and of NMOS is connected to ground.
Switch models of CMOS inverter
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From the above fig when Vin is high and equal to Vdd ,
Nmos transistor is on and Pmos is off . Direct path exists
between Vout and ground node resulting in a steady statevalue of 0 V.
When the input voltage is low (0 V) , NMOS and PMOS
transistors are off and on. Here the path exists between
VDD and Vout .
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Complementary CMOS:
The static CMOS gate is a combination of two networks
Pull up network (PUN) and Pull down network(PDN).
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Static properties of CMOS inverter characteristics:
The high and low output levels equal VDD and groundwhich implies that voltage swing is equal to the supply
voltage resulting in high noise margins.
The logic levels are not dependent upon the relative
device sizes,so that the transistors can be minimum
size. Gates with this property are called ratioless.
Logic levels are determined by the relative dimensions
of the composing transistors is called as ratioed logic.
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No direct path exists between the supply and ground rails
under steady-state operating conditions (when the inputand outputs remain constant). The absence of current
flow means that the gate does not consume any static
power.
Voltage-transfer characteristic (VTC) can be graphically
deduced by superimposing the current characteristics of
the NMOS and the PMOS devices.
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Load line curves for PMOS and NMOS are plotted as shown
above. For a dc operating points to be valid, the currents
through the NMOS and PMOS devices must be equal.
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The VTC of the inverter hence exhibits a very narrow
transition zone. This results from the high gain during the
switching transient, when both NMOS and PMOS aresimultaneously on, and in saturation. In that operation
region, a small change in the input voltage results in a
large output variation.
VTC of static CMOS inverter,
derived from the load curves as shown above(VDD = 2.5 V).
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There are 5 different regions in the VTC as shown in the fig
above.
In the first region Vin
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The above characteristics also represent the input output
characteristics of an ideal inverter.
Switching threshold voltage of a CMOS inverter:
The switching threshold, VM, is defined as the point where
Vin = Vout. Its value can be obtained graphically from theintersection of the VTC with the line given by Vin = Vout.
In this region, both PMOS and NMOS are always saturated.
We obtain the expression for VM ignoring the channellength modulations as follows
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For larger values of VDD the above equation can be
simplified as
VM=r VDD/(1+r)
Which states that the switching threshold is set by ratio r,
which compares the relative driving strengths of NMOS and
PMOS transistors.
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Piecewise approximation approach yields the following
expressions for width of the transition region VIH-VIL, VIH,
VIL and the noise margins NMH and NML are calculated asfollows,
To calculate the midpoint gain of the static CMOS inverterwe assume PMOS and NMOS are velocity saturated where
gain is the strong function of slopes of the currents in
saturation region.
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Hence the channel length modulation factor cannot be
ignored which would lead to infinite gain .The gain can be
now derived by differentiating the below equation which isvalid around the switching threshold with respect to Vin:
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with ID(VM) the current flowing through the inverter for
Vin = VM. The gain is almost determined by channel
length modulation.
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Scaling the supply voltage:
Scaling the supply voltage means reducing the signal
swing which helps to reduce the internal noise in the
system (such as caused by crosstalk) and makes the
design more sensitive to external noise sources that do
not scale.
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POWER DISSIPATION:
There will not be power dissipation instatic cmos inverter but when the
transistor is switching or changing its
state power dissipation occurs.
Inverter has the capacitive load at the output of the CMOS
which is connected to the input of the another CMOS.
Because of the charging and discharging property of
capacitor there will be flow of current.
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There will be 2 types of transitions during the charging and
discharging of the capacitor .
Energy transfer during each transistor can be given as
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The frequency f is given as the number of transitions
per second. Hence , the total power dissipation during
the f number of transitions can be given as
Power dissipation of the inverter can be reduced by reducingthe capacitance which is proportional to area i.e., if we
reduce the dimensions capacitance will be reduced and
hence the power dissipation is reduced.
Another way to reduce the power dissipation is reduce Vdd2.
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CONCLUSION:
The CMOS inverter is an important circuit device that
provides quick transition time, high buffer margins, and
low power dissipation which are the desired qualities
which makes in inverters for most circuit design.
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THANK U
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