Outline Introduction CMOS devices CMOS technology CMOS logic structures CMOS sequential circuits...

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Transcript of Outline Introduction CMOS devices CMOS technology CMOS logic structures CMOS sequential circuits...

  • OutlineIntroductionCMOS devicesCMOS technologyCMOS logic structuresCMOS sequential circuitsCMOS regular structures

  • CMOS logic structuresCMOS logic: 0 and 1The MOST - a simple switchThe CMOS inverterThe CMOS pass gateSimple CMOS gatesComplex CMOS gates

  • CMOS logic: 0 and 1Logic circuits process Boolean variablesLogic values are associated with voltage levels:VIN > VIH 0VIN < VIL 0Noise margin:NMH=VOH-VIHNML=VIL-VOL

  • The MOST - a simple switch

  • MOSFETs in digital designImportant characteristics:It is an unipolar deviceNMOS - charge carrier: electronsPMOS - charge carrier: holesIt is a symmetrical deviceSource = drainHigh input impedance (Ig=0)Low standby current in CMOS configurationVoltage controlled device with high fan-out

  • The CMOS inverter

  • The CMOS inverter

  • The CMOS inverter

  • The CMOS pass gate

  • The CMOS pass gateRegions of operation: 0 to 1 transitionNMOS:source followerVgs = Vds always:Vout < Vdd-VTN saturationVout > Vdd-VTN cutoffVTN > VTN0 (bulk effect)PMOS:current sourceVout < |VTP| saturationVout > VTP linear

  • Simple CMOS gates

  • Simple CMOS gates

  • Simple CMOS gates

  • Simple CMOS gates

  • Simple CMOS gates

  • Simple CMOS gates

  • Complex CMOS gates

  • Complex CMOS gates

  • Complex CMOS gates

  • Complex CMOS gates

  • Complex CMOS gatesCan a compound gate be arbitrarily complex?NO, propagation delay is a strong function of fan-in:

    FO Fan-out, number of loads connected to the gate: 2 gate capacitances per FO + interconnectFI Fan-in, Number of inputs in the gate:Quadratic dependency on FI due to:Resistance increaseCapacitance increaseAvoid large FI gates (Typically FI 4)

  • Single-Bit AdditionHalf Adder Full AdderFor the Sum SkIf Ak=Bk then Sk=Ck-1 else Sk=Ck-1For the carryIf Ak=Bk then Ck=Ak=Bk else Ck=Ck-1

    ABCoutS0000010110011110

    AkBkCk-1CkSk0000000101010010111010001101101101011111

  • 17: Adders *Full Adder Design IBrute force implementation from eqns

    17: Adders

  • 17: Adders *Full Adder Design IIFactor S in terms of CoutS = ABC + (A + B + C)(~Cout)Critical path is usually C to Cout in ripple adder

    17: Adders

  • Complex CMOS gates

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