VHDL code for 2 to 4 decoderlibrary IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity twoto4decvhdl is

Port ( a : in STD_LOGIC_VECTOR (1 downto 0);

y : out STD_LOGIC_VECTOR (3 downto 0));

end twoto4decvhdl;

architecture Behavioral of twoto4decvhdl is

begin

process (a)

begin

case a is

when "00"=> y y y y null;

end case;

end process;

end Behavioral;

Test bench code for 2 to 4 decoder

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY tb_2to4 IS

END tb_2to4;

ARCHITECTURE behavior OF tb_2to4 IS

COMPONENT twoto4decvhdl

PORT(

a : IN std_logic_vector(1 downto 0);

y : OUT std_logic_vector(3 downto 0)

);

END COMPONENT;

--Inputs

signal a : std_logic_vector(1 downto 0) := (others => '0');

--Outputs

signal y : std_logic_vector(3 downto 0);

-- No clocks detected in port list. Replace below with

-- appropriate port name

BEGIN

uut: twoto4decvhdl PORT MAP (

a => a,

y => y

);

- Stimulus process

stim_proc: process

begin

a Y

);

-- Stimulus process

stim_proc: process

begin

en