All VHDL Codes for Final year executed
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VHDL code for 2 to 4 decoder library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity twoto4de!"dl is #ort $ a % in STD_LOGIC_&ECTO' $1 downto (); y % out STD_LOGIC_&ECTO' $* downto ()); end twoto4de!"dl; ar"iteture +e"a!ioral o, twoto4de!"dl is be-in roess $a) be-in ase a is w"en /((/0 y20/(((1/; w"en /(1/0 y20/((1(/; w"en /1(/0 y20/(1((/; w"en /11/0 y20/1(((/; w"en ot"ers 0 null; end ase; end roess; end +e"a!ioral; Test bench code for 2 to 4 decoder
description
All VHDL codes for Final year has been executed.
Transcript of All VHDL Codes for Final year executed
VHDL code for 2 to 4 decoderlibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity twoto4decvhdl is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0));
end twoto4decvhdl;
architecture Behavioral of twoto4decvhdl is
begin
process (a)
begin
case a is
when "00"=> y y y y null;
end case;
end process;
end Behavioral;
Test bench code for 2 to 4 decoder
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_2to4 IS
END tb_2to4;
ARCHITECTURE behavior OF tb_2to4 IS
COMPONENT twoto4decvhdl
PORT(
a : IN std_logic_vector(1 downto 0);
y : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal y : std_logic_vector(3 downto 0);
-- No clocks detected in port list. Replace below with
-- appropriate port name
BEGIN
uut: twoto4decvhdl PORT MAP (
a => a,
y => y
);
- Stimulus process
stim_proc: process
begin
a Y
);
-- Stimulus process
stim_proc: process
begin
en
