Transcript

www.jntuworld.com

ECE357: Introduction to VLSI CAD

Electrical Engineering & Computer Science Northwestern University

w w

. w

tu jn

Prof. Hai Zhou

or w

. ld

m o c

1

www.jntuworld.com

www.jntuworld.com

Logistics Time & Location: MWF 11-11:50 TECH L160

Instructor: Hai Zhou [email protected] Oce: L461 Oce Hours: W 3-5P

Teaching Assistant: Chuan Lin Texts: VLSI Physical Design Automation: Theory & Practice, Sait & Youssef, World Scientic, 1999. Reference:2

w w

. w

tu jn

or w

. ld

m o c

www.jntuworld.com

www.jntuworld.com

An Introduction to VLSI Physical Design, Sarrafzadeh & Wong, McGraw Hill, 1996. Grading: Participation-10% Project-30% Midterm-30% Homework-30% Homework must be turned in before class on each due date, late: -40% per day Course homepage: www.ece.northwestern.edu/~haizhou/ece357

w w

. w

tu jn

or w

. ld

m o c

2

www.jntuworld.com

www.jntuworld.com

What can you expect from the course Understand modern VLSI design ows (but not the details of tools) Understand the physical design problem

Familiar with the stages and basic algorithms in physical design Improve your capability to design algorithms to solve problems Improve your capability to think and reason3

w w

. w

tu jn

or w

. ld

m o c

www.jntuworld.com

www.jntuworld.com

What do I expect from you Active and critical participation

speed me up or slow me down if my pace mismatches yours Your role is not one of sponges, but one of whetstones; only then the spark of intellectual excitement can continue to jump over Read the textbook

Do your homeworks You can discuss homework with your classmates, but need to write down solutions independently4

w w

. w

tu jn

or w

. ld

m o c

www.jntuworld.com

www.jntuworld.com

VLSI (Very Large Scale Integrated) chips VLSI chips are everywhere computers

commercial electronics: TV sets, DVD, VCR, ... voice and data communication networks automobiles

VLSI chips are artifacts they are produced according to our will ...

w w

. w

tu jn

or w

. ld

m o c

5

www.jntuworld.com

www.jntuworld.com

Design: the most challenging human activity Design is a process of creating a structure to fulll a requirement Brain power is the scarcest resource Delegate as much as possible to computersCAD Avoid two extreme views:

Everything manual: impossiblemillions of gates Everything computer: impossible either

w w

. w

tu jn

or w

. ld

m o c

6

www.jntuworld.com

www.jntuworld.com

Design is always dicultA main task of a designer is to manage complexity Silicon complexity: physical eects no longer be ignored resistive and cross-coupled interconnects; signal integrity; weak and faster gates reliability; manufacturability System complexity: more functionality in less time gap between design and fabrication capabilities desire for system-on-chip (SOC)7

w w

. w

tu jn

or w

. ld

m o c

www.jntuworld.com

www.jntuworld.com

CAD: A tale of two designs Targethardware design

How to create a structure on silicon to implement a function Aidsoftware design (programming) How to create an algorithm to solve a design problem Be conscious of their similarities and dierences

w w

. w

tu jn

or w

. ld

m o c

8

www.jntuworld.com

www.jntuworld.com

Emphasis of the course Design ow

Understand how design process is decomposed into many stages What are the problems need to be solved in each stage Algorithms

Understand how an algorithm solves a design problem Consider the possibility to extend it Be conscious and try to improve problem solving skills9

w w

. w

tu jn

or w

. ld

m o c

www.jntuworld.com

www.jntuworld.com

Basics of MOS Devices The most popular VLSI technology: MOS (Metal-Oxide-Semiconductor).

CMOS (Complementary MOS) dominates nMOS and pMOS, due to CMOSs lower power dissipation, high regularity, etc. Physical structure of MOS transistors and their schematic icons: nMOS, pMOS. Layout of basic devices: CMOS inverter CMOS NAND gate CMOS NOR gate10

w w

. w

tu jn

or w

. ld

m o c

www.jntuworld.com

www.jntuworld.com

MOS Transistors gatedrain source conductor (polysilicon) insulator (SiO2) drain n n gate

psubstrate ntransistor

diffusion

The nMOS switch passes "0" well.

w w

. wdrain p

gate

tu jnsource p

or wdrain

substrate

schematic icon

. ldgate

source

m o c

conductor (polysilicon) insulator (SiO2)

source substrate

nsubstrate ptransistor

diffusion

schematic icon

The pMOS switch passes "1" well.11

www.jntuworld.com

www.jntuworld.com

A CMOS InverterMetal VDD Polysilicon Metaldiffusion contact pMOS transistor

nMOS transistor

A

GND

w w

. w

tu jnB Diffusion

or wA

. ld

m o cVDD B

A 1 0

B 0 1

pchannel (pMOS)

nchannel (nMOS) GND

layout12

www.jntuworld.com

www.jntuworld.com

A CMOS NAND GateMetal VDD Diffusion Polysilicon C A

GND

w w

jn . w

w tuB

orA

. ld

A 0 0 1 1

m o cVDD

B C 0 1 1 1 0 1 1 0

CB

GND

layout13

www.jntuworld.com

www.jntuworld.com

A CMOS NOR GateMetal VDD Polysilicon

A

C

GND

w

w w

jn .

w tuB Diffusion

or

. ld

A 0 0 1 1

m o cVDD

B C 0 1 1 0 0 0 1 0

A

C

B

GND

layout14

www.jntuworld.com

www.jntuworld.com

Current VLSI design phases Synthesis (i.e. specication implementation)

1. High level synthesis (459 VLSI Algorithmics) 2. Logic synthesis (459 VLSI Algorithmics) 3. Physical design (This course)

Analysis (implementation semantics) Verication (design verication, implementation verication) Analysis (timing, function, noise, etc.) Design rule checking, LVS (Layout Vs. Schematic)15

w w

. w

tu jn

or w

. ld

m o c

www.jntuworld.com

www.jntuworld.com

Physical Design Physical design converts a structural description into a geometric description. Physical design cycle: 1. Circuit partitioning 2. Floorplanning

3. placement, and pin assignment 4. Routing (global and detailed) 5. Compaction16

w w

. w

tu jn

or w

. ld

m o c

www.jntuworld.com

www.jntuworld.com

Design StylesIssues of VLSI circuits

Performance

Area

Full custom

w w

. w

tu jn

or wCost

. ld

Timetomarket

m o c

Different design styles

Standard cell

Gate array

FPGA

CPLD

SPLD

SSI

Performance, Area efficiency, Cost, Flexibility

17

www.jntuworld.com

www.jntuworld.com

Full Custom Design Style

Data path PLA

w w

jn . wpins

ROM/RAM

w tuController

or

. ldI/O

m o cvia (contact)

overthecell routing

A/D converter

Random logic

I/O pads

18

www.jntuworld.com

www.jntuworld.com

Standard Cell Design StyleD A C B

A

B

w w

. w

tu jnA B Cell B

D

C

or wD A

B

. ld

m o c

B

library cellsCell A

Cell C

Cell D

Feedthrough Cell

19

www.jntuworld.com

www.jntuworld.com

Gate Array Design Style

I/O pads

pins

prefabricated transistor array

w w

. w

tu jn

or w

. ld

m o ccustomized wiring

20

www.jntuworld.com

www.jntuworld.com

FPGA Design Style

logic blocks

w w

. w

tu jn

or w

. ld

m o c

routing tracks

switches Prefabricated all chip components21

www.jntuworld.com

www.jntuworld.com

SSI/SPLD Design Stylex1 y1 x2 y2 x3 y3 x4 y474LS86 x1 y1Vcc

74LS02Vcc

74LS00

Vcc

x3 y3

x2 y2

GND

F=

4 i=1

xi

yi

(a) 4bit comparator.

x1 y1 x2 y2 x3

w wx4 y4

y3

. w

tu jn

or wy4GND

x4

. ldGND

m o cx3 y3 x4 y4

F

(b) SSI implementation.

AND arrayx1 y1 x2 y2

OR array

F

(c) SPLD (PLA) implementation.

(d) Gate array implementation.

F

22

www.jntuworld.com

www.jntuworld.com

Comparisons of Design StylesCell size Cell type Cell placement Interconnections Full custom variable variable variable variable Standard cell xed height variable in row variable

* Uneven height cells are also used.

w w

. w

tu jn

or wGate array xed xed xed variable

. ld

m o cSPLD xed programmable xed programmable

FPGA xed programmable xed programmable

23

www.jntuworld.com

www.jntuworld.com

Comparisons of Design StylesFabrication time Packing density Unit cost in large quantity Unit cost in small quantity Easy design and simulation Easy design change Accuracy of timing simulation Chip speed + desirable not desirable Full custom +++ +++ +++

w w

. w

tu jn

or w

Standard cell ++ ++ ++

. ld

Gate array + + + + +

m o cFPGA +++ +++ ++ ++ +

SPLD ++ + + ++ +

24

www.jntuworld.com

www.jntuworld.com

Design-Style Trade-os104

10

3

10 Turnaround Time (Days) 10

2

w w1 1

. w10

tu jnSPLDs 102

or wCPLDs 103

. ld

m o csemi custom

Full custom

FPGAs

SSIs 104

optimal solution

10

5

10

6

10

7

Logic Capacity (Gates)

25

www.jntuworld.com

www.jntuworld.com

Algorithms 101

Algorithm: a nite step-by-step procedure to solve a problem Requirements:

Unambiguity: can even be followed by a machine Basic: each step is among a given primitives Finite: it will terminate for every possible input

w w

. w

tu jn

or w

. ld

m o c

26

www.jntuworld.com

www.jntuworld.com

A game

An ECE major is sitting on the Northwestern beach and gets thirsty, she knows that there is an ice-cream booth along the shore of Lake Michigan but does not know wherenot even north or south. How can she nd the booth in the shortest distance?

Primitives: walking a distance, turning around, etc.

w w

. w

tu jn

or w

. ld

m o c

27

www.jntuworld.com

www.jntuworld.com

A rst solution

Select a direction, say north, and keep going until nd the booth

Suppose the booth is to the south, she will never stop... of course, with the assumption she follows a straight line, not lake shore or on earth

w w

. w

tu jn

or w

. ld

m o c

28

www.jntuworld.com

www.jntuworld.com

Another solution Set the place she is sitting as the origin

Search to south 1 yard, if not nd, turn to north Search to north 1 yard, if not nd, turn to south Search to south 2 yard, if not nd, turn to north Search to north 2 yard, if not nd, turn to south

... (follow the above pattern in geometric sequence 1, 2, 4, 8, ...)

w w

. w

tu jn

or w

. ld

m o c

29

www.jntuworld.com

www.jntuworld.com

OR n = 1; While (not nd) do n = n + 1;

Search to south 2n, and turn; Search to north 2n, and turn;

w w

. w

tu jn

or w

. ld

m o c

29

www.jntuworld.com

www.jntuworld.com

Correctness proof Each time when the while loop is nished, the range from south 2n to north 2n is searched. Based on the fact that the booth is at a constant distance x from the origin, it will be within a range from south 2N to north 2N for some N . With n to increment in each loop, we will nd the booth in nite time.

Is this the fastest (or shortest) way to nd the booth?

w w

. w

tu jn

or w

. ld

m o c

30

www.jntuworld.com

www.jntuworld.com

Analysis of algorithm Observation: the traveled distance depends on where is the booth Suppose the distance between the booth and the origin is x When the algorithm stops, we should have 2n x but 2n1 < x The distance traveled is

which is smaller than 14x We know that the lower bound is x, can we do better?31

w w

3 2n + 2(2 2n1 + 2 2n2 + + 2) 7 2n

. w

tu jn

or w

. ld

m o c

www.jntuworld.com

www.jntuworld.com

Complexity of an algorithm Two resources: running time and storage

They are dependent on inputs: expressed as functions of input size Why input size: lower bound (at least read it once) Big-Oh notation: f (n) = O(g(n)) if there exist constants n0 and c such that for all n > n0, f (n) c g(n). Make our life easy: is it 13x instead of 14x in our game The solution is asymptotically optimal for our game

w w

. w

tu jn

or w

. ld

m o c

32

www.jntuworld.com

www.jntuworld.com

Time complexity of an algorithm

Run-time comparison: 1000 MIPS (Yr: 200x), 1 instr. /op.Time 500 3n n log n n2 n3 2n n! Big-Oh O(1) O(n) O(n log n) O(n2 ) O(n3 ) O(2n ) O(n!) n = 10 5 107 sec 3 108 sec 3 108 sec 1 107 sec 1 106 sec 1 106 sec 0.003 sec n = 100 5 107 sec 3 107 sec 2 107 sec 1 105 sec 0.001 sec 3 1017 cent. -

Polynomial-time complexity: O(p(n)), where n is the input size and p(n) is a polynomial function of n.

w w

. w

tu jn

or w

. ld

m o c

n = 103 5 107 sec 3 106 sec 3 106 sec 0.001 sec 1 sec -

n = 106 5 107 sec 0.003 sec 0.006 sec 16.7 min 3 105 cent. -

33

www.jntuworld.com

www.jntuworld.com

Complexity of a problem Given a problem, what is the running time of the fastest algorithm for it? Upper bound: easynd an algorithm with less time Lower bound: hardevery algorithm requires more time P: set of problems solvable in polynomial time NP(Nondeterministic P): set of problems whose solution can be proved in polynomial time Millennium open problem: NP = P? Fact: there are a set of problems in NP resisting any polynomial solution for a long time (40 years)34

w w

. w

tu jn

or w

. ld

m o c

www.jntuworld.com

www.jntuworld.com

NP-complete and NP-hard

Cook 1970: If the problem of boolean satisability can be solved in poly. time, so can all problems in NP. Such a problem with this property is called NP-hard. If a NP-hard problem is in NP, it is called NP-complete. Karp 1971: Many other problems resisting poly. solutions are NP-complete.

w w

. w

tu jn

or w

. ld

m o c

35

www.jntuworld.com

www.jntuworld.com

How to deal with a hard problem Prove the problem is NP-complete:

1. The problem is in NP (i.e. solution can be proved in poly. time) 2. It is NP-hard (by polynomial reducing a NP-complete problem to it) Solve NP-hard problems:

Exponential algorithm (feasible only when the problem size is small) Pseudo-polynomial time algorithms Restriction: work on a subset of the input space36

w w

. w

tu jn

or w

. ld

m o c

www.jntuworld.com

www.jntuworld.com

Approximation algorithms: get a provable close-to-optimal solution

Heuristics: get a as good as possible solution Randomized algorithm: get the solution with high probability

w w

. w

tu jn

or w

. ld

m o c

36

www.jntuworld.com

www.jntuworld.com

Algorithmic Paradigms Divide and conquer: divide a problem into sub-problems, solve sub-problems, and combine them to construct a solution. Greedy algorithm: optimal solutions to sub-problems will give optimal solution to the whole problem. Dynamic programming: solutions to a larger problem are constructed from a set of solutions to its sub-problems. Mathematical programming: a system of optimizing an objective function under constraints functions. Simulated annealing: an adaptive, iterative, non-deterministic algorithm that allows uphill moves to escape from local optima.37

w w

. w

tu jn

or w

. ld

m o c

www.jntuworld.com

www.jntuworld.com

Branch and bound: a search technique with pruning. Exhaustive search: search the entire solution space.

w w

. w

tu jn

or w

. ld

m o c

37

www.jntuworld.com

Top Related