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    UNIT I

    INTRODUCTION

    Integrated Circuit(IC)

    An integrated circuit (IC), or microchip, is a semiconductor wafer on which thousands or millions of tinyresistors, capacitors, and transistors are fabricated An IC can function as an amplifier, oscillator, timer, counter,computer memory, or microprocessor

    Ad!antages of IC

    " #iniature in si$e As fabrication process is used for the integration of acti!e and passi!e components on to asilicon chip, the IC becomes a lot smaller %hen compared to a discrete circuit, it may be at least a thousandtimes smaller

    & To produce hundreds of discrete circuits on a 'C for the same logic taes more time and increase the costfactor ut for the production of hundreds of IC*s the cost of production will be !ery low and less timeconsuming+ The small si$e of IC*s causes lesser power consumption and lesser power loss Increased operating speed because of absence of parasitic capacitance effect- Impro!ed functional performance as more comple. circuits can be fabricated for achie!ing bettercharacteristics/As all the components are fabricated !ery close to each other in an IC, they are highly suitable for smallsignal operation, as there won*t be any stray electrical picup

    0isad!antages of Integrated Circuits" 1ome comple. IC*s maybe costly If such integrated circuits are used roughly and become faulty, they ha!e to

    be replaced by a new one They cannot be repaired as the indi!idual components inside the IC are too small

    &1ome components lie transformers and inductors cannot be integrated into an IC They ha!e to be connectede.ternally to the semiconductor pins+It is difficult to achie!e low temperature coefficient It is not possible to fabricate capacitors that e.ceed a !alue of +2p3 Thus, high !alue capacitors are to beconnected e.ternally to the IC

    Integrated Circuit ClassificationICs can be classified on the basis of their chip si$e as gi!en below4

    1mall scale integration (11I)5+ to +2 gates6chip

    #edium scale integration (#1I)5+2 to +22 gates6chip

    7arge scale integration (71I)5+22 to +,222 gates6chip

    8ery large scale integration (871I)5more than +,222 gates6chipultra9scale integration (U71I) 9 "22,222 and more

    :n the basis of applications ICs are of two types namely4 7inear Integrated Circuits and 0igitalIntegrated Circuits

    Linear ICsha!e continuously !ariable output that depends on the input signal le!el As the termimplies, the output signal le!el is a linear function of the input signal le!el The operationalamplifier(op amp) is a common de!ice in these applications

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    Digital ICsoperate at only a few defined le!els or states, rather than o!er a continuous range ofsignal amplitudes These de!ices are used in computers, computer networs, modems, and fre;uencycounters The fundamental building blocs of digital ICs are logic gates, which wor with binary data,that is, signals that ha!e only two different states, called low (logic 2) and high (logic ")

    "#onolithic Integrated CircuitsThe word

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    1. Process steps in IC fabrication

    abrication of Integrated Circuits

    The basic semiconductor materials used in chips are crystalline silicon

    1.1.1Cr!stals

    1olid materials are classified by the way the atoms are arranged within the solid #aterials in whichatoms are placed at random are called amorphous #aterials in which atoms are placed in a highordered structure are called crystalline 'oly9crystalline materials are materials with a high degree ofshort9range order and no long9range order These materials consist of small crystalline regions withrandom orientation called grains, separated by grain boundaries

    The crystal can be thought of as consisting of two separate parts4 the lattice and the basis The latticeis an ordered arrangement of points in space, while the basis consists of the simplest arrangement of

    atoms which is repeated at e!ery point in the lattice to build up the crystal structure 3ig illustrates thebasis and lattice in a crystal

    A crystal structure is composed of a unit cell, a set of atoms arranged in a particular way and isperiodically repeated in three dimensions on a lattice In a cubic system, the lattice parameter is theside length of a cube and angles between the edges are ?2 The cubic lattices are an important subsetof these fourteen ra!ais lattices since a large number of semiconductors are cubic The three cubiclattices are the simple cubic lattice, the body9centered cubic lattice and the face9centered cubic latticeas shown in 3ig++ The positions of the atoms inside the unit cell are described by the set of atomic

    positions (., y, $) measured from a lattice point

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    In 1imple Cubic (1C) structure, atoms lie on the corners of a cube as shown in 3ig 8ery fewcrystals e.hibit this structure In this structure each atom has si. e;uidistant nearestneighbors

    In ody centered Cubic (CC) structure, structure atoms lie on the corners of a cube with anadditional atom at the centre of the cube as shown in 3ig& Its atomic positions are (222),

    ("22), (2"2), (22"), ("2"), (""2), (2""), (""") and ( , , ) #etals lie #olybdenum,tantalum (Ta) and tungsten (%), iron (3e), 'latinum ('t), 1odium (Na) and 'otassium (@)ha!e this structure In this structure each atom has eight nearest neighbours y placement ofan atom at the center of the cube, the body9centered cubic structure has twice the atomdensity of the simple cubic lattice

    In 3ace centered Cubic (3CC) structure, atoms lie on the corners of a cube with additionalatoms at the centers of each cube face as shown in 3ig + Its atomic positions are (222),

    ("22), (2"2), (22"), ("2"), (""2), (2""), ("""), ( , , 2), ( , 2, ), ( 2, , ),

    , , 2), ( , ", , 2) and (", , ) In this structure each atom has twel!ee;uidistant nearest neighbours 0ue to its low energy, 3CC is e.tremely common and thee.amples are lead ('b), aluminum (Al), copper (Cu), and gold (Au)

    The most common crystal structure among fre;uently used semiconductors such as siliconand germanium is the diamond lattice, shown in 3ig ach atom in the diamond lattice has a

    co!alent bond with four adBacent atoms, which together form a tetrahedron

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    1.1." #$! and $o% is silicon pre&ailing as a se'iconductor

    The semiconductor materials are either silicon and germanium or compound such as gallium

    arsenide 1ilicon is the most used semiconductor for discrete de!ices and integrated circuits

    1i is less e.pensi!e due to the greater abundance of element The maBor raw material for 1iwafer fabrication is sand and there is lots of sand a!ailable in nature

    1ilicon has large band gap than =e(""e8)

    The structure of =ermanium crystals will be destroyed at higher temperature >owe!er,1ilicon crystals are not easily damaged by e.cess heat

    ut there is a disad!antage for 1ilicon o!er =ermanium The potential arrier of 1ilicon ismore compared to =ermanium

    "& Cr!stal ro%t$

    Integrated circuits are built on single9crystal silicon substrates that possess a high degree ofchemical purity, a high degree of crystalline perfection, and high structure uniformity 1uchsilicon crystal preparation in!ol!es two maBor steps4 (") refinement of raw material (such as;uart$ite, a type of sand) into electronic grade polycrystalline silicon (=1) and (&) growing

    of single9crystal silicon from this =1 either by C$ochralsi or 3loat one process

    A single9crystal 1i or mono crystalline silicon or mono91i is a base material of the electronicindustry It consists of silicon in which the crystal lattice of the entire solid is continuous,unbroen to its edges The mono crystalline form is used in the semiconductor de!icefabrication since grain boundaries would bring discontinuities and fa!our imperfections in themicrostructure of silicon, such as impurities and crystallographic defects, which can ha!esignificant effects on the local electronic properties of the material

    1.".1 *etallurgical rade +ilicon(#=1), #=1 is poly crystalline material with a purity of

    about ??D It is made by the reduction of 1i:& (;uart$ sand) with carbon (coal) in hugefurnaces lined with carbon, with big graphite electrodes inside (carrying huge amounts ofcurrent) at about &222EC The reaction is

    C (s) F 1i:&(s) 1i (l) F C: (g)

    The process starts by the production of #etallurgical =rade 1ilicon (#=1) by charging itwith ;uart$ite and carbon in an arc furnace Guart$ite is a relati!ely pure form of sand (1iG&),and carbon is obtained in the form of coal, coe, and wood chips

    The o!erall reaction in the furnace is gi!en below

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    1iCF1i2& H 1i F 1i: F C:

    The #=1 after being drawn off, has to be solidified at a purity of ?D ut this purity is notenough for the manufacture of semiconductor de!ices 1o, the #=1 has to be pul!eri$edmechanically and reacted with anhydrous hydrogen chloride (>CI) to form trichlorosilane(1i>CI+) The reaction is shown below

    1i F +>Cl H 1i>CI+ F >&

    %ith the help of a catalyst, the reaction taes place at a nominal temperature of +22EC Thereaction creates products lie silicon tetrachloride (1iCl) and the chlorides of impurities Atthis point the purification process occurs The purification process has to be done byfractional distillation method as the products trichlorosilane and unwanted chlorides areli;uids at room temperature

    The purified 1i>CI+ is subBected to chemical !apor deposition (C80) The chemical reactionis a hydrogen reduction of 1i>Cl+

    The chemical reaction is shown below

    &1i>Cl+ F &>& H &1i F />Cl

    lectronic9=rade 1ilicon (=1) is the raw material that is used for the preparation of single9crystalsilicon =1 is actually a polycrystalline material of high purity =1 has some maBor impurities lie

    boron, carbon, and residual donors The pure =1 will ha!e doping elements in the parts per billion(ppb) range, and carbon less than & parts per million (ppm)

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    The ne.t step is to con!ert this poly91i to a single crystal There are two methods for crystal growthused in this caseJ C$ochralsi or crucible grown crystals (C crystals) and 3loat $one (3) crystals

    1.".,C-oc$ralsi Cr!stal ro%t$ Process

    The highly refined silicon (=1) though free from impurities, is still polycrystalline TheC$ochralsi crystal growth process is often used for producing single9crystal silicon ingotsThe diagram is gi!en below

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    1ince monolithic ICs are usually fabricated on a substrate which is doped with impurity, thepoly9crystalline silicon with an appropriate amount of dopant is9put into a ;uart$ crucible,which is then placed inside a crystal growth furnace The material is then heated to atemperature that is slightly in e.cess of the silicon melting pint of "&2 degree Celsius Asmall single9crystal rod of silicon called a seed crystal is then dipped into the silicon melt

    The conduction of heat up the seed crystal will produce a reduction in the temperature of themelt in contact with the seed crystal to slightly below the silicon melting point The siliconwill therefore free$e onto the end of the seed crystal, and as the seed crystal is slowly pulledup out of the melt it will pull up with it a solidified mass of silicon that will be acrystallographic continuation of the seed crystal oth the seed crystal and the crucible arerotated but in opposite directions during the crystal pulling process in order to producecrystalline ingots of circular cross section

    The li;uid solid interface remains near to the surface of the melt if the temperature andpulling rate are correctly chosen !en a long single crystal silicon is pulled from it Thediameter of the ingot is controlled by the pulling rate and the melt temperature, with ingot

    diameters of about "22 to "-2 mm ( to / inches) being the most common The ingot lengthwill generally be of the order of + meter, and se!eral hours are re;uired for the KpullingL of acomplete ingot The crystal pulling is done in an inert9gas atmosphere (usually argon orhelium), and sometimes a !acuum is used This is done to pre!ent o.idationL

    The pull9rate is closely related to the heat input and losses, crystal properties and dimensionsThe conditions for crystal pulling are therefore carefully controlled 3or e.ample, the melttemperature is monitored with a thermocouple and feedbac controller The crystal growthapparatus shown in the figure abo!e consists of the following parts

    3urnace Crystal pulling mechanism

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    Ambient control facility Control system circuitry

    The furnace consists of a crucible, susceptor (crucible support) and rotational mechanism,heating element and power supply, and a chamber As the crucible contains the melt, it is themost important component of the growth apparatus The crucible material should bechemically unreacti!e with molten silicon Also, the material should ha!e high melting point,

    thermal stability, and hardness The materials for crucible, which satisfy these properties, aresilicon nitride (1i+N) and fused silica (1i:&) 3used silicaJ howe!er, reacts with silicon,releasing silicon and o.ygen into the melt In tins process the crucible undergoes erosion Thesusceptor, is used to support the silica crucible It also pro!ides for better thermal conditions=raphite is the material of choice because of its high9temperature properties The graphiteshould be pure to pre!ent contamination of the crystal from impurities that would be!olatili$ed from the graphite at the temperature in!ol!ed The susceptor rests on a pedestalwhose shaft is connected to a motor that pro!ides rotation The whole assembly can usually

    be raised and lowered to eep the melt le!el e;uidistant from a fi.ed reference point, which isneeded for automatic diameter control

    The chamber housing the furnace must pro!ide easy access to the furnace components tofacilitate maintenance and cleaning The furnace structure must be airtight to pre!entcontamination from the atmosphere, and ha!e a specific design that does not allow any partof the chamber to become so hot that its !apour pressure would be a factor in contaminatingthe crystal >ottest parts of the apparatus are water cooled Insulation is usually pro!ided

    between the heater and the chamber wall

    The crystal9pulling mechanism consists of seed shaft or chain, rotation mechanism, and seedchuc The mechanism controls two parameters of die growth process4 pull rate and crystalrotation Also, the pulling mechanism must ha!e minimum !ibration and great precision Theseed holder and pulling mechanism must maintain precise orientation perpendicular to themelt surface

    3rom the figure we can see that the crystal lea!es the furnace through a purge tube, whereambient gas, if present, is directed along the surface of the crystal to cool it 3rom the purgetube, the crystal enters an upper chamber, which is usually separated from the furnace by anisolation !al!e

    The ambient control for the crystal growth apparatus consists of gas source, flow control,purge lube, and e.haust or !acuum system The crystal growth must be conducted in an inertgas or !acuum as staled earlier This is necessary becauseThe hot graphite parts must be

    protected from o.ygen to pre!ent erosion and The gas around the process should not reactwith the molten silicon =rowth in !acuum meets these re;uirements

    =rowth in a gaseous atmosphere, generally used on large growers, must use an inert gas suchas helium or argon The inert gas may be at atmospheric pressure or at reduced pressure

    The control system for crystal growing may consist of micro processing sensors, and outputsand pro!ides control of process parameters such as temperature, crystal diameter, pull rateand rotation speed

    1.2.4 Ingot Trimming and Slicing

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    As soon as the crystal ingot is obtained using the abo!e processes, the e.treme top andbottom portions of the ingot are cut off and the ingot surface is grounded to produce aconstant and e.act diameter The normal diameter is usually "22,"&-, or "-2 mm Acrystallographic orientation flat is also ground along the length of the ingot The ingot is thensliced using a large9diameter stainless steel saw blade with industrial diamonds embeddedinto the inner9diameter cutting edge This will help in producing circular slices or wafers that

    are about /22 to "222 micro meters thic The orientation flat ser!es as a useful referenceplane for !arious de!ice processes

    1.2.5 Wafer Polishing and leaning

    %hen the wafer is sliced, its surface will be hea!ily damaged This can be made normal onlyby polishing The reasons for polishing are gi!en below

    To remo!e the damaged silicon from the sawn surface

    To produce a highly planar or flat surface that will be re;uired for the photo9lithographic

    process especially when flue9line geometries are in!ol!ed

    To impro!e the parallel

    The sliced wafer will ha!e saw mars and is 2/ to " mm thic This is ;uite rough >ence ithas to be lapped to produce a flat surface The wafer, before polishing, may ha!e a surfacedamage in the order of M- micro meters !en through lapping, only /2 micro meters can be

    polished and scraped The remaining "- micro meters has to be remo!ed with the help ofetching process The chemical etch consists of an acid mi.ture, including nitric acid too.idi$e the surface and hydrofluoric acid to dissol!e the o.ide

    The wafer is then made into a mirror lie finish by polishing it This polishing is carried outby using aluminium abrasi!e powders of decreasing grit si$e (down to a final " micro metersdiameter) !en after the polishing, the wafer will still ha!e a surface damage of around &micro meters deep This is remo!ed by an additional chemical etching stage, which cansometimes be simultaneous with the final polishing stage

    In most cases, only one side of the wafer s carefully polished to produce a mirror lie image

    The other side is gi!en a normal lapping procedure to pro!ide a somewhat flat surface withagreeable parallelism After the wafer polishing operations are completed, the wafers arethoroughly cleaned, and dried, and they are now ready to be used for the !arious processingsteps described in the following sections efore discussing these steps let us discuss some

    processing considerations necessary to maintain the purity and perfection of the material

    1. C$e'ical Cleaning

    The wafers are cleaned thoroughly as soon as the polishing is completed :riginally, thesilicon wafers are cleaned so as to remo!e all organic films, hea!y metals, and particulars4

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    The commonly used cleaning agents are a;ueous mi.tures of N/0O/ /"O" /CI /"O" and/"+O0 /"O".

    ". ettering Treat'ents

    The transition group elements which act as the metallic impurities are located at theinterstitial or substitutional lattice sites and act as generation9recombination centres for thecarriers The precipitated forms of these impurities are usually silicides These silicides arenown to be electrically conducti!e In the case of 871I circuits, these transition groupelements decrease their performance, especially in the case of dynamic random accessmemories and narrow9base bipolar transistors, as they are sensiti!e to conducti!e impurity

    precipitatesNormally, a process called gettering treatment is carried out to remo!e the impuritiesettering is a process that remo!es, and harms the impurities or defects them from theregions in a wafer where de!ices are fabricated 'regettering refers to a gettering treatment

    pro!ided to silicon wafers that are used for IC processing %hen the wafer with sins arede!eloped for de!ice processing, the impurities are absorbed with the help of pregettering

    process The common techni;ues that are used for gettering treatment are gi!en below4

    Common mechanical abrasion methods lie lapping and sand blasting are carried out todamage the bac surface of the wafer

    A focused heat beam from a G9pulsed, Nd9A= laser is used to damage the wafer0islocations are made in the wafer by rastering the laser beam along the wafer*s bac surfaceThus they become fa!orable trapping sites for fast9diffusing species

    Intrinsic gettering As told earlier, when an impurity o.ygen precipitates, defects aregenerated The defects generated by o.ygen precipitation are useful as trapping sites As thewafer is needed for de!ice fabrication, high temperature cycle is employed to lower theo.ygen content near the surface of the wafer Additional thermal cycles are added to promotethe formation of o.ygen precipitates and defects in the interior of the wafer

    1.3 Difusion o Dopant Impurities

    The process of Bunction formation, that is transition from p to n type or !ice !ersa, is typicallyaccomplished by the process of diffusing the appropriate dopant impurities in a hightemperature furnace Impurity atoms are introduced onto the surface of a silicon wafer anddiffuse into the lattice because of their tendency to mo!e from regions of high to lowconcentration 0iffusion of impurity atoms into silicon crystal taes place only at ele!atedtemperature, typically ?22 to ""22EC

    Although these are rather high temperatures, they are still well below the melting point ofsilicon, which is at "&2EC The rate at which the !arious impurities diffuse into silicon will

    be of the order of " micro meter per hour at a temperature range stated abo!e, and thepenetration depth that are in!ol!ed in most diffusion processes will be of the order of 2+ to+2 micro meter At room temperature the diffusion process will be so e.tremely slow such

    that the impurities can be considered to be essentially fro$en in place

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    A method of p9n Bunction formation which was popular in the early days is the grownBunction techni;ue In this method the dopant is abruptly changed in the melt during theprocess of crystal growth A con!enient techni;ue for maing p9n Bunction is the alloying of ametal containing doping atoms on a semiconductor with the opposite type of dopant This iscalled the alloyed Bunction techni;ue The p9n Bunction using epita.ial growth is widely usedin ICs An epita.ial grown Bunction is a sharp Bunction In terms of !olume of production, the

    most common techni;ue for forming p9n Bunctions is the impurity diffusion process Thisproduces diffused Bunction Along with diffusion process the use of selecti!e masing tocontrol Bunction geometry, maes possible the wide !ariety of de!ices a!ailable in the form ofIC*s 1electi!e diffusion is an important techni;ue in its controllability, accuracy and!ersatility

    1.3.2Nature o Impurity Difusion

    The diffusion of impurities into a solid is basically the same type of process as occurs whene.cess carriers are created non9uniformly in a semiconductor which cause carrier gradient In

    each case, the diffusion is a result of random motion, and particles diffuse in the direction ofdecreasing concentration gradient The random motion of impurity atoms in a solid is, ofcourse, rather limited unless the temperature is high Thus diffusion of doping impurities intosilicon is accomplished at high temperature as stated abo!e

    There are mainly two types of physical mechanisms by which the impurities can diffuse intothe lattice They are

    1. +ubstitutional Diffusion

    At high temperature many atoms in the semiconductor mo!e out of their lattice site, lea!ing!acancies into which impurity atoms can mo!e The impurities, thus, diffuse by this type of!acancy motion and occupy lattice position in the crystal after it is cooled Thus,substitutional diffusion taes place by replacing the silicon atoms of parent crystal byimpurity atom In other words, impurity atoms diffuse by mo!ing from a lattice site to aneighbouring one by substituting for a silicon atom which has !acated a usually occupied siteas shown in the figure below

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    1ubstitutional diffusion mechanism is applicable to the most common diffusants, such asboron, phosphorus, and arsenic These dopants atoms are too big to fit into the interstices or!oids, so the only way they can enter the silicon crystal is to substitute for a 1i atom

    In order for such an impurity atom to mo!e to a neighbouring !acant site, it has to o!ercomeenergy barrier which is due to the breaing of co!alent bonds The probability of its ha!ingenough thermal energy to do this is proportional to an e.ponential function of temperatureAlso, whether it is able to mo!e is also dependent on the a!ailability of a !acant neighbouringsite and since an adBacent site is !acated by a 1i atom due to thermal fluctuation of the lattice,the probability of such an e!ent is again an e.ponent of temperature

    ". Interstitial Diffusion

    In such, diffusion type, the impurity atom does not replace the silicon atom, but insteadmo!es into the interstitial !oids in the lattice The main types of impurities diffusing by suchmechanism are =old, copper, and nicel =old, particularly, is introduced into silicon to

    reduce carrier life time and hence useful to increase speed at digital IC*s

    ecause of the large si$e of such metal atoms, they do not usually substitute in the siliconlattice To understand interstitial diffusion, let us consider a unit cell of the diamond lattice ofthe silicon which has fi!e interstitial !oids ach of the !oids is big enough to contain animpurity atom An impurity atom located in one such !oid can mo!e to a neighbouring !oid,as shown in the figure below

    1.,.0 ic2s 3a%s of Diffusion

    The diffusion rate of impurities into semiconductor lattice depends on the following

    #echanism of diffusion

    Temperature

    'hysical properties of impurity

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    The properties of the lattice en!ironment

    The concentration gradient of impurities

    The geometry of the parent semiconductor

    The beha!iour of diffusion particles is go!erned by 3ic*s 7aw, which when sol!ed for appropriateboundary conditions, gi!es rise to !arious dopant distributions, called profiles which areappro.imated during actual diffusion processes

    In "--, 3ic drew analogy between material transfer in a solution and heat transfer by conduction3ic assumed that in a dilute li;uid or gaseous solution, in the absence of con!ection, the transfer ofsolute atoms per unit area in a one9dimensional flow can be described by the following e;uation

    3 H 90 ON(.,t)6O. H 9O3(.,t)6O.

    where 3 is the rate of transfer of solute atoms per unit area of the diffusion flu. density (atoms6cm&9

    sec) N is the concentration of solute atoms (number of atoms per unit !olume6cm+), and . is thedirection of solute flow (>ere N is assumed to be a function of . and t only), t is the diffusion time,and 0 is the diffusion constant (also referred to as diffusion coefficient or diffusi!ity) and has units ofcm&6sec

    The abo!e e;uation is called 3ic*s 3irst law of diffusion and states that the local rate of transfer(local diffusion rate) of solute per unit area per unit time is proportional to the concentration gradientof the solute, and defines the proportionality constant as the diffusion constant of the solute Thenegati!e sign appears due to opposite direction of matter flow and concentration gradient That is, thematter flows in the direction of decreasing solute concentration

    3ic*s first law is applicable to dopant impurities used in silicon In general the dopant impurities arenot charged, nor do they mo!e in an electric field, so the usual drift mobility term (as applied toelectrons and holes under the influence of electric field) associated with the abo!e e;uation can beomitted In this e;uation N is in general function of ., y, $ and t

    The change of solute concentration with time must be the same as the local decrease of the diffusionflu., in the absence of a source or a sin This follows from the law of conser!ation of matterTherefore we can write down the following e;uation ON(.,t)6Ot H 9O3(.,t)6O.

    1ubstituting the abo!e e;uation to

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    complimentary error function (erfc) and limited source distribution following =aussiandistribution function

    Constant +ource (erfc) Distribution

    In this impurity distribution, the impurity concentration at the semiconductor surface ismaintained at a constant le!el throughout the diffusion cycle That is,

    N (ot) 5 N+ 5 Constant

    The solution to the diffusion e;uation which is applicable in this situation is most easilyobtained by first considering diffusion inside a material in which the initial concentrationchanges in same plane as .H2, from N1 to 2 Thus the e;uation can be written as

    N (ot) 5 N+ 5 Constant and N(6t) 5 7

    1hown below is a graph of the complementary error function for a range of !alues of itsargument The change in concentration of impurities with time, as described by the e;uation

    is also shown in the figure below The surface concentration is always held at N1, falling tosome lower !alue away from the surface If a sufficiently long time is allowed to elapse, it is

    possible for the entire slice to ac;uire a dopant le!el of N1per m+

    If the diffused impurity type is different from the resisti!ity type of the substrate material, aBunction is formed at the points where the diffused impurity concentration is e;ual to thebacground concentration already present in the substrate

    In the fabrication of monolithic IC*s, constant source diffusion is commonly used for theisolation and the emitter diffusion because it maintains a high surface concentration by acontinuous introduction of dopant

    There is an upper limit to the concentration of any impurity that can be accommodated at the

    semiconductor wafer at some temperature This ma.imum concentration which determines

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    the surface concentration in constant source diffusion is called the solid solubility of theimpurity

    1.,.4 3i'ited +ource Diffusion or aussian Diffusion

    >ere a predetermined amount of impurity is introduced into the crystal unlie constant sourcediffusion The diffusion taes place in two steps

    1. Predeposition +tep In this step a fi.ed number of impurity atoms are deposited on thesilicon wafer during s short time

    ". Dri&e8in step >ere the impurity source is turned off and the amounts of impuritiesalready deposited during the first step are allowed to diffuse into silicon water

    The essential difference between the two types of diffusion techni;ues is that the surfaceconcentration is held constant for error function diffusion It decays with time for the=aussian type owing to a fi.ed a!ailable doping concentration G 3or the case of modellingthe depletion layer of a p9n Bunction, the erfc is modelled as a step Bunction and the =aussianas a linear graded Bunction In the case of the erfc, the surface concentration is constant,typically the ma.imum solute concentration at that temperature or solid solubility limit

    1.,.9 Para'eters %$ic$ affect diffusion profile

    +olid +olubilit! In deciding which of the a!ailability impurities can be used, it isessential to now if the number of atoms per unit !olume re;uired by the specific

    profile is less than the diffusant solid solubility

    Diffusion te'perature >igher temperatures gi!e more thermal energy and thus

    higher !elocities, to the diffused impurities It is found that the diffusion coefficientcritically depends upon temperature Therefore, the temperature profile of diffusionfurnace must ha!e higher tolerance of temperature !ariation o!er its entire area

    Diffusion ti'e Increases of diffusion time, t, or diffusion coefficient 0 ha!e similareffects on Bunction depth as can be seen from the e;uations of limited and constantsource diffusions 3or =aussian distribution, the net concentration will decrease dueto impurity compensation, and can approach $ero with increasing diffusion tunes 3orconstant source diffusion, the net Impurity concentration on the diffused side of the p9n Bunction shows a steady increase with time

    +urface cleanliness and defects in silicon cr!stal The silicon surface must bepre!ented against contaminants during diffusion which may interfere seriously withthe uniformity of the diffusion profile The crystal defects such as dislocation orstacing faults may produce locali$ed impurity concentration This results in thedegradation of Bunction characteristics >ence silicon crystal must be highly perfect

    1.,.: ;asic Properties of t$e Diffusion Process

    3ollowing properties could be considered for designing and laying out ICs

    %hen calculating the total effecti!e diffusion time for gi!en impurity profile, onemust consider the effects of subse;uent diffusion cycles

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    The erfc and =aussian functions show that the diffusion profiles are functions of (.6S0t) >ence, for a gi!en surface and bacground concentration, the Bunction depth ."and .& associated with the two separate diffusions ha!ing different times andtemperature

    3ateral Diffusion 3+I Tec$nolog!

    The common dopants in 871I circuit fabrication are boron, phosphorus and arsenic'hosphorus is useful not only as an emitter and base dopant, but also far gettering fast9diffusing metallic contaminants, such as Cu and An, which cause Bunction leaage current

    problems Thus, phosphorus is indispensable in 871I technology >owe!er, n9p9n transistors

    made with arsenic9diffused emitters ha!e better low9current gain characteristics and bettercontrol of narrow base widths than those made with phosphorus9diffused emitters Therefore,in 8 71I, the use of phosphorus as an acti!e dopant in small, shallow Bunctions and low9temperature processing will be limited to its use as the base dopant of p9n9p de!ice and as agettering agent Arsenic is the most fre;uently used dopant for the source and drain regions inn9channel #:13Ts

    Diffusion +!ste's

    Impurities are diffused from their compound sources as mentioned abo!e The methodimpurity deli!ery to wafer is determined by the nature of impurity sourceJ Two9step diffusionis widely techni;ue Using this techni;ue, the impurity concentration and profiles can be

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    carefully controlled The type of impurity distribution (erfc or =aussian) is determined by thechoice of operating conditions

    The two9step diffusion consists of a deposition step and a dri!e9in step In the former step aconstant source diffusion is carried out for a short time, usually at a relati!ely lowtemperatures, say, "222EC In the latter step, the impurity supply is shutoff and the e.istingdopant is allowed to diffuse into the body of the semiconductor, which is now held at a

    different temperature, say "&22EC, in an o.idi$ing atmosphere The o.ide layer which formson tire surface of the wafer during this step pre!ents further impurities from entering, or thosealready deposited, from diffusing out The final impurity profile is a function of diffusioncondition, such as temperature, time, and diffusion coefficients, for each step

    Diffusion urnace

    3or the !arious types of diffusion (and also o.idation) processes a resistance9heated tubefurnace is usually used A tube furnace has a long (about & to + meters) hollow opening intowhich a ;uart$ tube about "22,"-2 mm in diameter is placed as shown in the figure below

    The tem"erat#re of the f#rnace is $e"t a%o#t1!!!&. The tem"erat#re 'ithin the(#art) f#rnace t#%e can %e controlled *er+ acc#ratel+ s#ch that a tem"erat#re

    'ithin 1,2& of the set-"oint tem"erat#re can %e maintained #niforml+ o*er ahot )one/ a%o#t 1 m in length. This is achie*ed %+ three indi*id#all+ controlledad0acent resistance elements. The silicon 'afers to %e "rocessed are stac$ed #"*erticall+ into slots in a (#art) carrier or %oat/ and inserted into the f#rnacel#%e.

    1.,.? Diffusion Of p8T!pe I'purit!

    oron is an almost e.clusi!e choice as an acceptor impurity in silicon It has a moderatediffusion coefficient, typically of order I29"/ m&6sec at ""-2EC which is con!enient for

    precisely controlled diffusion It has a solid solubility limit of around - . "2&/ atoms6m+, so

    that surface concentration can be widely !aried, but most reproducible results are obtained

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    when the concentration is appro.imately "2&6m+, which is typical for transistor basediffusions

    ;oron Diffusion using ;"/9(Diborane) +ource

    This is a gaseous source for boron This can be directly introduced into the diffusion furnaceA number of other gases are metered into the furnace The principal gas flow in the furnace

    will be nitrogen (N&) which acts as a relati!ely inert gas and is used as a carrier gas to be adilutent for the other more reacti!e gases The N&, carrier gas will generally mae up some ?2to ?? percent of the total gas flow A small amount of o.ygen and !ery small amount of asource of boron will mae up the rest of the gas flow This is shown in the figure below Thefollowing reactions will be occurring simultaneously at the surface of the silicon wafers4

    +i @ 7"5 +iO"(silica glass)

    ";"/9@ ,7"5 ;"O,(boron glass) @ 9/"

    This process is the chemical !apour deposition (C80) of a glassy layer on (lie silicon surface

    which is a mi.ture of silica glass (1i2&) and boron glass (&2+) is called borosilica glass(1=) The 1= glassy layer, shown in the figure below, is a !iscous li;uid at the diffusiontemperatures and the boron atoms can mo!e around relati!ely easily

    1.0 ION I*P3ANTATION

    Ion Implantation is an alternati!e to a deposition diffusion and is used to produce a shallowsurface region of dopant atoms deposited into a silicon wafer This technology has madesignificant roads into diffusion technology in se!eral areas In this process a beam of impurityions is accelerated to inetic energies in the range of se!eral tens of 8 and is directed to the

    surface of the silicon As the impurity atoms enter the crystal, they gi!e up their energy to thelattice in collisions and finally come to rest at some a!erage penetration depth, called theproBected range e.pressed in micro meters 0epending on the impurity and its implantationenergy, the range in a gi!en semiconductor may !ary from a few hundred angstroms to about"micro meter Typical distribution of impurity along the proBected range is appro.imately=aussian y performing se!eral implantations at different energies, it is possible tosynthesi$e a desired impurity distribution, for e.ample a uniformly doped region

    1.0.1Ion I'plantation +!ste'

    A typical ion9implantation system is shown in the figure below

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    gas containing the desired im"#rit+ is ioni)ed 'ithin the ion so#rce. The ionsare generated and re"elled from their so#rce in a di*erging %eam that isfoc#ssed %efore if "asses thro#gh a mass se"arator that directs onl+ the ions ofthe desired s"ecies thro#gh a narro' a"ert#re. second lens foc#ses thisresol*ed %eam 'hich then "asses thro#gh an accelerator that %rings the ions totheir re(#ired energ+ %efore the+ stri$e the target and %ecome im"lanted in thee"osed areas of the silicon 'afers. The accelerating *oltages ma+ %e from 2!$ to as m#ch as 25! $. In some ion im"lanters the mass se"aration occ#rsafter the ions are accelerated to high energ+. eca#se the ion %eam is smallmeans are "ro*ided for scanning it #niforml+ across the 'afers. or this "#r"osethe foc#ssed ion %eam is scanned electrostaticall+ o*er the s#rface of the 'aferin the target cham%er.

    1.0."Properties of Ion I'plantation

    The depth of penetration of any particular type of ion will increase with increasingaccelerating !oltage The penetration depth will generally be in the range of 2" to "2 micrometers

    1.4 Annealing after I'plantation

    After the ions ha!e been implanted they are lodged principally in interstitial positions in thesilicon crystal structure, and the surface region into which the implantation has taen placewill be hea!ily damaged by the impact of the high9energy ions The disarray of silicon atomsin the surface region is often to the e.tent that this region is no longer crystalline in structure,

    but rather amorphous To restore this surface region bac to a well9ordered crystalline stateand to allow the implanted ions to go into substitutional sites in the crystal structure, thewafer must be subBected to an annealing process The annealing process usually in!ol!es theheating of the wafers to some ele!ated temperature often in the range of "222EC for a suitablelength of time such as +2 minutes

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    7aser beam and electron9beam annealing are also employed In such annealing techni;uesonly the surface region of the wafer is heated and re9crystalli$ed An ion implantation processis often followed by a con!entional9type dri!e9in diffusion, in which case the annealing

    process will occur as part of the dri!e9in diffusion

    Ion implantation is a substantially more e.pensi!e process than con!entional depositiondiffusion, both in terms of the cost of the e;uipment and the throughput, it does, howe!er,

    offer following ad!antages

    1.0.0 Ad&antages of Ion I'plantation

    Ion implantation pro!ides much more precise control o!er the density of dopants depositedinto the wafer, and hence the sheet resistance This is possible because both the accelerating!oltage and the ion beam current are electrically controlled outside of the apparatus in whichthe implants occur Also since the beam current can be measured accurately duringimplantation, a precise ;uantity of impurity can be introduced Tins control o!er doping le!el,along with the uniformity of the implant o!er the wafer surface, mae ion implantationattracti!e for the IC fabrication, since this causes significant impro!ement in the ;uality of an

    IC

    0ue to precise control o!er doping concentration, it is possible to ha!e !ery low !alues ofdosage so that !ery large !alues of sheet resistance can be obtained These high sheetresistance !alues are useful for obtaining large9!alue resistors for ICs 8ery low9dosage, low9energy implantations are also used for the adBustment of the threshold !oltage of #:13T*sand other applications

    An ob!ious ad!antage of implantation is that it can be done at relati!ely low temperatures,this means that doped layers can be implanted without disturbing pre!iously diffused regionsThis means a lesser tendency for lateral spreading

    1.0.4 I'portance of Ion I'plantation for >3+I Tec$nolog!

    Ion implantation is a !ery popular process for 871I because it pro!ides more precise controlof dopants (as compared to diffusion) %ith the reduction of de!ice si$es to the submicronrange, the electrical acti!ation of ion9implanted species relies on a rapid thermal annealingtechni;ue, resulting in as little mo!ement of impurity atoms as possible Thus, diffusion

    process has become less important than methods for introducing impurity atoms into siliconfor forming !ery shallow Bunctions, an important feature of 871I circuits Ion, implantation

    permits introduction of the dopant in silicon that is controllable, reproducible and free from

    undesirable side effects :!er the past few years, ion implantation has been de!eloped into a!ery powerful tool for IC fabrication Its attributes of controllability and reproducibility maeit a !ery !ersatile tool, able to follow the trends to finer9scale de!ices Ion implantationcontinues to find new applications in 871 technologies

    1.4 Utilit! of T$er'al O6idation

    The function of a layer of silicon dio.ide (1i:&) on a chip is multipurpose 1i:& plays animportant role in IC technology because no other semiconductor material has a nati!e o.idewhich is able to achie!e all the properties of 1i: & The role of 1i:& in IC fabrication is as

    below 4

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    It acts as a diffusion mas permitting selecti!e diffusions into silicon wafer through thewindow etched into o.ide

    It is used for surface passi!ation which is nothing but creating protecti!e 1i:& layeron the wafer surface It protects the Bunction from moisture and other atmosphericcontaminants

    It ser!es as an insulator on the water surface Its high relati!e dielectric constant,which enables metal line to pass o!er the acti!e silicon regions

    1i:& acts as the acti!e gate electrode in #:1 de!ice structure

    It is used to isolate one de!ice from another

    It pro!ides electrical isolation of multile!el metalli$ation used in 871I

    It is fortunate that silicon has an easily formed protecti!e o.ide, for otherwise we should ha!e

    to depend upon deposited insulators for surface protection 1ince 1i:& produces a stablelayer, this has held bac germanium IC technology

    1.4." ro%t$ and Properties of O6ide 3a!ers on +ilicon

    1ilicon dio.ide (silica) layer is formed on the surface of a silicon wafer by thermal o.idationat high temperatures in a stream of o.ygen

    +i@7" 5 +iO"(solid)

    The o.idation furnace used for this reaction is similar to the diffusion furnace The thicness

    of the o.ide layer depends on the temperature of the furnace, the length of time that thewafers are in it, and the flow rate of o.ygen The rate of o.idation can be significantlyincreased by adding water !apour to the o.ygen supply to the o.idi$ing furnace

    +i @ "/"O 5 +iO"@ "/"

    The time and temperature re;uired to produce a particular layer thicness arc obtained fromempirically determined design cur!es, of the type shown in the figures gi!en belowcorresponding to dry9 o.ygen atmosphere and also corresponding to steam atmosphere

    1.4., ro%t$ Rate of +ilicon O6ide 3a!er

    The initial growth of the o.ide is limited by the rate at which the chemical reaction taesplace After the first "22 to +22 A of o.ide has been produced, the growth rate of the o.idelayer will be limited principally by the rate of diffusion of the o.idant (2&or >&2) through theo.ide layer, as shown in the figures gi!en below

    The rate of diffusion of :&or >&: through the o.ide layer will be in!ersely proportional tothe thicness of the layer, so that we will ha!e that

    d.6dt H C6.

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    where . is the o.ide thicness and C is a constant of proportionality earranging thise;uation gi!es

    .d. H Cdt

    Integrating this e;uation both sides yields, .&6& H Ct

    1ol!ing for the o.ide thicness . gi!es, . H S&Ct

    %e see that after an initial reaction9rate limited linear growth phase the o.ide growth willbecome diffusion9rate limited with the o.ide thicness increasing as the s;uare root of thegrowth time This is also shown in the figure below

    The rate of o.ide growth using > &: as the o.idant will be about four times faster than therate obtained with :& This is due to the fact that the >&: molecule is about one9half the si$eof the :& molecule, so that the rate of diffusion of >&: through the 1i:&layer will be muchgreater than the :&diffusion rate

    1.4., O6ide C$arges

    The interlace between silicon and silicon dio.ide contains a transition region 8arious chargesare associated with the o.idised silicon, some of which are related to the transition region Acharge at the interface can induce a charge of the opposite polarity in the underlying silicon,thereby affecting the ideal characteristics of the #:1 de!ice This results in both yield andreliability problems The figure below shows general types of charges

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    :.ide Charges

    Interface8trapped c$arges

    These charges at 1i91i:& are thought to result from se!eral sources including structuraldefects related to the o.idation process, metallic impurities, or bond breaing processes Thedensity of these charges is usually e.pressed in terms of unit area and energy in the silicon

    band gap

    i6ed o6ide c$arge

    This charge (usually positi!e) is located in the o.ide within appro.imately +2 A of the 1i 1i:&interface 3i.ed o.ide charge cannot be charged or discharged 3rom a processing pointof !iew, fi.ed o.ide charge is determined by both temperature and ambient conditions

    *obile ionic c$arge

    This is attributed to alali ions such as sodium, potassium, and lithium in the o.ides as wellas to negati!e ions and hea!y metals The alali ions are mobile e!en at room temperaturewhen electric fields are present

    O6ide trapped c$arge

    This charge may be positi!e or negati!e, due to holes or electrons trapped in the bul of theo.ide This charge, associated with defects in the 1i2&, may result from ioni$ing radiation,a!alanche inBection

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    + =roup III and 8 elements

    >alogen

    In addition damage to the silicon also affects o.idation rate As wet o.idation occurs at asubstantially greater rate than dry o.ygen, any unintentional moisture accelerates the dryo.idation >igh concentrations of sodium influence the o.idation rate by changing the bond

    structure in the o.ide, thereby enhancing the diffusion and concentration of the o.ygenmolecules in the o.ide

    0uring thermal o.idation process, an interface is formed, which separates the silicon fromsilicon dio.ide As o.idation proceeds, this interface ad!ances into the silicon A dopingimpurity, which is initially present in the silicon, will redistribute at the interface until itschemical potential is the same on each side of the interface This redistribution may result inan abrupt change in impurity concentration across the interface The ratio of the e;uilibriumconcentration of the impurity, that is, dopant in silicon to that in 1i: & at the interface is calledthe e;uilibrium segregation coefficient The redistribution of the dopants at the interfaceinfluences the o.idation beha!iour If the dopant segregates into the o.ide and remains there

    (such as oron, in an o.idi$ing ambient), the bond structure in the silica weaens Thisweaened structure permits an increased incorporation and diffusi!ity of the o.idi$ingspecies through the o.ide thus enhancing the o.idation rate Impurities that segregate into theo.ide but then diffuse rapidly through it (such as aluminium, gallium, and indium) ha!e noeffect on the o.idation inetics 'hosphorus impurity shows opposite effect to that of boron,that is, impurity segregation occurs in silicon rather than 1i2& The same is true for As and 1bdopants

    >alogen (such as chlorine) impurities are intentionally introduced into the o.idation ambientto impro!e both the o.ide and the underlying silicon properties :.ide impro!ement occurs

    because there is a reduction in sodium ion contamination, increase in o.ide breadown

    strength, and a reduction in interface trap density Traps arc energy le!els in the forbiddenenergy gap which are associated with defects in the silicon

    1.4.9 ro%t$ and Properties of T$in O6ides

    #:1 871I technology re;uires silicon dio.ide thicness in the -2 to -22 A range in arepeatable manner This section is de!oted to the growth and properties of such thin o.ideThis o.ide must e.hibit good electrical properties and pro!ide long9term reliability As ane.ample, the dielectric material for #:1 de!ices can be thin thermal o.ide This dielectric isan acti!e component of the storage capacitor in dynamic A#s, and its thicness determines

    the amount of charge that can be storedThe growth of thin o.ide must be slow enough to obtain uniformity and reproducibility8arious growth techni;ues for thin o.ide are dry o.idation, dry o.idation with >Cl,se;uential o.idations using different temperatures and ambients, wet o.idation, reduced

    pressure techni;ues, and high pressure6low temperature o.idation >igh pressure o.idation isdiscussed later The o.idation rate will, of course, be lower at lower temperatures and atreduced pressures Ultra9thin o.ide (-2 A) ha!e been produced using hot nitric acid, boilingwater, and air at room temperatures 1ome recent de!elopments in thin o.ide growthtechni;ue are

    (i) apid thermal o.idation performed in a controlled o.ygen ambient with heating pro!idedby tungsten9halogen lamps and

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    (ii) Ultra!iolet pulsed laser e.citation in an o.ygen en!ironment

    The properties of thin o.ide depend upon the growth techni;ue employed 3or e.ample,o.ide density increases as the o.idation temperature is reduced Additionally, >Cl ambientsha!e typically been used to passi!ate ionic sodium, impro!e the breadown !oltage, andgetter impurities and defects in the silicon This passi!ation effect begins to occur only in thehigher temperature range

    3or thin o.ides, there is an increase in leaage for a gi!en !oltage In thin o.ides thedielectric breadown may be field9dependent (breadown in a ramping field) or time9dependent (breadown at a constant field) This breadown is a failure mode for #:1 ICsThinner o.ides are more prone to failure

    /ig$ Pressure O6idation

    There is a benefit of increase in the o.idation rate if the thermal o.idation is carried out atpressures that are much abo!e atmospheric pressure The rate of diffusion of the o.idantmolecules through an o.ide layer is proportional to the ambient pressure 3or e.ample, at a

    pressure of "2 atm the diffusion rate will be increased by a factor of "2 and the correspondingo.idation time can be reduced by nearly the same factor Alternati!ely, the o.idation can bedone for the same length of time, but the temperature re;uired will be substantially lower

    Thus, one principal benefit of high9pressure o.idation processing is lower9temperatureprocessing The lower processing temperature reduces the formation of crystalline defectsand produces less effect on pre!ious diffusions and other processes The shorter o.idationtime is also ad!antageous in increasing the system throughput The maBor limitation of this

    process is the high initial cost of the system

    O6ide *asing

    The o.ide layer is used to mas an underlying silicon surface against a diffusion (or ionimplantation) process The o.ide layer is patterned by the phtolithographic process to produceregions where there are opening or KwindowsL where the o.ide has been remo!al to e.posethe underlying silicon Then these e.posed silicon regions are subBected to the diffusion (orimplantation) of dopants, whereas the une.posed silicon regions will be protected The

    pattern of dopant that will be deposited into the silicon will thus be a replication of the patternof opening in the o.ide layer The replication is a ey factor in the production of tinyelectronic components

    The thicness of o.ide needed for diffusion masing is a function of the type of diffusant andthe diffusion time and temperature conditions In particular, an o.ide thicness of some -222A will he !ufftcieni to mas against almost all diffusions This o.ide thicness will also besufficient to bloc almost alt but the highest9energy ion implantation

    O6ide Passi&ation

    The other function of 1i2&in IC fabrication is the surface passi!ation This is nothing butcreating protecti!e 1i2&layer on the wafer surface The figure below shows a cross9sectional!iew of a p9n Bunction produced by diffusion through an o.ide window There are lateraldiffusion effects, that is, the diffusion not only proceeds in the downward direction, but also

    sideways as well, since diffusion is an isotropic process The distance from the edge of theo.ide window to the Bunction in the lateral direction underneath die o.ide is indicated as yB

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    1.9 P$otolit$ograp$!

    %hen a sample of crystalline silicon is co!ered with silicon dio.ide, the o.ide9layer acts as abarrier to the diffusion of impurities, so that impurities separated from the surface of thesilicon by a layer of o.ide do not diffuse into the silicon during high9temperature processingA p9n Bunction can thus be formed in a selected location on the sample by first co!ering thesample with a layer of o.ide Po.idation stepR remo!ing the o.ide in the selected region, andthen performing a predeposition and diffusion step The selecti!e remo!al of the o.ide in thedesired area is performed with photolithography Thus, the areas o!er which diffusions areeffecti!e are defined by the o.ide layer with windows cut in it, through which diffusion cantae place The windows are produced by the photolithographic process This process is themeans by which microscopically small electronic circuits and de!ices can be produced on

    silicon wafers resulting in as many as "2222 transistors on a " cm . " cm chipIn fact photolithography or optical lithography is a ind of lithography The lithographytechni;ue was first used in the late "thcentury by people interested in art A lithograph is aless e.pensi!e picture made from a flat, specially prepared stone or metal plate and thelithography is art of maing lithographs Therefore, lithography for IC manufacturing isanalogous to the lithography of the art world In this process the e.posing radiation, such asultra!iolet (U8) light in case of photolithography, is transmitted through the clear parts of themas The circuit pattern of opa;ue chromium blocs some of die radiation This type ofchromium6glass mas is used with U8 light :ther types of e.posing radiations are electrons,V9rays, or ions Thus for IC manufacturing we ha!e following types of lithography

    'hotolithography has been e.plained in this post To now about the other types oflithographic process, clic on the lin below

    " P$otolit$ograp$!

    &

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    aligner The mas aligner may be contact type or pro.imity type or proBection typeAccordingly we ha!e three types of printing They are

    Contact printing

    'ro.imity printing

    'roBection printing

    1.9.1 P$otolit$ograp$ic Process +teps

    1. P$otoresist Application (+pinning)

    A drop of light9sensiti!e li;uid called photoresist is applied to the centre of the o.idi$edsilicon wafer that is held down by a !acuum chuc The wafer is then accelerated rapidly to arotational !elocity in the range +222 to M222 '# for some +2 to /2 seconds This actionspreads the solution in a thin, nearly uniform coat and spins off the e.cess li;uid The

    thicness of the coat so obtained is in the range -222 to "2222 A, as shown in the figurebelow The thicness of the photoresist layer will be appro.imately in!ersely proportional tothe s;uare root of the rotational !elocity

    1ometimes prior to the application of the photoresist the silicon wafers are gi!en a Kbae9outLat a temperature :f at least "22EC to dri!e off moisture from the wafer surfaces so as toobtain better adhesion of the photoresist Typical photoresist used is @oda Thin 3ilm esist(@T3)

    ". Prebae

    The silicon wafers coated with photoresist are now put into an o!en at about 2EC for about+2 to /2 minutes to dri!e off sol!ents in the photoresist and to harden it into a semisolid film

    ,. Align'ent and

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    Two types of photoresist e.ist9 negati!e photoresist and positi!e photoresist In the presentdescription negati!e photoresist is used in which the areas of the photoresist that are e.posedthe ultra!iolet radiation become polymeri$ed The polymeri$ation process increases thelength of the organic chain molecules that mae up the photoresist This maes the resisttougher and maes it essentially insoluble in the de!eloper solution The resisting photoresist

    pattern after the de!elopment process will therefore be a replication of the photomas pattern,with the clear areas on the photomas corresponding to the areas where the photoresist

    remains on the wafers, as shown in the figure below

    An opposite type of process occurs with positi!e photoresist .posure to U8 radiationresults in depolymeri$ation of the photoresist This maes these e.posed areas of the

    photoresist readily soluble in the de!eloper solution, whereas the une.posed areas areessentially insoluble The de!eloper solution will thus remo!e the e.posed or depolymeri$edregions of the photoresist, whereas the une.posed areas will remain on the wafer Thus againthere is a replication of the photomas pattern, but this time the clear areas of the photomas

    produce the areas on the wafer from which the photoresist has been remo!ed

    4. Postbae

    After de!elopment and rinsing the wafers are usually gi!en a postbae in an o!en at atemperature of about "-2EC for about +2 to /2 minutes to toughen further the remaining resiston the wafer This is to mae it adhere better to the wafer and to mae it more resistant to thehydrofluoric acid P>3R solution used for etching of the silicon dio.ide

    9. O6ide 3R acidsolution This solution is usually a diluted solution of typically "24 ", >&: 4 >3, or more oftena "2 4 " N>3 Pammonium fluorideR4 >3 solution The >3 solutions will etch the 1i: &butwill not attac the underlying silicon, nor will it attac the photoresist layer to anyappreciable e.tent The wafers are e.posed to the etching solution ion enough to remo!e the1i:&completely in the areas of the wafer that are not co!ered by the photoresist as shown inthe figure

    The duration of o.ide etching should be carefully controlled so that all of the o.ide present

    only in the photoresist window is remo!ed If etching time is e.cessi!ely prolonged, it willresult in more undercutting underneath the photoresist and widening of the o.ide openingbeyond what is desired

    The abo!e o.ide etching process is termed %et etc$ing processsince the chemical reagentsused are in li;uid form A newer process for o.ide etching is a dry etching process calledplas'a etc$ing Another dry etching process is ion milling

    :. P$otoresist +tripping

    3ollowing o.ide etching, the remaining resist is finally remo!ed or stripped off with a

    mi.ture of sulphuric acid and hydrogen pero.ide and with the help of abrasion process

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    3inally a step of washing and drying completes the re;uired window in the o.ide layer Thefigure below shows the silicon wafer ready for ne.t diffusion

    1.9." P$otoresists

    :ne of the maBor factors in pro!iding increasingly comple. de!ices has been impro!ement inphotolithographic art A large part of this impro!ement has been due to high ;ualityphotoresist, materials as impro!ed techni;ues of coating, baing, e.posing and de!elopingphotoresists

    The principal constituents of a photoresist solution are a polymer, a sensiti$er and a suitablesol!ent system 'olymers ha!e properties of e.cellent film forming and coating 'olymersgenerally used are poly!inyl cinnamate, partially cycli$ed isoprene family and other types are

    phenol formaldehyde

    %hen photoresist is e.posed to light, sensiti$er absorbs energy and initiates chemical changesin the resist The sensiti$ers are chromophoric organic molecules They greatly enhance crosslining of the photoresist Cross lining of polymer or long chain formation of considerablenumber of monomers maes high molecular weight molecules on e.posure to light radiation,termed as photo9polymeri$ation Typical sensiti$ers are carbonyl compounds, en$oin,en$oyl pero.ide, en$oyl disulphide, nitrogen compounds and halogen compounds

    The sol!ents used to eep the polymers in solution are mi.ture of organic li;uids Theyinclude aliphetic esters such as butyl acetate and cellosol!e acetate, aromatic hydrocarbonslie .ylene and thylben$ene, chlorinated hydrocarbons lie chloroben$ene and methylenechloride and etones such as cyclohe.anone The same sol!ents are used as thinners andde!elopers

    C$aracteristics of ood P$otoresist

    To achie!e faithful registration of the mas geometry o!er the substrate surface, the resistshould satisfy following conditions

    Uniform film formation

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    =ood adhesion to the substrate

    esolution

    esistance to wet and dry etch processes

    T!pes of P$otoresist

    'olymers film is either photosensiti!e or capable or reacting with the pholysis product ofadditional compound so that the solubility increases or decreases greatly by e.posure to U8(ultra9!iolet) radiation According to the changes that tae place, photoresists are termednegati!e or positi!e #aterials which are rendered less soluble in a de!eloper solution byilluminationW yield a negati!e pattern of the mas and are called negati!e photoresistsCon!ersely, positi!e photoresists become more soluble when subBected to light and thereforeyield a positi!e image of the mas

    Negati&e P$otoresist

    @oda negati!e photoresist contain poly!inyl cinnametes @' is being used in printingcircuit boards @T3 is widely used in fabrication of ICs It pro!ides good adhesion tosilicon dio.ide and metal surfaces It gi!es well etch results to different etchant solutions 3orfiner resolution, thinner coating of @T3 is used To achie!e controlled and uniformthicness, the !iscosity of resist is suitably lowered using thinners

    Another negati!e photoresist is @oda #icroneg MM which pro!ides high scan speeds athigh aperature gi!ing high throughput and resolution

    Positi&e P$otoresist

    'ositi!e 'hotoresists ha!e sol!ed the problem of resolution and substrate protection 'hotoresists can be used at a coating thicness of " micro meter that eliminates holes andminimises defects from dust

    'ositi!e photoresist is inherently of low solubility (polymeri$ed) material The base polymeris acti!e by itself A sensiti$er, when absorbs light, maes the base resist soluble in an alalide!eloper 'ositi!e photoresists are No!olac resins Typical sol!ents are cellosol!e acetate,

    butyl acetate, .ylene and toluene

    Resist reuire'ents for >3+I

    3or fine line geometries in 871I circuits, the resist re;uirements become more stringent Theresist properties should meet the re;uired demand of high resolution >ere the resist shoulde.hibit

    >igh sensiti!ity for partial e.posure tool chosen

    0ry de!eloping, dry compatibility

    8ertical profile control

    P$oto'as abrication

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    'hotolithography is used to produce windows in the o.ide layer of the silicon wafer, throughwhich diffusion can tae place 3or this purpose photomas is re;uired In this section weshall discuss !arious techni;ues of mas fabrication The pattern appearing on the mas isre;uired to be transferred to the wafer 3or this purpose !arious e.posure techni;ues areemployed %e will also discuss these techni;ues

    *as *aing

    IC fabrication is done by the batch processing, where many copies of the same circuit arefabricated on a single wafer and many wafers are fabricated at the same time The number ofwafers processed at one time is called the lot si$e and many !ary between &2 to &22 wafers1ince each IC chip is s;uare and the wafer is circular, the number of chips per wafer is thenumber of complete s;uares of a gi!en si$e that can fit inside a circle

    The pattern for the mas is designed from the circuit layout #any years ago, bread boardingof the circuit was typical In this, the circuit was actually built and tested with discretecomponents before its integration At present, howe!er, when 71I and 871I circuits containfrom a thousand to se!eral hundred thousand components, and switching speeds are of such

    high order where propagation delay time between de!ices is significant, bread boarding isob!iously not practical 'resent9day mas layout is done with the help of computer

    The photographic mas determines the location of all windows in the o.ide layer, and henceareas o!er which a particular diffusion step is effecti!e ach complete mas consists of a

    photographic plate on which each window is represented by an opa;ue are, the remainderbeing transparent ach complete mas will not only include all the windows for theproduction of one stage of a particular IC, but in addition, all similar areas for all suchcircuits on the entire silicon as shown in the figure below

    It will be ob!ious that a different mas is re;uired for each stage in the production of an arrayof IC*s on a wafer There is also a !ital re;uirement for precise registration between one masand the other in series, to ensure that there is no o!erlap between components, and that eachsection of a particular transistor is formed in precisely the correct location

    To mae a mas for one of the production stages, a master is first prepared which is an e.actreplica of that portion of the final mas associated with one indi!idual integrated circuit, butwhich is &-2. PsayR enlargement of the final si$e of IC The figure below shows a possiblemaster for the production of a mas to define a particular layer of diffusion for a hypotheticalcircuit Art wor at enlarge si$e a!oids large tolerance errors 7arge si$e also permits the artwor to be dealt easily by human operator In the design of the art wor, the locations of all

    components that is, resistor, capacitor, diode, transistor and so on, are determined on thesurface of the chip Therefore, si. or more layout drawings are re;uired ach drawing showsthe position of %indows that are re;uired for a particular step of the fabrication 3or comple.circuit the layout is generated by the use of computer9aided graphics

    1.9., >arious Printing Tec$niues

    'hotolithography comprises the formation of images with !isible or U 8 radiation in aphotoresist using contact pro.imity, or proBection printing >ere we will discuss about theseprinting techni;ues

    1. Contact Printing

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    In this printing techni;ue, the photomas is pressed against the resist coated wafer with apressure typically in the range of 22- atm to 2+ atm and e.posure by light of wa!elengthnear 22 micro meters A resolution of less than " micro meter linewidth is possible, but itmay !ary across the wafer because of spatial non9uniformity of the contact To pro!ide bettercontact o!er the whole wafer, a thin (2& mm) fle.ible mas has been used

    ". Pro6i'it! Printing

    Inpro.imity or shadow printing, there e.ists a gap between mas and wafer in the range of&2 to -2 micro meters This has the ad!antage of longer mas life because there is no contact

    between the mas and the wafer In the pro.imity printing, the mas and wafer are bothplaced in an e;uipment called a proBection aligner 7ooing through a microscope, anoperator brings the mas into close pro.imity Psay "2 to &2 micro metersR to the wafer and

    properly aligns the wafer and mas using alignment mar on the mas and the wafer U8light is then proBected through the mas on to the entire resist coated wafer at one time Thismas that is used is a full wafer . " mas The resolution of this process is a function of thewa!elength of the light source and the distance between the mas and the wafer Typically,the resolution of pro.imity printing is & to micro meter and is therefore not suitable for a

    process re;uiring less than a & um minimum line width

    ,. Proection Printing

    In this case the image is actually proBected with the help of a system of lenses, onto the waferThe mas can be used a large number of times, substantially reducing the mas cost perwafer Theoretically a mas can be used an unlimited9number of times, but actual usage islimited to about "22,222 times because the mas must be cleaned due to dust accumulation,and it is scratched at each cleaning This is costliest of the con!entional systems, howe!ermas life is good, and resolution obtained is higher than pro.imity printing together withlarge separation between mas and wafer

    Auto'ated *as eneration

    As discussed abo!e, layouts of electronic circuit are drawn on large mylar sheets They canalso be drawn on a CT screen by which layouts are stored digitally in a magnetic tape (ordis) In this case we need to prepare many layouts since each layout represents a pattern oneach mas to be used during fabrication 1ince the layouts are to be stored digitally, it isre;uired to con!ert the layouts drawn on mylar sheets into digital data This is performed by adigiti$er with the aid of a computer Then different portions of each layout are displayed on aCT one by one and inspected for further mistaes After all the corrections ha!e been made,

    a reticle, which is a small photographic plate of the layout image, is prepared from eachlayout stored on the magnetic tape

    0epending upon the type of e;uipment used, the mas to be fabricated contains one IC chippattern which is repeated as many times as there are on the wafer Alternati!ely, the masconsists of only magnified chip pattern as shown in the figure below

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    Automated #as generation

    The two most common approaches to automated mas maing or generation are

    Using optical proBection and

    Using electron beam

    A pattern generator ('=) tape is used as the Input to both approaches The '= tape, containsthe digiti$ed data necessary to control the light source or electron beam that is used to write a

    pattern on a photosensiti!e glass plate An A."2 pattern for a single chip (called a ."2 reticle)is first produced This reticle is then photo enlarged by a factor of "-, yielding . "-2

    blowbac, which is used for !isual checing A . " mas of the type shown in the figure isthen produced from the . "2 reticle by optical reduction and proBection onto a second

    photosensiti!e plate The same pattern is stepped and repeated on this plate as many as thereare chips on the wafer This step and repat operation is performed by photo repeater Theglass plate is then de!eloped yielding a . " mas which is called a master mas and loos liea tile floor where each rectangular tile has the same layout image of the chp 0uring the stepand repeat process the position and angle of the reticle are precisely aligned with the help oftwo fiducial mars incorporated in the '= files of all layouts in the same relati!e positionwith respect to the entire chip The master mas plate is then placed in close pro.imity to thewafer and optically proBected on to a resist9coated wafer during the lithographic process

    The figure below shows the second approach This employs electron9beam mas generatione;uipment winch generates the mas plate in one step The layout data are con!erted into ahit map of "*s and 2*s on a raster image The electron beam sweeps the row in a repeating 1

    pattern, blaning or unblaning the beam according to the input bit !alue, 2 or " In thefigure, the ."2 reticle is optically reduced and stepped directly onto the wafer This is referredto as direct9step on wafer (01%) lithography

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    Automated #as =eneration 'rocess

    The main ad!antage of electron9beam pattern generator is speed in the case of comple. chipsA large, dense chip can re;uire &2 hours or more of optical pattern generator time, but onlytwo hours or less of electron9beam pattern generator time

    1.: C$e'ical >apor Deposition (C>D)is the deposition of a solid material onto a heatedsubstrate through decomposition or chemical reaction of compounds contained m the gas

    passing o!er the substrate #any materials such as, silicon nitride, silicon dio.ide, non9crystalline silicon, and single crystal silicon, can be deposited through C80 method

    A special method in C80, called pita.y or pita.ial 7ayer 0eposition or 8apor9'hasepita.y (8'), has only a single9crystal form as the deposited layer This process is usuallycarried out for certain combinations of substrate and layer materials and under specialdeposition conditions

    In C80 process, a reaction chamber is introduced in which the materials to be deposited arepassed through These materials should be in the gaseous or !apor phase and react on or nearthe surface of the substrates, which are at some ele!ated temperature This produces achemical reaction and forms atoms or molecules that are to be deposited on entire substratesurface A number of different materials can be deposited by the C80 process These arelisted below4

    1ilicon epita.ial layer on a single9crystal silicon substrate (homoepita.y or commonlyreferred to as epita.y)

    1ilicon epita.ial layer deposition on a sapphire (>eteroepita.y)

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    1ilicon dio.ide deposition

    1ilicon nitride deposition

    ach one of these depositions will be described in this post

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    called homoepita.y >ere the epi9layer becomes a crystallographic continuation of thesubstrate

    The C80 of single9crystal silicon is usually performed in a reader consisting of a ;uart$reaction chamber into which a susceptor is placed The susceptor pro!ides physical supportfor the substrate wafers and pro!ides a more uniform thermal en!ironment 0eposition occursat a high temperature at which se!eral chemical reactions tae place when process gases flow

    into the chamber

    &Cl&R, trichlorosilane P1i>Cl+R and silaneP1i>R

    1ilicon tetrachloride has been the most studied and has seen the widest industrial use Theo!erall reaction can be classed as a hydrogen reduction of a gas

    +iCl0EgasF @ "/"EgasF 5 +i EsolidF @ 0/Cl EgasF

    3or understanding the abo!e reaction, we should determine for the 1i CI > system thee;uilibrium constant for each possible reaction and the partial pressure of each gaseousspecies at the temperature of interest ;uilibrium calculations re!eal fourteen species to bein e;uilibrium with solid silicon In practice many of the species can be ignored because their

    partial pressures are less than "29/atm

    Doping and Autodoping

    The considerations applied to epita.ial growth process are also applicable to doping Typicalhydrides of the impurity atoms are used as the source of dopant Typical reaction for arsenicdopant is as below

    &As>+(gas) H &AsPsolidR F +>& PgasR H &As (solid) H &AsFPsolidR F &e

    The hydride As>+does not decompose spontaneously as it is relati!ely stable because of thelarge !olume of hydrogen present in the reaction Interactions also tae place between thedoping process and the growth process In addition to intentional dopants incorporated intothe layer, unintentional dopants are introduced from the substrate This effect is termed

    autodoping Autodoping limits the minimum layer thicness that can be grown withcontrolled doping as well as the minimum doping le!el

    1.:." ori$ontal eactor

    8ertical eactor and

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    Cylindrical eactor

    The three reactors ha!e been e.plained in the figure below

    >ori$ontal reactors offer lowest cost construction, howe!er, controlling the depositionprocess o!er the entire susceptor length is a problem 8ertical reactors are capable of !eryuniform deposition but suffer from mechanical comple.ity Cylindrical reactors are alsocapable of uniform deposition due to employment of radiant heating, but arc not suited fore.tended operation at temperature abo!e "&22EC

    Epitaxial Growth Process

    A typical epita.ial growth process includes se!eral steps as follows

    h+drogen carrier gas is #sed to "#rge the reactor of air.

    The reactor is then heated to a tem"erat#re.

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    fter thermal e(#ili%ri#m is esta%lished in the cham%er anh+dro#s l gasis fed into the reactor. The l gas reacts 'ith the silicon at the s#rface of'afers in reaction that is re*erse of that gi*en for Sil42:.This re*ersereaction res#lts in *a"or-"hase-etching of the silicon s#rface and #s#all+occ#rs at a tem"erat#re %et'een 115! and 12!!& for 3 min.

    The tem"erat#re is then red#ced to the gro'th tem"erat#re 'ith timeallo'ed for sta%ili)ing the tem"erat#re and ;#shing the I gas. or SiI22: reaction the gra"hite %oat is heated to a tem"erat#re in the range115! < 125! degree elsi#s. The *a"or of Sil4and h+drogen as a carriergas arc introd#ced into the l#%e for "rod#cing e"itaial la+er.

    =nce gro'th is com"lete the do"ant and silicon ;o's are eliminated andthe tem"erat#re red#ced #s#all+ %+ sh#tting of the "o'er.

    s the reactor cools to'ard am%ient tem"erat#re the h+drogen ;o' isre"laced %+ a nitrogen ;o' so that the reactor ma+ %e o"ened safel+.

    0epending on wafer diameter and reactor type, capacities range from "2 to "- wafer per

    batch 'rocess cycle times are about " hour The !apor9phase etching (8') described abo!eis necessary to remo!e a small amount of 1i and other contaminants from the wafer surfacesto ensure that a clear freshly etched silicon surface will be a!ailable for epita.ial layerdeposition %hen the concentration of 1iCI, is high, etching can still occur e!en whenhydrogen chloride is not present due to a competing interaction

    +iC0@ +i 5 "+iCl"

    Thus, the growth rate of epita.ial silicon, which will be negati!e if etching occurs It is

    critically dependent on the concentration of silicon chloride as well as the temperature Intypical en!ironmental conditions for growth, at a rate of around " micro meter per min,produces layers which are well within the region for single9crystal epita.y

    %hen reduction of 1iC laes place, the reaction gi!es rise to free silicon atoms Atoms fromthe gas phase sid about on the surface of the growing epita.ial film until they find correct

    position in the lattice before becoming fastened into the growing structure

    3or producing doped p9type or n9type epita.ial layers, a number of gases can be metered intothe reactor tube, including some !ery small amounts of doping gases, such as &>/

    PdiboraneR for boron doping and '>+ PphosphineR for phosphorus doping of the epita.iallayer 0uring the epita.ial layer deposition the dopant gas molecules react and becomedecomposed and the dopant atoms thus produced become incorporated into the epita.iallayer 0oping of the epita.ial layer is also achie!ed by adding controlled amounts of9theappropriate impurity in li;uid form, for e.ample, phosphorus trichloride or arsenictrichloride, to the silicon chloride

    The main ad!antages and disad!antages of 1iCl as a source of 1i epita.y are as follows4

    Ad&antages

    Sil4is non-toic ine"ensi*e and eas+ to "#rif+.

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    The reaction ma$ing silicon from Sil4 ta$es "lace onl+ at s#rface and noton the %oat or reaction cham%er 'alls.

    Disad&antages

    The gro'th "rocess is accom"anied %+ the di>#sion "henomenon 'hichca#ses an echange of im"#rities %et'een silicon 'afer and gro'ing ilm.

    This "re*ents the fa%rication of an ideal ste" 0#nction.

    Sil4 "rocess re(#ires higher tem"erat#re than silane "rocess and alsohas slo'er gro'th rate.

    Problems in Growin Impurity Dope! Epitaxial "ayers

    pita.ial layer deposition taes place at temperatures in the range ?-2 to "&-2EC 0ue to this,diffusion of impurities may occur across the epita.ial layer or substrate interface due to thedeposition and high temperature processing steps This will cause a blurring of the impurity

    profile in the region of this interface ut the main problem will be the deposition of a !ery

    thin and !ery lightly doped epita.ial layer on a !ery hea!ily doped substrate The outdiffusionof impurities from the hea!ily doped substrate into the lightly doped epita.ial layer will blotout the sharp n6nFtransition that would otherwise be present at the layer9substrate interfaceThe influ. of donor atoms from the substrate will reduce the effecti!e thicness of the lightlydoped epita.ial layer by " or & micro meter To minimi$e this problem of outdiffusion fromhea!ily doped nFsubstrate, slow donor diffusants such as antimony and arsenic are often usedfor the doping of substrate in preference to phosphorus

    ?olec#lar eam @"ita+ A?@B

    #olecular beam epita.y differs from !apor9phase epita.y (8') in that it employse!aporation t Pinstead of depositionR method Thus it is a non9C80 epita.ial processAlthough the method has been nown since the early "?/2s, it has recently been considered asuitable technology for silicon de!ice fabrication In the # process the silicon along withdopants is e!aporated The e!aporated species are transported at a relati!ely high !elocity in a!acuum to the substrate

    The relati!ely low !apor pressure of silicon and the dopants ensures condensation on a low9temperature substrate Usually, silicon # is performed under ultra9high !acuum PU>8R

    conditions of "29

    to l29"/

    Torr

    The two maBor reasons why # was not used were in earlier years were that the ;uality wasnot commensurate with de!ice needs and that no industrial e;uipment e.isted ;uipmentsare now a!ailable, but the process has low throughput and is e.pensi!e #, howe!er, doesha!e a number of inherent ad!antages o!er C80 techni;ues4

    It is a low temperature process Thus outdiffusion and autodoping is minimi$ed

    It allows precise control of doping and permits complicated doping profiles in he generated,This is useful for discrete microwa!e de!ices

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    A linear !oltage 9capacitance relationship is desired for !aractor diodes used in 3#modulators 3or this linear doping profile is re;uired, which is easily obtained with #

    1.:.,C>D Reactors

    The most common deposition methods are

    At'osp$eric8pressure c$e'ical &apor deposition (APC>D)

    3o%8pressure c$e'ical &apor deposition (3PC>D) and

    Plas'a8en$anced c$e'ical &apor deposition (PD) or plas'a deposition

    In earlier years, dielectric and poly9silicon films ha!e been deposited at atmospheric pressurewith the use of different types of reactors ut the use of such At'osp$eric8PressureReactorsha!e caused problems lie low wafer throughput, and also re;uire e.cessi!e waferhandling during loading and unloading, and pro!ide uniformity in thicness As time passed

    by, they ha!e been replaced by low9pressure, hot9wall reactors 'lasma assisted depositions in

    hot9wall reactors or with parallel9plate geom