Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 1.1 EE4800 CMOS Digital IC Design & Analysis...
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![Page 1: Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 1.1 EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng.](https://reader035.fdocuments.net/reader035/viewer/2022062313/56649d365503460f94a0dc66/html5/thumbnails/1.jpg)
Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.11
EE4800 CMOS Digital IC Design & Analysis
Lecture 1 IntroductionZhuo Feng
![Page 2: Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 1.1 EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng.](https://reader035.fdocuments.net/reader035/viewer/2022062313/56649d365503460f94a0dc66/html5/thumbnails/2.jpg)
Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.22
■ Prof. Zhuo Feng► Office: EERC 513► Phone: 487-3116 ► Email: [email protected]
■ Class Website ► http://www.ece.mtu.edu/~zhuofeng/EE4800Fall2011.html► Check the class website for lecture materials, assignments
and announcements
■ Schedule► TR 12:35pm-13:50pm EERC 227► Office hours: TR 4:30pm – 5:30pm or by appointments
![Page 3: Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 1.1 EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng.](https://reader035.fdocuments.net/reader035/viewer/2022062313/56649d365503460f94a0dc66/html5/thumbnails/3.jpg)
Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.33
Topics (tentative)■ Introduction■ CMOS circuit and layout ■ MOS transistor device characteristics■ DC and transient responses, delay estimation■ Logical effort■ Power■ SPICE simulation■ Modified Nodal Analysis (MNA)■ Interconnect ■ Combinational circuits■ Sequential circuits■ Design for Testability■ Adders■ SRAM■ Packaging, power and clock distributions
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.44
Grading Policy■Homework: 40%■Quizzes 10%■Mid-term Exam: 20%■Final Exam: 30%■Late homework: 50% penalty/day.■Letter Grades:
►A: 85~100; AB: 80~84; B: 75~79; BC: 70~74; C: 65~69; D: 60~64; F: 0~59
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.55
Moore’s law in Microprocessors
40048008
80808085 8086
286386
486Pentium® proc
P6
0.001
0.01
0.1
1
10
100
1000
1970 1980 1990 2000 2010Year
Tra
nsis
tors
(M
T) 2X growth in 1.96 years!
Transistors on Lead Microprocessors double every 2 yearsTransistors on Lead Microprocessors double every 2 years
Courtesy, Intel
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.66
Die Size Growth
40048008
80808085
8086286
386486Pentium ® proc
P6
1
10
100
1970 1980 1990 2000 2010Year
Die
siz
e (
mm
)
~7% growth per year~2X growth in 10 years
Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law
Courtesy, Intel
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.77
Frequency
P6Pentium ® proc
48638628680868085
8080800840040.1
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Fre
qu
en
cy (
Mh
z)
Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years
Doubles every2 years
Courtesy, Intel
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.88
Power Dissipation
P6Pentium ®proc
486
3862868086
80858080
80084004
0.1
1
10
100
1971 1974 1978 1985 1992 2000Year
Pow
er
(Watt
s)
Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase
Courtesy, Intel
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.99
Why Scaling?
■ Technology shrinks by ~0.7 per generation■ With every generation can integrate 2x more
functions on a chip; chip cost does not increase significantly
■ Cost of a function decreases by 2x■ But …
► How to design chips with more and more functions?► Design engineering population does not double every two
years…
■ Hence, a need for more efficient design methods► Exploit different levels of abstraction
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.1010
Pentium 4■ Deep pipeline (2001)
► Very fast clock► 256-1024 KB L2$
■ Characteristics► 180 – 65 nm process► 42-125M transistors► 1.4-3.4 GHz► Up to 160 W► 32/64-bit word size► 478-pin PGA
■ Units start to becomeinvisible on this scale
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.1111
Pentium M■ Pentium III derivative
► Better power efficiency► 1-2 MB L2$
■ Characteristics► 130 – 90 nm process► 140M transistors► 0.9-2.3 GHz► 6-25 W► 32-bit word size► 478-pin PGA
■ Cache dominates chip area
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.1212
Core2 Duo■ Dual core (2006)
► 1-2 MB L2$ / core■ Characteristics
► 65-45 nm process► 291M transistors► 1.6-3+ GHz► 65 W► 32/64 bit word size► 775 pin LGA
■ Much better performance/power efficiency
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.1313
Core i7■ Quad core (& more)
► Pentium-style architecture► 2 MB L3$ / core
■ Characteristics► 45-32 nm process► 731M transistors► 2.66-3.33+ GHz► Up to 130 W► 32/64 bit word size► 1366-pin LGA► Multithreading
■ On-die memory controller
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.1414
Atom■ Low power CPU for netbooks
► Pentium-style architecture► 512KB+ L2$
■ Characteristics► 45-32 nm process► 47M transistors► 0.8-1.8+ GHz► 1.4-13 W► 32/64-bit word size► 441-pin FCBGA
■ Low voltage (0.7 – 1.1 V) operation► Excellent performance/power
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.1515
Design Abstraction Levels
n+n+S
GD
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.1616
Design Metrics■How to evaluate performance of a
digital circuit (gate, block, …)?►Cost►Reliability►Scalability►Speed (delay, operating frequency) ►Power dissipation►Energy to perform a function
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.1717
Cost of Integrated Circuits■ NRE (non-recurrent engineering) costs
►design time and effort, mask generation►one-time cost factor
■ Recurrent costs►silicon processing, packaging, test►proportional to volume►proportional to chip area
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.1818
Cost per Transistor
0.00000010.0000001
0.0000010.000001
0.000010.00001
0.00010.0001
0.0010.001
0.010.01
0.10.111
19821982 19851985 19881988 19911991 19941994 19971997 20002000 20032003 20062006 20092009 20122012
cost: cost: ¢-per-¢-per-transistortransistor
Fabrication capital cost per transistor (Moore’s law)
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.1919
Silicon Lattice■ Transistors are built on a silicon substrate■ Silicon is a Group IV material■ Forms crystal lattice with bonds to four
neighbors
Si SiSi
Si SiSi
Si SiSi
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.2020
Dopants■ Silicon is a semiconductor■ Pure silicon has no free carriers and conducts
poorly■ Adding dopants increases the conductivity■ Group V: extra electron (n-type)■ Group III: missing electron, called hole (p-type)
As SiSi
Si SiSi
Si SiSi
B SiSi
Si SiSi
Si SiSi
-
+
+
-
N-typeN-type P-typeP-type
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.2121
P-N Junctions■ A junction between p-type and n-type
semiconductor forms a diode.■ Current flows only in one direction
p-type n-type
anode cathode
Current flow directionCurrent flow direction
Electron flow directionElectron flow direction
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.2222
NMOS Transistor■ Four terminals: gate, source, drain, body■ Gate – oxide – body stack looks like a capacitor
► Gate and body are conductors
► SiO2 (oxide) is a very good insulator
► Called metal – oxide – semiconductor (MOS) capacitor► Even though gate is no longer made of metal
Substrate, body or bulkSubstrate, body or bulk
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+Body
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.2323
NMOS Operation■ Body is commonly tied to ground (0 V)■ When the gate is at a low voltage:
► P-type body is at low voltage► Source-body and drain-body diodes are OFF► No current flows, transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+D
0
S
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.2424
NMOS Operation Cont.■ When the gate is at a high voltage:
► Positive charge on gate of MOS capacitor► Negative charge attracted to body► Inverts a channel under gate to n-type► Now current can flow through n-type silicon from source
through channel to drain, transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+D
1
S
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.2525
PMOS Transistor■ Similar, but doping and voltages reversed
► Body tied to high voltage (VDD)
► Gate low: transistor ON► Gate high: transistor OFF► Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.2626
Power Supply Voltage■ GND = 0 V
■ In 1980’s, VDD = 5V
■ VDD has decreased in modern processes► High VDD would damage modern tiny transistors
► Lower VDD saves power
■ VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.2727
Transistors as Switches■ We can view MOS transistors as electrically
controlled switches■ Voltage at gate controls path from source to
drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF ON
ON OFF
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.2828
CMOS Inverter
A Y
0
1
VDD
A Y
GNDA Y
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.2929
CMOS Inverter
A Y
0
1 0
VDD
A=1 Y=0
GND
ON
OFF
A Y
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.3030
CMOS Inverter
A Y
0 1
1 0
VDD
A=0 Y=1
GND
OFF
ON
A Y
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.3131
CMOS NAND Gate
A B Y
0 0
0 1
1 0
1 1
A
B
Y
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.3232
CMOS NAND Gate
A B Y
0 0 1
0 1
1 0
1 1
A=0
B=0
Y=1
OFF
ON ON
OFF
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.3333
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0
1 1
A=0
B=1
Y=1
OFF
OFF ON
ON
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.3434
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0 1
1 1
A=1
B=0
Y=1
ON
ON OFF
OFF
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.3535
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
A=1
B=1
Y=0
ON
OFF OFF
ON
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.3636
CMOS NOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
A
BY
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.3737
3-input NAND Gate■ Y pulls low if ALL inputs are 1■ Y pulls high if ANY input is 0
A
B
Y
C
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.3838
CMOS Fabrication■ CMOS transistors are fabricated on silicon wafer
■ Lithography process similar to printing press
■ On each step, different materials are deposited or etched
■ Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.3939
Inverter Cross-section■ Typically use P-type substrate for NMOS
transistors■ Requires N-well for body of PMOS transistors
► Silicon dioxide (SiO2) prevents metal from shorting to other layers
inputinput
n+
p substrate
p+
n well
A
YGND VDD
n+ p+
SiO2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.4040
Well and Substrate Taps■ P-type substrate (body) must be tied to GND
■ N-well is tied to VDD
■ Use heavily doped well and substrate contacts ( taps)
► Establish a good ohmic contact providing low resistance for bidirectional current flow
n+
p substrate
p+
n well
A
YGND VDD
n+p+
substrate tapwell tap
n+ p+
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.4141
Inverter Mask Set■ Transistors and wires are defined by masks
► Inverter can be obtained using six masks: n-well, polysilicon, n+ diffusion, p+ diffusion, contacts and metal
■ Cross-section taken along dashed line
GND VDD
Y
A
substrate tap well tapnMOS transistor pMOS transistor
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.4242
■ Six masks► n-well
► Polysilicon
► N+ diffusion► P+ diffusion► Contact
► Metal
Detailed Mask Views
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.4343
Fabrication■ Chips are built in huge factories called fabs■ Contain clean rooms as large as football fields
Courtesy of InternationalBusiness Machines (IBM) Corporation. Unauthorized use not permitted.
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.4444
Fabrication Steps■ Start with blank wafer■ Build inverter from the bottom up■ First step will be to form the n-well
► Cover wafer with protective layer of SiO2 (oxide)
► Remove layer where n-well should be built► Implant or diffuse n dopants into exposed wafer
► Strip off SiO2
p substrate
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.4545
Oxidation■ Grow SiO2 on top of Si wafer
►900 – 1200 Celcius with H2O or O2 in oxidation furnace
p substrate
SiO2
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.4646
Photoresist■ Spin on photoresist
►Photoresist is a light-sensitive organic polymer►Softens where exposed to light
p substrate
SiO2
Photoresist
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.4747
■ Expose photoresist through n-well mask
■ Strip off exposed photoresist
Lithography
p substrate
SiO2
Photoresist
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.4848
Etch■ Etch oxide with hydrofluoric acid (HF)■ Only attacks oxide where resist has been
exposed
p substrate
SiO2
Photoresist
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.4949
Strip Photoresist■ Strip off remaining photoresist
►Use mixture of acids called piranha etch
■ Necessary so resist doesn’t melt in next step
p substrate
SiO2
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.5050
N-well■ N-well is formed with diffusion or ion
implantation■ Diffusion
► Place wafer in furnace with arsenic gas► Heat until As atoms diffuse into exposed Si
■ Ion Implantation► Blast wafer with beam of As ions
► Ions blocked by SiO2, only enter exposed Si
n well
SiO2
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.5151
Strip Oxide■ Strip off the remaining oxide using HF■ Back to bare wafer with n-well■ Subsequent steps involve similar series of
steps
p substraten well
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.5252
Polysilicon■ Deposit very thin layer of gate oxide (SiO2)
► < 20 Å (6-7 atomic layers)
■ Chemical Vapor Deposition (CVD) of silicon layer► Place wafer in furnace with Silane gas (SiH4)
► Forms many small crystals called polysilicon► Heavily doped to be good conductor
Thin gate oxidePolysilicon
p substraten well
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.5353
Polysilicon Patterning■ Use same lithography process to pattern
polysilicon
Polysilicon
p substrate
Thin gate oxidePolysilicon
n well
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.5454
Self-Aligned Process■ Use oxide and masking to expose where n+
dopants should be diffused or implanted■ N-diffusion forms NMOS source, drain, and n-
well contact
p substraten well
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.5555
N-diffusion■ Pattern oxide and form n+ regions■ Self-aligned process where gate blocks diffusion■ Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
p substraten well
n+ Diffusion
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.5656
N-diffusion cont.■ Historically dopants were diffused■ Usually ion implantation today■ But regions are still called diffusion
n wellp substrate
n+n+ n+
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.5757
N-diffusion cont.■ Strip off oxide to complete patterning step
n wellp substrate
n+n+ n+
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.5858
P-Diffusion■ Similar set of steps form p+ diffusion regions
for pMOS source and drain and substrate contact
p+ Diffusion
p substraten well
n+n+ n+p+p+p+
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.5959
Contacts■ Now we need to wire together the devices■ Cover chip with thick field oxide■ Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+n+ n+p+p+p+
Contact
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.6060
Metallization■ Sputter on aluminum over whole wafer■ Pattern to remove excess metal, leaving wires
p substrate
Metal
Thick field oxide
n well
n+n+ n+p+p+p+
Metal
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.6161
Layout■ Chips are specified with set of masks■ Minimum dimensions of masks determine
transistor size (and hence speed, cost, and power)
■ Feature size f = distance between source and drain
► Set by minimum width of polysilicon
■ Feature size improves 30% every 3 years or so
■ Normalize for feature size when describing design rules
■ Express rules in terms of = f/2► E.g. = 0.3 m in 0.6 m process
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Simplified Design Rules■ Conservative rules to get you started
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.6363
Inverter Layout■ Transistor dimensions specified as Width /
Length► Minimum size is 4 / 2sometimes called 1 unit► In f = 0.6 m process, this is 1.2 m wide, 0.6 m long
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Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisZ. Feng MTU EE4800 CMOS Digital IC Design & Analysis1.1.6464
Summary■ MOS Transistors are stack of gate, oxide, silicon■ Can be viewed as electrically controlled switches■ Build logic gates out of switches■ Draw masks to specify layout of transistors■ Now you know everything necessary to start
designing schematics and layout for a simple chip!