Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor:...

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Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013

Transcript of Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor:...

Page 1: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

Independent Internet Embedded System - Final A

Preformed by: Genady OkrainInstructor: Tsachi MartsianoDuration: Two semesters - 2013

Page 2: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

Agenda

• Introduction• System• FPGA• Test Environment• Results• Part B

Page 3: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

Introduction

• Project Goals• Part A Goals• Part B Goals

Page 4: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

Project Goals

• Independent system connected to the Internet.• Transferring data and control from and to a PC.• Store large amount of data transferred from a

PC on the DDR.• Notifying remote and locals statuses using the

LCD.• Light ON/OFF status LEDS using remote GUI.• Read control switches to the GUI.

Page 5: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

Part A Goals

• Transfer packets from the PC to the FPGA and back.• Ethernet Interface• DDR Interface

• UDP Packets Analyzers:• Ostinato Packet/Traffic Generator and

Analyzer.• Wireshark network protocol analyzer.

Page 6: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

Part B Goals

• Transfer files from the PC to the FPGA and back.• UDP Filters and UDP package builders.• Storing and fetching module.• GUI

• Control LEDS.• Control the LCD.• Read switches status.• UDP Filters and UDP package builders.• VHDL and Microblaze bridge.• Microblaze software.• GUI

Page 7: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

System

• System Overview• Xilinx XUPV5-LX110T• GUI

Page 8: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

System Overview

Packet

HELLO

Page 9: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

Xilinx XUPV5-LX110T

• Xilinx Virtex-5 XC5VLX110T FPGA• 64-bit wide 256Mbyte DDR2• 10/100/1000 tri-speed Ethernet PHY• 16x2 character LCD• LEDS• Switches

Page 10: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

GUI

• C# GUI• Send/Receive Files•Write on the LCD• Light LEDS• Read Switches

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Winter 2013

FPGA

• FPGA Dataflow • FPGA Interfaces (Part A&B)• FPGA Blocks (Part A&B)• Embedded Processor• MPMC• NPI PIM• Ethernet MAC• Dummy• Clocks & Throughput

Page 12: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

FPGA DataflowPacket

Page 13: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

FPGA Interfaces (Part A&B)

Page 14: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

FPGA Blocks (Part A&B)

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Winter 2013

Embedded Processor Interface

•MicroBlaze is the industry-leader in FPGA-based soft processors.•Memory Management Unit (MMU).• 32-bit RISC Harvard architecture soft

processor core.

Page 16: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

MPMC

• Double Data Rate (DDR/DDR2/DDR3/LPDDR) and Single Data Rate (SDR) SDRAM memory support.• Parameterized:• number of ports (1 to 8)• number of data bits to memory (4, 8, 16, 32, 64)• configuration of data path FIFOs.

Page 17: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

NPI PIM Features

• Extends the MPMC capabilities to meet design needs.• Simple interface to memory, can be easily

adapted to nearly any protocol.• Provides address, data, and control signals to

enable read and write requests for memory.• Simultaneous push and pull data from the port

FIFOs.

Page 18: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

NPI Interface State Machine

Page 19: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

Embedded Tri-Mode Ethernet MAC

• Fully integrated 10/100/1000 Mb/s Ethernet MAC.• Configurable full-duplex operation in

10/100/1000 Mb/s.• Media Independent Interface (MII), Gigabit

Media Independent Interface (GMII), and Reduced Gigabit Media Independent Interface (RGMII).

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Winter 2013

Dummy State Machine

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Winter 2013

Clocks & Throughput

• FPGA:• 125 Mhz•Microblaze:• 125 Mhz•DDR2@200 MHz 64 bits:• 1.6 Gbyte/sec• Ethernet:• 1 Gbit/sec

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Winter 2013

Test Environment

• Wireshark• ChipScope• SDK• Ostinato

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Winter 2013

Wireshark – Transmitting Packet

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Winter 2013

Chipscope – Writing DDR

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Winter 2013

SDK – Viewing DDR

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Winter 2013

Wireshark – Receiving Packet

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Winter 2013

Ostinato – Transmitting Burst

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Winter 2013

Wireshark – Receiving Burst

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Winter 2013

Results

• Took x3 planned time to implement .•MPMC, Ethernet MAC, Microblaze – All

tested.• Sending and receiving packets.•Writing and reading to/from DDR.• 1000 Packets burst with Ostinato.

Page 30: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

DEMO

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Winter 2013

Part B Missions• VHDL:• UDP Filtering by port for receive.• UDP Header generator for transmit.• Storage module for reading/writing files to DDR.

• Microblaze (SOC - C):• Read switches status.• Control LEDS.• Control LCD & LCD Driver.

• GUI (PC - C#):• Send and receive files.• Send control packages to the Microblaze (LEDS/LCD).• Receive status packages from the Microblaze (Switches).

Page 32: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

Timetable

•Today - 14/05/2013 - FPGA•15/05 - 28/05/2013 - GUI•29/05 - 11/06/2013 - Microblaze•12/06 - 30/06/2013 - Verification•07/2013 - Presentation

Page 33: Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters - 2013.

Winter 2013

Thank You!