Final Presentation

Performed by: Boris Goychman & Eyal Tsin

Instructor: Tsachi Martsiano

Adaptive Mirror Control System

Annual project, Winter 2012

Background

*Joint project with physics faculty, deals with an adaptive mirror

*The mirror:

*Changes Convexity in order to correct distortions of light originated in the atmosphere

*Now used for eye retina distortion corrections

Projects Goals

*Build a system that interfaces with a PC from one end and controls an adaptive mirror on the other.*Adaptive Mirror – contains 59 capacitors to control the shape of the mirror

*Learn an approach for practical engineering.

*Get familiar with FPGA, Logic Design and board design basics.

System Overview

PC

DE2 - FGPABOARD

DLP - USB

GUIDLP CHIP

ALTERA CHIP

D2A

HV S&H

HV S&H

Part APart B

Sample & Hold FPGA D2A DLP-USB

4.15us per channel 50Mhz 460ns per

channel 1MbpsData transfer rates

Up to 300V 3.3V 5V 3.3V Supply voltage

240mW 217mW 3mW 125uWPower consumption

D/AAdaptive Mirror

USBD/A

Sample & HoldFPGA

PCFPGA

Interfaces

ScopeDVM

1. Simulation - ModelSim

2. Emulation for each external

component

1. Emulation2. scope

1. Read from dat file (signal tap)

2. Write to FPGA FIFO

Test requirements

Specifications

System Rates (timing analysis)

2

From PC to DLP-USB :

59 8 2 944

9441.888

0.5PC DLP

bits

t SecM

2

From FPGA to D2A :

59 channels (8 bit each)

59 460 sec 27.14 secFPGA DACt n

2

From D2A TO Sample and Hold :

30 75 4 75

124.5 sec

FPGA HVwriting to both HVs at the same time

t n n

2

From DLP-USB to FPGA's internal FIFO :

944 (8 bit parallel transfer)

118 200 23.6DLP FPGAWrite Cycle

bits

t ns Sec

1888 23.6 27.14 124.5 2.02

2.02 20

one update cycleT ms

ms ms

0ms 20ms

2ms 18 marginms

Development alternatives*Microprocessor

*Philips provide software and drivers, easy to implement

*Need to buy one + external RAM

*Board design

*FPGA design

*Predesigned board

*Difficult to test and design with VHDL

*Choosing alternative USB control – ISP

*Difficult interface

*Higher rate (12Mbps)

Devised solutions

*VHDL implementation

*At least 4 FSM’s and some TBs

*FPGA implementation selected

*Due to availability

*DLP_USB_245

*Simple FIFO – works!

System usage & possible expansions

*Control a 59 capacitor adaptive mirror

*256 voltage values for each capacitor

*Same controller can be used to control any other system with the same requirements

*59 inputs or less

*256 values per input

*The output of the D2A will pass through

*a SAMPLE & HOLD (not in the scope of part A)

*and then to the mirror (not in the scope of part A)

Data flow

DLP’s FIFO FPGA’s FIFO MANAGER

FISRT8bit

LAST LAST8bit

FIRST

6 005 2

D2A

HV_A5 bit

control

8 bit control

HV_B

5 bit control

8bit8bit

8bit8bit

8bit8bit

6bit capacitor 8bit

voltage 00

6bit capacitor 8bit

voltage 00

ערכים 59

חבילת עדכון אחת של הקבלים במחשב

8bit

8bit

8bit8bit

8bit8bit

8bit

Packets Split

8 bit control

1*

6 005 21*

8bit

USB transfe

r

* בוחר את אחד יםHVה-

59*(6 8 2) 944bits

128 1024bytes bits 8192 262144words bits

MANAGER

DLP_Controller

_ _START POWER UP

_FINISH SU

_ _START POWER DOWN

_START SAMPLING

RESET

_ [4..0]A IN

_ [4..0]B IN

_FINISH SD

_FINISH SAMPLE

(SC)FIFO

D[7

..0]

wrre

q

rdreq

full

Q[7…0]

empty

FINISH

START

_ 2 _CLR DE DA

_ 2 _ [7..0]DATA DE DA

_ 2 _GAIN DE DA

_ 2 _ [1..0]ADDRESS DE DA

CS

WR

[7..0]DB

0, 1A A

GAIN

LDAC

CLR

_IN MUX

_VNN SWITCH

_EN MUX

_EN HV

_ [4..0]A OUT

_ 300RELAY

_VDD SWITCH

SWITCH- ADG202AKN

RELAY-AQY274

S&H-HV257

S&H-HV257

MUX-ADG784

_ [4..0]B OUT

D_inout[7..0]

DLP245-

USBD2A

sclr

RESET_PD NOT

Ext_S

TAR

T_K

EY

0

Ext_S

D_K

EY

1

Ext_R

ES

ET

_KE

Y2

RD

RXF

RESET

DATAOUT

OE

RESETD2A

Controller

General Block Diagram

HV257 Controlle

r

√Designed FSM’s and coded VHDL for:√D2A Controller

√DLP Controller

√FIFO

√HV Controller

√Manager

√Simulated and Emulated FSM’s for:√D2A Controller

√DLP Controller

√DLP Controller + FIFO

√DLP Controller + FIFO + Manager

√HV Controller

What we have done in Part A

√Tested FSM’s with:√D2A+DVM

√Emulation + Leds + 7 segment

√Signal Tap

What we have done in Part A

Design and test the analog electric circuits :D2A support circuitDLP (USB) support circuitHV support circuitMUX, RELAY and SWITCH support circuits300V, +15V and -15V power supplyIntegrate and test every-thing

What we will do in part B

Schedule

Questions