San José State UniversityCollege of Engineering/Electrical Engineering

EE174: Analog Peripheral for Embedded Systems

Section 01, Spring 2018

LAB6 Phase Locked Loop (PLL)

Goals:

The phase-locked loop, or PLL, is one of the most useful blocks in modern electronic circuits. It is used in many different applications, ranging from communications (FM modulation, demodulation, frequency synthesis, signal correlation), control systems (motor control, tracking controls, etc), as well as applications such as pulse recovery and frequency multiplication. The objective of this lab is to learn the basic concepts of operation of phase-locked loops (PLL). Experiments cover the measurement of the gain of a voltage-controlled oscillator and the construction of a PLL with a first-order filter. PLL properties such as capture range, hold range, are measured, and correlated with analysis results

Required Equipment:

1x CD4046, 1x 74160, 1x 0.1uF, 2x 1nF, 1x 120kΩ, 1x 150kΩ, 1x 240kΩ

Introduction:The basic PLL system is shown in Figure 1. The system consists of three parts: phase comparator, low-pass filter (LPF), and voltage-controlled oscillator (VCO). All parts are connected to form a closed-loop frequency-feedback system. Its purpose is to force the VCO to replicate and track the frequency and phase at the input when in lock. The PLL is a control system allowing one oscillator to track with another. It is possible to have a phase offset between input and output, but when locked, the frequencies must exactly track.

XOR Phase Comparator:Phase comparator I is an exclusive-OR network that operates analogously to an overdriven balanced mixer. To maximize the lock range, the signal- and comparator-input frequencies must have 50% duty cycle. With no signal or noise on the signal input, this phase comparator has an average output voltage equal to VDD/2. The LPF connected to the output of phase comparator I supplies the averaged voltage to the VCO input and causes the VCO to oscillate at the center frequency (fo). With phase comparator I, the range of frequencies over which the PLL can acquire lock (capture range) is dependent on the LPF characteristics and can be made as large as the lock range.Phase comparator I enables a PLL system to remain in lock despite high amounts of noise in the signal input.

Low-pass loop filter:A simple RC low-pass filter with a square wave input. Note that the second waveform has a higher duty cycle and therefore the filtered output is higher.

Fig 3: A Simple low-pass filter

Voltage-Controlled Oscillator (VCO) The VCO output frequency (Freq) is linearly related to the control voltage (V), i.e., Freq = Ko*V where Ko is a constant. If the phase of the VCO output square wave is considered as the output variable, the VCO can be modeled as an integrator i.e.

φo = Ko*V/s

Fig 4: Step Response of VCO and Phase Comparator

Pre-lab:1. Write a brief, one or two paragraph summary of the background about the PLL circuit, the

VCO, Phase Comparator, and the Low-Pass filter. The summary should be in your own words.

2. Determine the transfer functions for the RC networks F(s).

T a sks to be c o mpleted in l a b:

Fig 5: PLL circuit

1. Build the PLL circuit above with given component values.2. Apply no input, 0, 1, 2.5, 4 and 5V to pin 9 before connecting the low pass filterand

record the corresponding frequencies. Plot Vout versus frequency.

Apply voltage to Pin 9 (VCO input) FrequencyNo input

0V

1V

2.5V

4V

5V

fout

Vout

3. Apply a 50% duty cycle square-wave input Vin with frequency close to free-running frequency fo, the Vosc should lock with Vin . You may need to adjust the input frequency so the Vosc lock with Vin. Capture PLL when locked waveforms as shown below.

4. To obtain Lock Range:a. Adjust Vin to lower frequency until PLL become unlocked. Record frequency

starts to cause PLL to unlock and compare with fmin.b. Adjust Vin to higher frequency until PLL become unlocked. Record frequency

starts to cause PLL to unlock and compare with fmax.5. To obtain Capture Range:

a. From step 4a above, adjust Vin to higher frequency until PLL become locked. Record frequency starts to cause PLL to lock.

b. From step 4b above, adjust Vin to lower frequency until PLL become locked. Record frequency starts to cause PLL to lock.

6. Calculate the cut-off frequency of the low-pass filter and its transfer function.7. Calculate phase gain KD and VCO gain KO.8. Frequency synthesizer:

a. Connect PLL CD4046-pin3 to N74160-pin2.b. Connect N74160-pin14 to PLL CD4046-pin3.c. Adjust Vin to lower frequency until PLL become locked and capture waveforms

below

Conclusion:

References:Lecture Notes for formulas of transfer functions http://ecee.colorado.edu/~ecen4618/lab4.pdfhttp://www.futurlec.com/4000Series/CD4046.shtmlhttp://www.nxp.com/assets/documents/data/en/application-notes/AN535.pdfhttp://users.ece.gatech.edu/pallen/Academic/ECE_6440/Summer_2003/L090-PLLEqs & MeasA %282UP%29.pdf