Memory locations

0 – F We have a total of 16 locations00 - FF We have got another combination for this (2

digits) so we will have a total of 16*16 locations i.e 256 locations

000 – FFF With an addition of another digit we have another 16*256 combinations i.e 4096 locations which means 4KB

0000 – FFFF Now we can have 16*4096 or 16*4KB so we get 64KB locations

00000 – FFFFF Now wecan get up to 16 *64KB i.e 1MB locations

In this way with an increase of a single digit there will be an increase in 1 byte of memory.Eg : 00000 is a location and 00001 is an address location change in the last digit means increase of 1 byte of memory.

Eg : 00000 is a location and 0000F is an address location change in the last digit means increase of 16 bytes of memory.

Eg : 00000 is a location and 0000F is an address location change in the last digit means increase of 16 byte of memory.

Eg : 00000 is a location and 0001F is an address location change in the last digit means increase of 16+16 = 32 bytes of memory.

Eg : 00000 is a location and 0002F is an address location change in the last digit means increase of 16+16+16 = 48 bytes of memory.

Eg : 00000 is a location and 0003F is an address location change in the last digit means increase of 16+16+16+16 = 64 bytes of memory.

In that way finally we get 00000 to 000FF as 16*16 = 256 locations.Similarily ,

00000 to 000FF 256 Bytes00000 to 001FF 256 + 256 = 51200000 to 002FF 256+256+256 = 76800000 to 003FF 4*256 = 1024 bytes or 1 KB.00000 to 004FF 5*256= 1280 bytes in that way if we proceed00000 to 00FFF 16256 = 4096 bytes or 4 KBNow 00000 to 01FFF 2*4K 00000 to 02FFFF 3*4K00000 to 0FFFF 16*4K which is 64K00000 to 1FFFF 2*64 KSimilarily 00000 to FFFFF

16*64 = 1 MB

Unit III

Basic peripherals and their Interfacing

In this unit we will study only some concepts of

Interfacing memory (RAM & ROM) to 8086 processor. Interfacing 8255 I/O port IC.

Interfacings through 8255 to 8086.

Interfacing Memory to 8086 processor:

This topic will be like a problem to solve it. Questions will be asked in a way that the size of the memory will be given and the address locations for that will be given so that we need to interface (connect) them to 8086 processor through address and data lines and other pin configurations.

Problem 1.

Interface two 8K*8 EPROMS and two 4K*8 RAM chips with 8086. Select suitable maps.

Sol: We know that the processor will store the address of the memory segment in segments registers and offset address in various registers.

8086 is capable of addressing a memory space of 1 MB. The address locations will be starting from 00000 H to FFFFF H. First of all we need to consider the given memory size, here it is given as 4K*8 which means that the

size of the memory is 4KB and it supports 8 data lines. In this problem it is given to select suitable maps, which means that the address locations can be

selected by the user. Generally RAM will be located in the initial locations (00000 H) whereas ROM will be there at final

locations (FFFFF H). But here we need not follow that rule as it is given as suitable locations.

The process of mapping the address to the given memory size is known as address mapping. For memory interfacing the first step to be followed is memory mapping

1. Memory Mapping:

Table 5.1 page number 159

As shown in the figure we have taken the ROM address from last location so the last address location that 8086 can map is FFFFF H. we take the binary equivalent for that and equate each bit with the available address lines from A0 to A19. Now in the problem it is given that the size of the ROM is 4K so, starting from the last location FFFFF H decrease the locations to 4K.

FFFFF H to FF000 H the no of locations available here are 256 bytes. FFFFF H to FE000 Hthe no of locations available here are 16*256 i.e 4K

So we have taken the startion location as FE000 H and the end location as FFFFF H.

Similarily for RAM we take the location before FE000 H i.e FDFFF H as end location and starting is calculated as FC000 H( FDFFF H to FD000 256 locations and FC000 to FDFFF 16*256= 4K).

For now we consider only the memory size but not the data line length, it will be considered during the interfacing. Here the data line length is 8. The interfacing diagram can be as below. As we need only 12 address lines for mapping a 4 kb memory we take 12 address lines for memory selection(A1 to A12) and the remaining address lines (A13 to A19) will be used for chip selection. The remaining one address line A0 will be used for even and odd bank selection.

Page no 160 fig 5.1

Here we have used a decoder for chip selection logic. The chip selection logic can be done in any way by the user using any gate or any logic. But the criteria that has to be considered is we need to use the address lines which are remained after address mapping (most of the time these lines will be either 1 or 0 only).

Problem 2.

Page 161, 162

Sol: In this problem we have given a memory size of 16K so the address corresponding to these locations has to be calculated. But here it is asked in such a way that the RAM address starts at 00000H. so we need to start the memory location for RAM at 00000H only. The memory mapping table corresponding to the RAM address were given.

Similarily the ROM address can be calculated for 16K. These are connected to 8086 processor using address and data lines. Here the size of the data line is given as 8.

Practice similar problems in the similar way.

I/O ports 8255 Interfacing with 8086:

An input device is connected to the Microprocessor through an input port. An input port is a place for unloading data. An input device unloads data into the port. The Microprocessor reads data from the I/P port. Thus data are transferred from the input device to the accumulator via input port. Similarly, an output device is connected to the Microprocessor through an O/P port. The Microprocessor unloads data into an O/P port. As the O/P port is connected to the O/P device, data are transferred to the O/P device.

An I/O port may be programmable or non-programmable. A non programmable port behaves as an input port if it has been designed and connected in input mode. Similarly, a port connected in O/P mode acts as an output port. But in a programmable I/O port the port can be programmed to act either as an input port or an output port.

Intel 8212 is an 8-bit non-programmable I/O port. It can be connected to the Microprocessor either as an input port or an Output port. If we require one Input port and one Output port, two 8212 chips are required. On of them will be connected in Input mode and the other in the Output mode.

Input mode

pI/OPort

INPUT DEVICE

A BUS

OUTPUTDEVICE

D BUS

C BUS

VCC

INT

I/O Port8212

Data Input Data Output

CLR

Output flag

Data bus

Output mode

PROGRAMMABLE PERIPHERAL INTERFACEPPI

A PPI is a multi port device. The ports may be programmed in a verity of ways as required by the programmer.

Intel 8255 is a programmable peripheral interface. It has two versions, namely Intel 8255A and the Intel 8255A-5. General descriptions for both are same. It’s main functions are to interface peripheral equipment to the micro computer. It has 3, 8-bit ports, namely Port – A , Port – B and Port – C. the Port – C has been further divided in to two 4 bit ports. Port – Cupper and Port – Clower. Thus a total of 4 ports are available. Each port can be programmed as either an Input port or an Output port.

CLR

GND

8212

Data Input Data Output

Input strobe

Data busINT

RD

WR

RESET

CS

PB0 – PB7

PC0 – PC3

PC4 – PC7

PA0 – PA7D0 – D7

INTEL8255

A0

A1

VCC

GND

Schematic Diagram of Intel 8255A

8255 BLOCK DIAGRAM8255 is a 40 pin IC. It operates on 5 V d.c supply. The pins for various ports are as follows:

PA0 – PA7 8 pins of port APB0 – PB7 8 pins of port BPC0 – PC3 4 pins of port C lowerPC4 – PC7 4 pins of port C upper

D7 – D0

Data bus buffer

CS

I/O

PB7-PB0

RESET

A0

A1

WR

RD

Group B

Port BGroup B

Control

Read Write

Control Logic

I/O

PA7-PA0

I/O

PC7-PC4

I/O

PC3-PC0

GND

+5V

Bi- Directional Data Bus

Group A

Control

Group A

Port A

Group APort C upper

Group BPort C lower

8-Bit internal

Databus

CS (Chip Select) : The low status of this signal enables communication between the CPU and 8255.

RD (Read) : When RD goes low the 8255 sends out data or status information to the CPU on the data bus. In other words it allows the CPU to read data from the input port of 8255.

WR (Write) : When WR goes low the CPU writes data or control word into 8255. The CPU writes data into the O/P port of 8255.

A0 and A1 : The selection of Input port and control word register is done using A0 and A1 in conjunction with RD and WR. A0 and A1 are normally connected to the least significant bits of the address bus.

RESET : A high on this Input clears the control register and all ports (A, B, C) are set to the Input mode.

Group A and Group B controls:

The 24 lines of I/O ports are divided into two groups, namely Group A and Group B. Group A contains port A and port C upper. The group B contains port B and Port C lower. The function of each port is programmed as desired. CPU Outputs a control word to 8255. This control word initialises the ports. The control word contains information such as “mode”, “bit set”, “bit reset”, etc.,. Each of the control blocks (Group A and Group B) accept commands from the read/write control logic, receives control words from the internal data bus and issues the proper commands to its associated ports.

Operating modes of 8255: It has 3 modes of operation.

Mode 0 Simple Input /Output Mode 1 Strobed Input / OutputMode 2 Bi directional port.

8255 has two 8 bit ports and two 4 – bit ports. In mode 0 operation a port can be operated as a simple Input or Output port. Each of the four ports of 8255 can be programmed to be either Input or Output port.

Mode 1 is strobed Input/Output mode of operation. The port A and port B both are designed to operate in this mode of operation. When port A and port B are programmed in mode 1, six pins of port C are used for their control. PC0, PC1 and PC2

are used for the control of port B. PC3, PC4, PC5 are used to control port A when it is used as Input port. The remaining pins PC6 and PC7 can be used as either an Input or Output. When port A is operated as an Output port, pins PC3, PC6, PC7 are used for its control. The pins PC4 and PC5 can be used as either Input or Output.Mode 2: It is bi-directional mode of operation. In this mode only port A can be programmed to operate as a bi-directional port. PC3 to PC7 are used to control port A.

Control Word:

Bit 0 : It is for port Clower. To make it as an input port, the bit is set to 1. To make port

Clower an Output port the bit is set to 0.

Bit 1 : Port B1 Input port.

0 Output port.

Bit 2 : 0 To operate port B in mode 0 1 To operate port B in mode 1.

Bit 3 : 1 Port C upper Input port0 Output port

Bit 4 : 1 Port A Input port0 Output port.

Bit 5 & Bit 6 : Used to define operating mode of Port A. 6 5 Mode 0 0 0Mode 1 0 1Mode 2 1 0 or 1 For mode 2 bit number

5 is set either 0 or 1.

Bit 7 : It is set to 1 if ports A,B and C are defined as simple Input / Output ports. It is set to 0 if the individual pins of the port C are to be set or reset.

Example 1: Form the control word when the ports of Intel 8255 are defined as follows:Port A as Input portMode of the port A ------- mode 0Port B as an Output portMode of the port B --------mode 0Port Cupper as an Input port Port Clower as an Output port

7 6 5 4 3 2 1 0

1 0 0 1 1 0 0 0 98H

Mode A Port A PCU PB PB PCL

0 Input I/P Mode0 O/P O/P

Example 2. Form the control word for the following configuration of the ports of Intel 8255 for mode 0 operation:

Port A OutputPort B OutputPort Clower OutputPort Cupper Input

7 6 5 4 3 2 1 0

1 0 0 0 1 0 0 0 88H

Example 3. Make the control word for the following arrangement of the ports of Intel 8255 for mode 0 operation:

Port A OutputPort B OutputPort Clower OutputPort Cupper Output

7 6 5 4 3 2 1 0

1 0 0 0 0 0 0 0 80H

Example 4. Frame the control word for the following configuration of the ports of Intel 8255 for mode 0 operation:

Port A InputPort B InputPort Clower InputPort Cupper Input

7 6 5 4 3 2 1 0

1 0 0 1 1 0 1 1 9BH

Example 5. Make the control word for the following configuration of the ports of Intel 8255 for mode 1 operation:

Port A Input Mode 1Port B Output Mode 1Port Cupper Input

When Port A and Port B are operated in mode 1, Six pins of the port C are used for their contorl. PC0,PC1,PC2 are used for the control of the Port B which can be programmed to be either an input or output port.

If Port A is operated as an input port, PC3,PC4 and PC5 are used for its control. The pins PC6 and PC7 can be used as either input or output. When port A is programmed as an output port, pins PC3, PC6 and PC7 are used for its control. Pins PC4 and PC5 can be used as either input or output.

7 6 5 4 3 2 1 0

1 0 1 1 1 1 0 X BCHorBDH

Example 6. Frame the control word for the following configuration of the ports of Intel 8255 for mode 1 operation:

Port A Output Mode 1Port B Output Mode 1Remaining pins of Port C i.e. PC4 and PC5—Input.

For mode 1 operation PC0, PC1 and PC2 are used for the control of the Port B. When Port A is used as an output Port PC3, PC6 and PC7 are used for its control. PC4 and PC5 are available to be used either as input or output.

7 6 5 4 3 2 1 0

1 0 1 0 1 1 0 X ACH or ADH

1. Simple input output2. Simple strobe I/O3. Single hand shake I/O

4.Double hand shake I/O

1) SIMPLE INPUT OUTPUT : When you need to get digital data from a simple switch, such as a Thermostat, into a Microprocessor, all you have to do is connect the switch to an input port line and read the port. The Thermostat data is always present and ready. So you can read it at any time.

Like wise, when you need to output data to a simple display device such as an LED, all you have to do is connect the input of the LED buffer on an output port pin and output the logic level required to turn on the light. The LED is always here and ready, so you can send data to it at any time.

2) SIMPLE STROBE I/O: In many applications valid data is present on an external device only at a certain time, so it must be read in at that time.

For example, take a keyboard when a key is pressed, circuitry on the key board sends out the ASCII code for the pressed key on the parallel data times, and then sends out a strobe signal on another line to indicate that valid data is present on the present on the parallel data lines.

3) SINGLE HANDSHAKING I/O: The peripheral outputs some parallel data and sends on STB signal to the lep. The lep detects the asserted STB signal on a polled or interrupt basis and reads in the byte of data. Then the lep sends on acknwoledge signal (ack) to the peripheral to indicate that the data has been read and that the peripheral cansend the next byte of data. This operation is referred to as a handshake or strobed input.

4) DOUBLE HANDSHAKE DATA TRANSFER: For data transfers where even more coordination is required between the sending system and the receiving system, a double handshake is used.The sending device asserts its STB line low to ask,, "Are you ready?"

The receiving system reaises its ack line high to say "I am ready".

The peripheral device then sends the byte of data and raises its STB line high to say, "Here is some valid data for you"

After reading the data the receiving system drops the ack line low to say "I have the data thank you and I await your request to send the next byte of data".