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Performance of Switched-Capacitor Circuits Due to

Finite Gain Amplifiers

Course: ECE1352

Prepared by

Robert Wang

97143359

Prepared for

Professor K. Phang

Due Date: Nov 15th

, 2002

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Table of Contents

PERFORMANCE OF SWITCHED-CAPACITOR CIRCUITS DUE TO FINITE GAIN

AMPLIFIERS............................................................................................................................................... 1

TABLE OF CONTENTS............................................................................................................................. 2

LIST OF FIGURES...................................................................................................................................... 3

LIST OF EQUATIONS ............................................................................................................................... 3

1. INTRODUCTION............................................................................................................................... 4

2. BACKGROUND ON SC INTEGRATORS AND FINITE GAIN ERROR................................... 5

3. REDUCED SENSITIVITY SC CIRCUIT........................................................................................ 9

4. PRECISE GAIN OPERATIONAL AMPLIFIERS ....................................................................... 12

5. SIGMA-DELTA MODULATORS.................................................................................................. 15

5.1 OVERSAMPLING........................................................................................................................... 155.2 THE1-BITCONVERTER ................................................................................................................ 17

6. SUMMARY ....................................................................................................................................... 19

REFERENCE ............................................................................................................................................. 21

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List of Figures

FIGURE 1: COMPLEMENTARY INTEGRATORS ....................................................................... 5

FIGURE 2: SCCIRCUIT WITH REDUCED SENSITIVITY TO FINITE OPAMP GAIN .................... 9

FIGURE 3: ERRORCOMPARISON USING REDUCED FINITE GAIN SENSITIVITY SCCIRCUIT 11

FIGURE 4: FIRST ORDERCELL FORPOGANALYSIS.......................................................... 12FIGURE 5: FIRST ORDERSIGMA DELTA MODULATOR....................................................... 18

List of Equations

EQUATION 1: INVERTING INTEGRATORTRANSFERFUNCTION IN THE Z-DOMAIN ................ 5

EQUATION 2:NON-INVERTING INTEGRATORTRANSFERFUNCTION IN THE Z-DOMAIN ....... 6

EQUATION 3: RELATIONSHIP ............................................................................................... 6EQUATION 4: IDEAL TRANSFERFUNCTION OF THE INVERTING INTEGRATOR...................... 6

EQUATION 5: IDEAL TRANSFERFUNCTION OF THENON-INVERTING INTEGRATOR............. 6

EQUATION 6:ACTUAL TRANSFERFUNCTION....................................................................... 6EQUATION 7:APPROXIMATION TO ACTUAL TRANSFERFUNCTION ...................................... 7

EQUATION 8:ACTUAL TRANSFERFUNCTION DUE TO FINITE OPAMP GAIN.......................... 7

EQUATION 9: INTEGRATORMAGNITUDE ERROR................................................................. 7

EQUATION 10: INTEGRATORPHASE ERROR......................................................................... 7EQUATION 11: REDUCED SENSITIVITY CIRCUIT PHASE 1.................................................. 10

EQUATION 12: REDUCED SENSITIVITY CIRCUIT PHASE II ................................................. 10

EQUATION 13: IDEAL TRANSFERFUNCTION OF FIGURE 4 ................................................. 13EQUATION 14: ACTUAL TRANSFERFUNCTION OF FIGURE 4 USING FINITE GAIN............... 13

EQUATION 15: POGCAPACITORVALUES ......................................................................... 14

EQUATION 16: POGTRANSFERFUNCTION USING POGCAPACITORVALUES ................... 14

EQUATION 17: EFFECTIVE GAIN OF POG.......................................................................... 14EQUATION 18: FREQUENCY SPECTRUM OF SAMPLED SIGNAL ........................................... 16

EQUATION 19: SNR1 ........................................................................................................ 16EQUATION 20: SNR2 ........................................................................................................ 17

EQUATION 21: FIRST ORDERDIFFERENCE EQUATION OF SIGMA-DELTA MODULATOR.... 18

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1. IntroductionOne of the distinct advantages of switched-capacitor (SC) circuits is that they are

compatible with existing CMOS technology. Hence, they are among the most popular

analog building blocks. However, the standard design methodology assumes the use of

infinite gain and infinite bandwidth operational amplifiers. The gain limitation of

operational amplifiers introduces finite gain error. Section 2 of this paper discusses the

background of switched-capacitor circuit and derives the relative magnitude of the finite

gain error. After Section 2, three current design methods are introduced in an attempt to

minimizing the finite gain error. Finally in the summary section, we conclude with the

advantages and disadvantages of each method.

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2. Background on SC Integrators and Finite Gain ErrorFigure 1 below shows the inverting parasitic insensitive integrator and the non

inverting parasitic insensitive integrator. Both are very popular analog building blocks

for a variety of analog and mixed signal applications.

Figure 1: Complementary Integrators

Please note that the following analysis is largely the result of [1] and [2]. Using

discrete analysis of difference equations, the transfer function of the above integrators

can be found in Equation 1 and Equation 2 [4]:

1)(

2

1

=

z

z

C

CzH

Equation 1: Inverting Integrator Transfer Function in the Z-domain

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1

1)(

2

1

=

zC

CzH

Equation 2: Non-inverting Integrator Transfer Function in the Z-domain

Using the relationship presented in Equation 3 below, Equation 4 and Equation 5

can be derived from Equation 1 and Equation 2 by simple substitution.

)2

sin()2

cos(

),2

sin()2

cos(

),sin()cos(

2/1

2/1

Tj

Tz

Tj

Tz

TjTez Tj

=

+=

+==

Equation 3: Relationship

)2

sin(2

)(

)2/(

2

1

Tj

eC

C

H

Tj

i

=

Equation 4: Ideal Transfer Function of the Inverting Integrator

)2

sin(2

)(

)2/(

2

1

Tj

eC

C

H

Tj

i

=

Equation 5: Ideal Transfer Function of the Non-Inverting Integrator

However, the practical operational amplifier has limited gain. Taking into

account of the finite gain, the actual transfer function of the integrators can be expressed

in the form shown in Equation 6:

[ ] )()(1)(

)(

j

ia

em

HH

=

Equation 6: Actual Transfer Function

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In Equation 6, )(m is the magnitude error and )( is the phase error. For

small errors where 1)(),(

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proportional to the open loop gain oA . In a practical circuit, the inverting terminal is not a

perfect virtual ground. This causes error during charge transfer. The result is magnitude

and phase error of the integrator transfer functions. In the following sections, we look at

circuit design techniques that minimize the finite gain error.

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3. Reduced Sensitivity SC CircuitAs seen in Section 2, due to the use of finite gain operational amplifier, error is

introduced during charge transferring. To minimize this error, a circuit design technique

is proposed in [3] to reduce the finite gain error by reducing the circuit sensitivity to the

opamp finite gain. By performing a preliminary operation using additional capacitors

that match the main switching capacitors, a very close approximation of the finite gain

error is obtained. This error is then stored and used during the final operation. This

circuit is shown in Figure 2 [6].

Figure 2: SC Circuit with Reduced Sensitivity to Finite Opamp Gain [6]

In Figure 2, C1 and C2 are the original capacitor in the inverting integrator

configuration. C3 and C4 are additional auxiliary capacitors chosen such that the ratio of

C3/C4 is the same as the ratio of C1/C2. An additional capacitor CI, is used and its value

is not critical.

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The operation of the circuit is as follows. Assuming the input is held constant.

During phase 1, capacitor C1 and C2 are discharged. Depending on the ratio of C3/C4, a

preliminary amplification/attenuation is performed using capacitors C3 and C4. Note that

capacitor CI is connected to ground and the imperfect virtual ground. Due to the finite

gain opamp, this operation contains finite gain error giving rise to a non-zero voltage at

the inverting input of the opamp. Shown in Equation 11 is the relationship between the

output voltage V5 and the input voltage at the inverting terminal V2. The superscript 1

denote that this relationship holds for phase 1 of the operation.

A

VV

1

51

2 =

Equation 11: Reduced Sensitivity Circuit Phase 1

During phase 2, amplification/attenuation is performed using capacitors C1 and

C2. Capacitors C3 and C4 are discharged. The new voltage at Node 1 in Figure 2 is the

new value of V2 subtracting the old value of V2 stored in CI as shown in Equation 12.

Hence, finite gain error is much reduced.

1

2

2

21 VVV =

Equation 12: Reduced Sensitivity Circuit Phase II

Using more in depth analysis, it is shown that the value of CI is not critical as

long as it is much larger than the parasitic capacitance at Node 1. And using this

technique, it is shown that the finite error is reduced to about2

1

oAvs.

oA

1as discussed in

Section 1. Figure 3 below illustrates the effectiveness of this technique comparing to the

standard circuit.

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In Figure 3, the amplitude error is in percentage log scale. Curve 1 shows the

standard integrator circuit without any finite gain error reduction as discussed in Section

2. Curve 2 and curve 3 shows the amplitude error of other techniques used [3]. And

Curve 4 shows the amplitude error of the circuit shown in Figure 2. From Figure 3, we

see that this technique performs much better at the expense of additional auxiliary

capacitors. In terms of circuit design, more than double the capacitor area is required to

achieve a much smaller finite gain error.

Figure 3: Error Comparison using Reduced Finite Gain Sensitivity SC Circuit [6]

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4. Precise Gain Operational AmplifiersThe concept of a SC circuit with reduced sensitivity to amplifier gain minimizes

error such that it can be used in very precise analog-to-digital design blocks. However, it

uses more than twice the capacitor area which is undesirable since capacitors consume

very large silicon area in a chip. One alternative approach is to use a precise opamp gain

(POG) approach [5]. As the name suggests, the gain oA must be precisely known and it

is used as a design parameter. By using this approach, the effective gain of the amplifier

is /oA where epsilon is the maximum relative gain deviation. The resulting accuracy is

the same response accuracy of a standard circuit with an effective gain /oA of the

amplifier. Also, by reducing the gain of the amplifier, bandwidth of the amplifier can be

increased. Hence, POG designs are often used in higher frequency SC circuits. Lets

take a look at the analysis of the first order cell presented in Figure 4.

Figure 4: First Order Cell for POG Analysis [5]

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Please note that the following analysis is largely the result of [5], and only the

important steps are listed. Using standard analysis technique, assuming infinite opamp

gain, the ideal transfer function is given in Equation 13.

( ) 12321

_ )( +=

zCCC

CzH id

Equation 13: Ideal Transfer Function of Figure 4

Now, if the opamp gain is finite, the actual transfer function is given in Equation

14. We observe that as open loop gain tends to infinity, Equation 14 is reduced to

Equation 13. To obtain the same transfer function as the ideal transfer function, POG

capacitor values are obtained from the standard values as shown in Equation 15. Hence,

the transfer function of the POG has the same form as the actual transfer function shown

in Equation 16. It is important to note that although Equation 14 and Equation 16 share

the same form, Equation 14 is the transfer function of Figure 4 taking into account the

finite gain of the amplifier. Equation 16 is the transfer function with adjusted capacitance

values according to the finite gain of amplifiers. Also, although the notation oA is used

for the open loop gain, the actual opamp gain is ( )1oA , where epsilon is the gain

deviation and its magnitude is much smaller than 1.

1

2321

32

1

_1

1)(

+

++++

=z

AC

A

CCCCC

C

zH

oo

act

Equation 14: Actual Transfer Function of Figure 4 using Finite Gain

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ooPOG

o

POG

POG

A

C

ACC

ACC

CC

11

133

1122

11

+

+=

+=

=

Equation 15: POG Capacitor Values

( ) ( )1

2321

32

1

1

11

1

)(

++

+

++++

=

zA

CA

CCCCC

CzH

o

POG

o

POGPOGPOGPOGPOG

POGPOG

Equation 16: POG Transfer Function using POG Capacitor Values

From Equation 14 and Equation 16, the relative pole deviation can be compared

using capacitor values defined in Equation 15. The result show that using the POG with

an actual gain of ( )1oA gives the same pole error as with the standard approach with

an actual gain of

( )( )

oo

eff

AAA

++=

11

Equation 17: Effective Gain of POG

For example, using the POG approach with a gain deviation 1.0= and an actual

opamp gain 100=oA , the performance is the same with the standard approach as if the

opamp gain is 1000. Recall that in section 2, the finite gain error is inversely

proportional to the opamp gain. Hence in this case using the POG approach, the finite

gain error is reduced by 1 order of magnitude. The more accurate or the smaller the gain

deviation, the larger the effective gain of the opamp.

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5. Sigma-Delta ModulatorsThe two circuit design technique presented in Section 3 and Section 4 are useful

in terms of building accurate analog building blocks. However, the draw back is still

exists. For the circuit with reduced sensitivity to finite opamp gain, large silicon area is

wasted to reduce finite gain error. For the POG circuit, additional design overhead is

necessary to compute the precise gain value and use it as a design parameter in the

capacitors. In this section, a system design topology is introduced that uses the concept

of feedback to minimize this error.

The concept of sigma-delta modulators have existed since the middle of this

century. It has gained increase popularity in the recent decade mainly due to the

advancement in VLSI technology and digital signal processing. Using the current

advance in VLSI technology, very high resolution ADC can be achieved using a 1-bit

sigma-delta modulator for low and medium signal bandwidth. One of the key building

blocks of the Sigma-Delta converter is the switched-capacitor integrator. The system

architecture of the sigma-delta converter is discussed here to illustrate that this topology

is not only tolerant to circuit non-idealities and component mismatch, but also suppress

quantization noise using the technique of oversampling and feedback [4] [7] [8].

5.1 OversamplingThe analog-to-digital conversion involves two steps: sampling in time and

quantization in amplitude. Assuming ( )txs is the time domain analog signal, its

frequency spectrum is presented in Equation 18. We see that in the frequency domain,

the signal spectrum is repeated sf apart. Hence, to avoid aliasing, one must sample the

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analog signal at equal or greater than twice the highest frequency component of ( )fXs to

avoid aliasing. This is known as the Nyquist rate sampling criteria.

( )

=

=k

s

s

s kffXT

fX 1)(

Equation 18: Frequency Spectrum of Sampled Signal

Using the standard quantization noise model, that is, assuming the quantization

noise is of a stationary random process and it is uncorrelated with the input signal, the

signal-to-noise ratio can be derived and obtained in Equation 19. We see that for every

extra bit of resolution increase, there is an equivalent increase of 6.02 dB in the SNR.

However, increasing resolution is very difficult for Nyquist rate converters [7]. For

example, if one wishes to build a 16bit converter, the circuit needs to resolve a 98 dB

dynamic range. However, circuit non-ideality and component mismatch are too great,

making this converter impractical for general Nyquist rate converters.

[ ] 76.102.6 += NdBSNR Equation 19: SNR1

Instead of sampling at the Nyquist rate, by increasing the sampling frequency,

greater SNR can be achieved without using higher resolution converters. By increasing

the sampling frequency, the repeated input signal spectrum is also separated. This

reduces the design requirement for the anti-aliasing filter before the A/D conversion. The

trade off is speed vs. bandwidth. Assuming the fastest sampling frequency is fixed for a

given technology, increasing the sampling frequency effectively translates into reduced

allowed signal bandwidth. Equation 20 shows the SNR and sampling frequency

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relationship. It is observed that for every doubling of OSR, there is a 3.01 dB increase in

SNR.

[ ] ( )

o

s

f

fOSR

whereOSRNdBSNR

2

,log1076.102.6

=

++=

Equation 20: SNR2

5.2 The 1-bit ConverterWith the oversampling discussed, we now turn to the sigma-delta converter. A

first order sigma-delta modulator is presented in Figure 5. In this figure, the integrator

samples the analog signal, and the quantizer is modeled as an error component that is

introduced into the system. Once the signal is sampled and quantized, it is passed into

the digital domain. The key to the first order sigma-delta modulator is the feedback

introduced that converts the digital signal y[n] back into the analog domain. This

feedback forces y[n] to be very accurate. Although in this model, only the quantization

noise is modeled. I believe that the non-ideality of the circuit can also be modeled as

error inputs into the system. Hence, even though circuit non-ideality and component

mismatch exist, solving this system gives the modulator output shown in Equation 21.

The output is essentially the first order difference of the error. This concept can be

extended to higher order sigma delta systems, but the point remains the same: the

feedback in the sigma delta modulator allows the modulator output, even though only at

one bit, be very accurate provided that the sampling frequency is much higher than the

incoming analog signal bandwidth.

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Figure 5: First Order Sigma Delta Modulator

[ ] [ ] [ ] [ ]11 += nenenxny

Equation 21: First Order Difference Equation of Sigma-Delta Modulator

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6. SummaryFinite gain of operational amplifier causes finite gain error of switched-capacitor

circuit, degrading its performance. In this paper, circuit design techniques were

discussed to improve the performance of switched-capacitor circuit by minimizing the

finite gain error. In section 3, it is observed that using a circuit with reduced sensitivity

to the finite gain amplifier reduces finite gain error fromoA

1to

2

1

oA. This technique uses

extra capacitors hence increasing circuit area. Also, the assumption of input being held

constant is used during the circuit analysis. If the input frequency is comparable to the

switching frequency, the finite gain error might not be reduced as much. Hence, this

circuit is good for low frequency applications. In section 4, the POG circuit uses the

precise gain parameter of an amplifier as a design parameter in deriving capacitor values.

This reduces the finite gain error by a factor of

1, where epsilon is typically much less

than 1. The POG approach is great for large bandwidth switched-capacitor circuit. Using

a reduced gain, the bandwidth of the circuit can be increased without the penalty of

increasing finite gain error by making the precise gain very accurate. However, extra

design overhead is required. The POG approach is good for circuit that requires large

bandwidth. It typically finds its application in high frequency SC circuits. In Section 5,

the use of sigma-delta modulator uses feedback to minimize the output error, including

the finite gain error. Using the oversampling technique, the 1-bit sigma-delta modulator

can be made very accurate, but at the expense of bandwidth. Hence, it is only applicable

to low and medium frequency signals.

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In this paper, only the finite gain error of SC circuits is discussed. SC circuits

suffer from another drawback which is due to the finite bandwidth of amplifiers. Often, a

design has to trade off gain for bandwidth. As circuit designers become more

experienced in dealing with practical circuit limitation and imperfections, better circuits

are designed that minimizes these imperfections and pushes technology to its limit.

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Reference

[1] G. C. Temes, Finite amplifier gain and bandwidth effects in switched

capacitor filters, IEEE J. Solid-Stage Circuits, vol. SC-15, pp. 358-361, June

1980

[2] K. Martin and A. S. Sendra, Effects of opamp finite gain and bandwidth on

the performance of switched-capacitor filters, IEEE Trans. Circuits Systems,vol. CAS-28, pp. 822-829, Aug. 1981

[3] K. Nagaraj, K. Singhal, T. R. Viswanathan, and J. Vlach, Reduction of thefinite gain effect in switched-capacitor filters, Electron. Lettt., vol 21, pp.

644-645, July 1985.

[4] Johns and Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc.,

New York, pp 403.

[5] A. Baschirotto, Considerations for the design of switched-capacitor circuits

using precise-gain operational amplifiers, IEEE Trans. Circuits Syst.II, vol.43, pp. 827-832, Dec. 1996

[6] K. Nagaraj, T. R. Viswanathan, K. Singhal, and J. Vlach, Switched-Capacitor

Circuits with reduced Sensitivity to Amplifier Gain, IEEE Transactions on

Circuits and Systems, VOL. CAS-34, No 5, May 1987.

[7] P.M. Aziz, H.V. Sorensen, and J.V.D. Spiegel, An Overview of Sigma-DeltaConverters, IEEE Signal Processing Magazine, pp 61-84, January 1996.

[8] B.E. Boser, B.A. Wooley, The Design of Sigma-Delta Modulation Analog-to-Digital Converters, IEEE Journal of Solid State Circuits, vol. 23, NO 6, pp

1298-1308, December 1988