VLSI Testing - DFT and Scan

8/12/2019 VLSI Testing - DFT and Scan

1/35

Copyright 2001, Agrawal & BushnellCopyright 2001, Agrawal & Bushnell

VLSI Testing

DFT and Scan

VLSI Testing

DFT and Scan

Definitions

Ad-hoc methods

Full Scan design Partial scan

Boundary scan

Summary


2/35

Copyright 2001, Agrawal & Bushnell DFT and Scan 2Copyright 2001, Agrawal & Bushnell 2

DefinitionsDefinitions

Design for testabil ity (DFT) refers to those design

techniques that make test generation and testapplication cost-effective.

DFT methods for digital circuits:

Ad-hoc methods

Structured methods: Scan

Partial Scan

Built-in self-test (BIST)

Boundary scan

DFT method for mixed-signal circuits: Analog test bus


3/35


Ad-Hoc DFT MethodsAd-Hoc DFT Methods Good design practices learnt through experience are used as

guidelines:

Avoid asynchronous (unclocked) feedback.

Make flip-flops initializable.

Avoid redundant gates. Avoid large fanin gates.

Provide test control for dif ficult-to-control signals.

Avoid gated clocks. Consider ATE requirements (tristates, etc.)

Design reviews conducted by experts or design auditing tools.

Disadvantages of ad-hoc DFT methods:

Experts and tools not always available. Test generation is often manual with no guarantee of high fault

coverage.

Design iterations may be necessary.


4/35

Copyright 2001, Agrawal & Bushnell DFT and Scan 4

Difficulties in Seq. ATPGDifficulties in Seq. ATPG

Poor initializability.

Poor controllability/observability of state variables. Gate count, number of flip-flops, and sequential depth

do not explain the problem.

Cycles are mainly responsible for complexity.

An ATPG experiment:

Circuit Number of Number of Sequential ATPG Fault

gates flip-flops depth CPU s coverage

TLC 355 21 14* 1,247 89.01%

Chip A 1,112 39 14 269 98.80%

* Maximum number of flip-flops on a PI to PO path


5/35


Scan DesignScan Design Circuit is designed using pre-specified design rules.

Test structure (hardware) is added to the verifieddesign:

Add a test control (TC) primary input.

Replace flip-flops by scan flip-flops (SFF) and connect to form

one or more shift registers in the test mode. Make input/output of each scan shift register

controllable/observable from PI/PO.

Use combinational ATPG to obtain tests for all testable

faults in the combinational logic. Add shift register tests and convert ATPG tests into

scan sequences for use in manufacturing test.


6/35


Scan Design RulesScan Design Rules

Use only clocked D-type of flip-flops for all state

variables.

At least one PI pin must be available for test; more

pins, if available, can be used. All clocks must be controlled from PIs.

Clocks must not feed data inputs of flip-flops.


7/35


Correcting a Rule ViolationCorrecting a Rule Violation All clocks must be controlled from PIs.

Comb.

logic

Comb.

logic

D1

D2

CK

Q

FF

Comb.

logic

D1

D2

CK

Q

FF

Comb.

logic


8/35


Scan Flip-Flop (SFF)Scan Flip-Flop (SFF)D

TC

SD

CK

Q

QMUX

D flip-flop

Master latch Slave latch

CK

TC Normal mode, D selected Scan mode, SD selected

Master open Slave open

t

t

Logicoverhead


9/35


Level-Sensitive Scan-Design

Flip-Flop (LSSD-SFF)

Level-Sensitive Scan-Design

Flip-Flop (LSSD-SFF)

D

SD

MCK

Q

Q

D flip-flop

Master latch Slave latch

t

SCK

TCK

SCK

MCK

TCK

N

ormal

mode

MCK

TCK Scan

mode

Logic

overhead


10/35


Adding Scan StructureAdding Scan Structure

SFF

SFF

SFF

Combinational

logic

PI PO

SCANOUT

SCANIN

TC or TCK Not shown: CK orMCK/SCK feed all

SFFs.


11/35


Comb. Test VectorsComb. Test Vectors

I2I1 O1 O2

S2S1 N2N1

Combinational

logic

PI

Present

state

PO

Next

state

SCANINTC

SCANOUT


12/35


Comb. Test VectorsComb. Test Vectors

I2I1

O1 O2

PI

PO

SCANIN

SCANOUT

S1 S2

N1 N2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0TC

Dont care

or random

bits

Sequence length= (ncomb + 1) nsff+ ncomb clock periods

ncomb = number of combinational vectors

nsff= number of scan flip-flops


13/35


Testing Scan RegisterTesting Scan Register Scan register must be tested prior to application

of scan test sequences. A shift sequence 00110011 . . . of length nsff+ 4 in

scan mode (TC = 0) produces 00, 01, 11 and 10

transitions in all fl ip-flops and observes the result

at SCANOUT output. Total scan test length:

(ncomb + 2) nsff+ ncomb + 4 clock periods.

Example: 2,000 scan flip-flops, 500 comb. vectors,total scan test length ~ 106 clocks.

Multiple scan registers reduce test length.


14/35


Multiple Scan RegistersMultiple Scan Registers Scan flip-flops can be distributed among

any number of shift registers, each having

a separate scaninand scanoutpin. Test sequence length is determined by the

longest scan shift register.

Just one test control(TC) pin is essential.

SFFSFF

SFF

Combinational

logic

PI/SCANIN PO/

SCANOUTMU

X

CK

TC


15/35


Scan OverheadsScan Overheads IO pins: One pin necessary.

Area overhead:

Gate overhead = [4 nsff/(ng+10nff)] x 100%where ng = comb. gates; nff = flip-flopsExample ng = 100k gates, nff= 2k flip-flopsoverhead = 6.7%.

More accurate estimate must consider scan wiringand layout area.

Performance overhead:

Multiplexer delay added in combinational path;approx. two gate-delays.

Flip-flop output loading due to one additionalfanout; approx. 5 - 6%.


16/35


Hierarchical ScanHierarchical Scan Scan flip-flops are chained within

subnetworks before chaining subnetworks.

Advantages: Automatic scan insertion in netlist

Circuit hierarchy preserved helps in

debugging and design changes

Disadvantage: Non-optimum chip layout.

SFF1

SFF2 SFF3

SFF4SFF3SFF1

SFF2SFF4

Scanin Scanout

Scanin

Scanout

Hierarchical netlist Flat layout


17/35


Optimum Scan LayoutOptimum Scan Layout

IO

pad

Flip-

flop

cell

Interconnects

Routing

channels

SFF

cell

TC

SCANIN

SCAN

OUT

Y

XX

Y

Active areas: XY and XY


18/35


Scan Area OverheadScan Area OverheadLinear dimensions of active area:

X = (C + S) / r

X = (C + S + S) / r

Y = Y + ry = Y + Y(1--) / TArea overhead

XY--XY

= -------------- x 100%XY

1--= [(1+s)(1+ -------) 1] x 100%

T

1--= (s + ------- ) x 100%

T

y = track dimension, wire

width+separationC = total comb. cell width

S = total non-scan FF cell

width

s = fractional FF cell area

= S/(C+S) = SFF cell width fractionalincrease

r = number of cell rows

or routing channels = routing fraction in activearea

T = cell height in track

dimension y


19/35


Example: Scan LayoutExample: Scan Layout 2,000-gate CMOS chip

Fractional area under flip-flop cells, s = 0.478

Scan flip-flop (SFF) cell width increase, = 0.25 Routing area fraction, = 0.471 Cell height in routing tracks, T = 10

Calculated overhead = 17.24%

Actual measured data:

Scan implementation Area overhead Normalized clock rate

______________________________________________________________________

None 0.0 1.00

Hierarchical 16.93% 0.87

Optimum layout 11.90% 0.91


20/35


ATPG Example: S5378ATPG Example: S5378

Original

2,781

179

0

0.0%

4,603

35/49

70.0%

70.9%

5,533 s

414

414

Full-scan

2,781

0

179

15.66%

4,603

214/228

99.1%

100.0%

5 s

585

105,662

Number of combinational gates

Number of non-scan flip-flops (10 gates each)

Number of scan flip-flops (14 gates each)

Gate overhead

Number of faults

PI/PO for ATPG

Fault coverage

Fault efficiency

CPU time on SUN Ultra II, 200MHz processor

Number of ATPG vectors

Scan sequence length


21/35


Partial-Scan DefinitionPartial-Scan Definition A subset of flip-flops is scanned.

Objectives: Minimize area overhead and scan

sequence length, yet achieve requiredfault coverage

Exclude selected flip-flops from scan: Improve performance

Allow limited scan design rule violations

Allow automation: In scan flip-flop selection In test generation

Shorter scan sequences


22/35


Partial-Scan ArchitecturePartial-Scan Architecture

FF

FF

SFF

SFF

Combinationalcircuit

PI PO

CK1

CK2 SCANOUT

SCANIN

TC


23/35


A Partial-Scan MethodA Partial-Scan Method

Select a minimal set of flip-flops for scan

to eliminate all cycles.

Alternatively, to keep the overhead low

only long cycles may be eliminated.

In some circuits with a large number ofself-loops, all cycles other than self-loops

may be eliminated.


24/35


The MFVS ProblemThe MFVS Problem For a directed graph find a set of vertices with

smallest cardinality such that the deletion of thisvertex-set makes the graph acyclic.

The minimum feedback vertex set(MFVS) problemis NP-complete; practical solutions use heuristics.

A secondary objective of minimizing the depth ofacyclic graph is useful.

1 2

3

4 5 6

L=3

1 2

3

4 5 6L=2

L=1

s-graphA 6-flip-flop circuit


25/35


Partial Scan ExamplePartial Scan Example Circuit: TLC

355 gates

21 flip-flops

Scan Max. cycle Depth* ATPG Fault sim. Fault ATPG Test seq.

flip-flops length CPU s CPU s cov. vectors length

0 4 14 1,247 61 89.01% 805 805

4 2 10 157 11 95.90% 247 1,249

9 1 5 32 4 99.20% 136 1,382

10 1 3 13 4 100.00% 112 1,256

21 0 0 2 2 100.00% 52 1,190

* Cyclic paths ignored


26/35


Test Length StatisticsTest Length Statistics Circuit: TLC

200

100

00 50 100 150 200 250

Numb

er

offau

lts

200

100

00 5 10 15 20 25

Numbe

r

offaults

200

100

00 5 10 15 20 25

Number

offaults

Without scan

9 scan flip-flops

10 scan flip-flops

Test

length

Test

length

Test

length


27/35


Partial vs. Full Scan:

S5378

Partial vs. Full Scan:

S5378

Original

2,781

179

0

0.0%4,603

35/49

70.0%

70.9%

5,533 s

414

414

Full-scan

2,781

0

179

15.66%4,603

214/228

99.1%

100.0%

5 s

585

105,662

Number of combinational gates

Number of non-scan flip-flops

(10 gates each)

Number of scan flip-flops

(14 gates each)

Gate overhead

Number of faults

PI/PO for ATPG

Fault coverage

Fault efficiency

CPU time on SUN Ultra II200MHz processor

Number of ATPG vectors

Scan sequence length

Partial-scan

2,781

149

30

2.63%

4,603

65/79

93.7%

99.5%

727 s

1,117

34,691


28/35


Random-Access Scan (RAS)Random-Access Scan (RAS)

POPI

Combinational

logic

RAM

nff

bits

SCANOUTSCANIN

CK

TC

ADDRESS

ACK

Address scan

register

log2 nffbits

Address decoder

SEL


29/35


RAS Flip-Flop (RAM Cell)RAS Flip-Flop (RAM Cell)

Scan flip-flop

(SFF)

Q To comb.

logic

D

SD

From comb. logic

SCANIN

TCCK

SELSCANOUT


30/35


RAS ApplicationsRAS Applications Logic test:

Reduced test length Reduced scan power

Delay test: Easy to generate single-input-change

(SIC) delay tests.

Advantage: RAS may be suitable for certainarchitecture, e.g., where memory is implemented

as a RAM block.

Disadvantages:

Not suitable for random logic architecture High overhead gates added to SFF, address

decoder, address register, extra pins and routing


31/35


Boundary Scan (BS)

IEEE 1149.1 Standard

Boundary Scan (BS)

IEEE 1149.1 Standard

Developed for testing chips on a printed circuitboard (PCB).

A chip with BS can be accessed for test from theedge connector of PCB.

BS hardware added to chip: Test Access port (TAP) added

Four test pins

A test controller FSM

A scan flip-flop added to each I/O pin. Standard is also known as JTAG (Joint Test

Action Group) standard.


32/35


Boundary Scan Test LogicBoundary Scan Test Logic


33/35


SummarySummary

Scan is the most popular DFT technique:

Rule-based design

Automated DFT hardware insertion

Combinational ATPG

Advantages:

Design automation

High fault coverage; helpful in diagnosis

Hierarchical scan-testable modules are easily combined

into large scan-testable systems Moderate area (~10%) and speed (~5%) overheads

Disadvantages:

Large test data volume and long test time

Basically a slow speed (DC) test

Variations of scan:

Partial scan

Random access scan (RAS)

Boundary scan (BS)


34/35


Problems to SolveProblems to Solve What is the main advantage of scan method?

Given that the critical path delay of a circuit is 800ps andthe scan multiplexer adds a delay of 200ps, determine theperformance penalty of scan as percentage reduction in theclock frequency. Assume 20% margin for the clock period

and no delay due to the extra fanout of flip-flop outputs.

How will you reduce the test time of a scan circuit by afactor of 10?


35/35


SolutionsSolutions What is the main advantage of scan method?

Only combinational ATPG (with lower complexity) is used.

Given that the critical path delay of a circuit is 800ps and the scanmultiplexer adds a delay of 200ps, determine the performance penaltyof scan as percentage reduction in the clock frequency. Assume 20%margin for the clock period and no delay due to the extra fanout of flip-flop outputs.

Clock period of pre-scan circuit = 800+160 = 960ps

Clock period for scan circuit = 800+200+200 = 1200ps

Clock frequency reduction = 100(1200-960)/1200 = 20%

How will you reduce the test time of a scan circuit by a factor of 10?

Form 10 scan registers, each having 1/10th the length of a single scanregister.

VLSI Testing - DFT and Scan

Documents

Transcript of VLSI Testing - DFT and Scan