CSE477 L28 DFT.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 28: Design for...

CSE477 L28 DFT.1 Irwin&Vijay, PSU, 2003

CSE477VLSI Digital Circuits

Fall 2003

Lecture 28: Design for Test

Mary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477

[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]


Test Procedures

Diagnostic test used in debugging and defect localization can afford to spend time testing

Production test - “go/no go” used in chip production (wafer and/or packaged) since have to test each part, must be fast

Parametric test [v, i] versus [0,1] check parameters such as noise margins, Vt, tp at corners (range

of temperatures and supply voltage variations) usually done with special wafer drop-ins


Testing Fabricated Designs

Goals of design-for-test (DFT) make testing of manufactured parts swift and comprehensive

DFT mantra Provide controllability and observability

Components of DFT strategy Provide test patterns that guarantee reasonable coverage Provide circuitry to enable testing


Two Important Test Properties

Controllability - measures the ease of bringing a node to a given condition using only the input pins

Observability - measures the ease of observing the value of a node at the output pins

Need both! combinational circuits are both - so relatively easy to determine

test patterns state in sequential circuits problematic - so turn into a

combinational circuit (or use self-test)


Generating and Validating Test Vectors

Automatic test-pattern generation (ATPG) for given fault, determine excitation vector (called test vector)

that will propagate error to primary (observable) output majority of available tools: combinational networks only sequential ATPG available from academic research

Fault simulation determines test coverage of proposed test-vector set simulates correct network in parallel with faulty networks

Both require adequate models of faults in CMOS integrated circuits


Fault Models

Stuck-at models sa0 - stuck at zero (short-circuit to GND) sa1 - stuck at one (short-circuit to Vdd)

A

B

C

Z

- A sa1

- A sa0 or B sa0

- C sa1 or Z sa0


Problem with Stuck-at Model

sequential effect - needs two vectors to ensure detection

A

B

BA

Z

A B Z

1 1 0

0 - 1

1 0 Zi-1

output node floats(retains old value)


Path Sensitization

Determine the input pattern that makes a fault controllable (triggers the fault) and observable (makes its impact visible at the output nodes)

AB

CD

E

U

X

Y

Z

sa0

Controllable:

Observable:

Try to set U to 1 A = 1 and B = 1

Propagate U to Z X = 1 and E = 0

1

11

1

11

0


Test Problem Size

comblogic

module

N inputs

K outputs

2N input patterns

comblogic

module

N inputs

K outputs

2N+M input patterns

M state regs

N=20 1 million patterns1 sec/pattern 1 second test

N=20, M=10 1 billion patterns1 sec/pattern 16 minute test


Reducing Number of Test Vectors

Two features can be exploited to reduce the number of test vectors

Redundancy - a single fault in the circuit is usually covered by several input patterns; detection of the fault requires only one

Reduced fault coverage - relax the requirement that all faults be detected (95% to 99% fault coverage is typical)


Test Approaches

Scan based test

Self test

Ad-hoc testing

Problem is getting harder increasing complexity and heterogeneous combination of

modules in system-on-a-chip. advanced packaging and assembly techniques extend problem

to the board level


Scan Based Test

Comblogic

A

reg

A

Comblogic

B

reg

B

In Out

Scanin Scanout

Two operational modes normal mode (N-bit wide clocked registers) test mode (registers chained as a single serial shift register)

run

test

run

test


Scan Path FF Implementation

Q (&scanout)

D

QM

run

scanin

test


Polarity Hold Shift FF

flipflop

latch

Qsystem data

!Q

scanout

!scanout

run

scanin

testA

testB

Introduced at IBM and set as company policy for all designs


Scan Register

FF

Test!Test

Test

In0

Out0

ScaninFF

Test!Test

Test

In1

Out1

FF

Test!Test

Test

In2

Out2

FF

Test!Test

Test

In3

Out3

Scanout

Test

Clock

N cyclesscan in

N cyclesscan out

1 cycleevaluate


Scan Path Testing

Partial scan can be more effective for pipelined datapaths

REG[5]

REG[4]

REG[3]REG[2]

REG[0]REG[1]

COMP

OUT

SCANIN

COMPIN

SCANOUT

A B


Boundary Scan (JTAG)

Printed-circuit board

Logic

scan path

normal interconnect

Packaged IC

Bonding Pad

Scan-in

Scan-out

si so

Board testing becoming as problematic as chip testing


Built in Self Test (BIST) The circuit decides if the results are correct!

Need a way to supply test patterns (stimulus generator) and to compare the circuit’s responses to a known correct sequence (response analyzer)

(Sub)circuitunder testStimulus

generatorResponseanalyzer

Testcontroller


Stimulus Generator (LRSR)

1 0 0 0

A1 A2 A3

Pseudo-random pattern generator

A0

0 1 0 00 0 1 01 0 0 11 1 0 00 1 1 0

1 1 0 10 0 0 1


Response Analyzer

Counter

Latch

In

Counts the number of 0 1 and 1 0 transitions

Counter value (signature of the circuit) is then compared to the known correct count

Signature Analysis

0 01010

01010 0

01111 0

to comparison circuitry

4


BILBO

R

In0

S0

R

S1

In1

R

In2

S2

B0

B1

s can

in

s can

iou t

B0 B1 Op Mode

1 1 Normal 0 0 Scan 1 0 0 1

0 0 0

In0 In1 In2

1

1

0

00 0 0

sc !sc !S0 !S1


BILBO

R

In0

S0

R

S1

In1

R

In2

S2

B0

B1

s can

in

s can

iou t

B0 B1 Op Mode

1 1 Normal 0 0 Scan 1 0 BIST 0 1 Reset

0 0 0

In0 In1 In2

1

0

0

10 0 0

sc !sc !S0 !S1

Ini !Si-1


Use of BILBO

Comblogic

A

BILB

O A

Comblogic

B

In Out

seedin Scanout

Reg A is a BILBO register doing pattern generation to test Comb logic A

run

test

Reg B is a BILBO register doing signature analysis to test Comb logic A

BILB

O B

run

test


Ad-Hoc Test

Inserting multiplexer improves testability

I/O bus

data

Memory

Processor

addr

ess

I/O bus

data

Memory

Processor

addr

ess

test select


Memory Self Test

FSM Memory Under Test

Signature Analysis

data_in

address & R/W control

data_out

Patterns: Writing/Reading 0s, 1s, Walking 0s, 1s Galloping 0s, 1s

CSE477 L28 DFT.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 28: Design for...

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