Vlsi Mid Term

7/29/2019 Vlsi Mid Term

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Submitted By:

Amardeep Kaur (Write your Red. No. here)

Gagandeep Kaur ()

Harinder Kaur ()

Nikunj Sehgal ()



Company Profile

"Dream Tech Labs" is a division of Dreamweavers group and powered by DUCAT.

It is providing Project based Industrial

training to the students where they are

learn latest technologies and work on LIVEprojects guided by companies under the

guidance of our experienced faculty.

The curriculum of the Project basedIndustrial Training is based on the latest

technologies.

Website: www.dreamtechlabs.com

http://www.dreamtechlabs.com/

http://www.dreamtechlabs.com/



Training Modules

Module1: Fundamentals of Digital Design

Module2: Advanced Digital Design

Module3: VHDL

Module4: Verilog

Module5: Advanced Verilog

Module6: System Verilog



INTRUDUCTION

Very Large Scale Integration:

design/manufacturing of extremely small,

complex circuitry using modified

semiconductor material

integrated circuit (IC) may contain

millions of transistors or CMOS, each a

few mm in size



Integrated Circuits

Integrated Type Number of Gates

Small Scale Integrated Circuits Upto 10

Medium Scale Integrated Circuits 10 - 100

Large Scale Integrated Circuits 100 – 10000

Very Large Scale Integrated Circuits More than 10000



Moore’s Law

The level of integration of silicontechnology as measured in terms of number of devices per IC

This comes about in two ways – sizereduction of the individual devices andincrease in the chip or dice size



Moore’s Law

The number of transistors on an

integrated circuit will double every 18

months



VLSI Logic Families

Transistor -Transistor Logic (TTL)

Emitter Coupled Logic (ECL)

Gallium Arsenide (GaAs)

Complementary Metal Oxide

Semiconductor (CMOS)



VLSI DESIGN FLOWDesign Specifications

Behavioral Description

RTL Description(HDL)

Functional Verification & Testing

Logic Synthesis

Gate-level Netlist

Logic Verification & Testing

Floor planning & Automatic Placing

Physical Layout & Verification

Implementation



VLSI Design…

Design Specification: It describe

abstractly the functionality, interface and

overall architecture of the digital circuit

to be designed. Behavioral Description: It is used to

analyze the design in terms of

functionality and performance. It can bewritten with HDLs and manually

converted to RTL description.



VLSI Design…

RTL Description: In this section designer

has to describe the data flow with that

will implement the desired digital circuit.

Logic Synthesis: Logic synthesis toolsconverts the RTL description to gate

level netlist.



VLSI Design…

Gate-Level Netlist: It is a description of

the circuits in term of gates and

connections between them.

Logic Verification and Testing: In thissection verify the logic and test it, if logic

is not accurately works then it returns

back to the RTL description.



VLSI Design…

Flour Planning and Automatic Placing: Inthis section we should plane for thebase of an IC and automatically place

the component according to our code. Physical Layout and Verification: In this

section we can take the layout of IC andverify it.

Implementation: If all the above sectionaccurate then go for production of Integrated circuits(ICs).



Comparison of VHDL &

VERILOGSr. No. V-HDL VERILOG -HDL

1. VHDL stand form is Very High

Speed Integrated Circuits

Hardware Description

Language

Verilog stand form is Very Logic

Hardware Description language

2. Case Insensitive Case Sensitive

3. Limited to gate level modeling Limited to switch level

4. Libraries and Packages areexist

Libraries and Packages are notexist

5. Simulation Process is slow Simulation Process is fast

6. Similar to EDA language Similar to C language



VHDL Introduction

VHDL is a hardware description languagethat can be used to model a digital systemat many levels of abstraction ranging fromthe algorithmic level to the gate level.

The VHDL language can be regarded asan integrated of the following languages:

Sequential language + Concurrent

language + Net-list language + Timingspecifications + Waveform generationlanguage => VHDL



VHDL Terminology

VHDL is a hardware description languagethat can be used to model a digital system.The digital system can be as simple as alogic gate or as complex as a completeelectronic system.

VHDL provides five different types of primary constructs called design units.

Entity declaration

Architecture body

Configuration declaration Package declaration

Package body



VHDL Terminology….

VHDL consists of three types of

modeling :

Dataflow Modeling: Set of concurrent

assignment statements Structural Modeling: Set of interconnected

components

Behavioral Modeling: Set of sequential

assignment statements



Full Subtractor

(Dataflow Modeling) Source Code:

library ieee;

use ieee.std_logic_1164.all;

entity full_subtractor is

port(X,Y,Z : in std_logic;

D,B : out std_logic);

end full_subtractor;

architecture dflow of full_subtractor is

beginD <= X xor Y xor Z;

B <= ((not X) and Y) or (Y and Z) or ((not X) and Z);

end dflow;



Waveform of Subtractor



Half Adder

(Structural Modeling) Source Code:

library ieee;


entity half_adder is

port (A,B:in bit;SUM,CARRY:out bit);

end half_adder;

architecture structure of half_adder iscomponent xor2

port(p,q:in bit;r:out bit);

end component;

component and2

port(l,m:in bit;n:out bit);

end component;

begin

X1: xor2 port map(A,B,SUM);

A1: and2 port map(A,B,CARRY);

end structure;



Waveform of Half Adder



JK Flip Flop

(Behavioral Modeling) Source Code:

library ieee;


entity jk_ff is

port(j,k,clk,rst:std_logic;q,qbar:

buffer std_logic);

end jk_ff;architecture behave of jk_ff is

begin

process(j,k,clk,rst)

begin

qbar<= not q;

if(rst='1')then q<='0';

elsif(clk'event and clk='1')then

q<=((j and(not q))or((not k)and q));

end if;

end process;

end behave;



Waveform of JKFF



PROJECT DETAIL

Problem’s Statement: Write a program

code or source code to design a D flip

flop using behavioral modeling with

assertion statements for holdup andsetup time.

S C d



Source Codelibrary ieee;


entity DFF_assert is

port (D, CK: in BIT; Q, NOTQ: out BIT);

end DFF_assert;architecture CHECK_TIMES of DFF_assert is

constant HOLD_TIME: TIME := 5 ns;

constant SETUP_TIME: TIME := 3 ns;

begin

process (D, CK)

variable LastEventOnD, LastEventOnCk: TIME;

begin

--Check for hold time:

if D' EVENT then

assert (NOW = 0ns) or

((NOW - LastEventOnCk) >= HOLD_TIME)

report "Hold time too short!"

severity FAILURE;

LastEventOnD := NOW;

end if;-- Check for setup time:

if (CK = '1') and CK'EVENT then

assert NOW = 0ns or((NOW - LastEventOnD) >= SETUP_TIME)

report "Setup time too short!"

severity FAILURE;

LastEventOnCk := NOW;

end if;



Waveforms



SUMMARY

Introduction of VLSI

VLSI Design Flow

Moore’s Law

Comparison of VHDL and Verilog

Introduction of VHDL

VHDL Terminology

Examples of VHDL Modeling

Live Project



Thanks…

Vlsi Mid Term

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