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Transcript of VLSI Lab Manual
![Page 1: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/1.jpg)
Dr. M. G. REducational and Research Institute
University
Department of Electronics and Communication Engineering
VLSI & Embedded System Design Lab
Subject Code: BEC 427
![Page 2: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/2.jpg)
List of ExperimentsEx. No Date Experiment Name Signature
XILINX Verilog HDL01 (A) HALF ADDER
01 (B) FULL ADDER
02 (A) HALF SUBTRACTOR
02 (B) FULL SUBTRACTOR
03 MULTIPLEXER
04 DE - MULTIPLEXER
05 D – FLIP FLOP
06 T – FLIP FLOP
07 JK – FLIP FLOP
08 ENCODER
09 DECODER
XILINX VHDL01(A) HALF ADDER
01(B) FULL ADDER
02(A) HALF SUBTRACTOR
03(B) FULL SUBTRACTOR
04 MULTIPLEXER
05 DE - MULTIPLEXER
06 ENCODER
07 DECODER
PIC Microcontroller01 Study Of PIC Microcontroller
02 Design of LED Display
03 Design DC Motor Controller
04 Design of LCD Display
05 Design of RS 232
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Verilog HDL
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EX. NO: 01 A Date:
HALF ADDER
AIM:
To Write a Program in Verilog HDL for HALF ADDER.
PROGRAM:
module Halfadd1(i0, i1, sum, c_out);
input i0;
input i1;
output sum;
output c_out;
xor(sum,i1,i2);
and(c_out,i1,i2);
endmodule
OUTPUT:
![Page 5: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/5.jpg)
TRUTH TABLE:
Input1 Input2 Carry Sum
0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0
![Page 6: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/6.jpg)
SIMULATION OUTPUT:
RESULT:
Thus the HALF ADDER Circuit was designed and verified.
EX. NO: 01 B Date:
![Page 7: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/7.jpg)
FULL ADDER
AIM:
To Write a Program in Verilog HDL for FULL ADDER.
PROGRAM:
module Fulladd(i1, i2, sum, c_in, c_out);
input i1;
input i2;
output sum;
input c_in;
output c_out;
wire s1,c1,c2;
xor n1(s1,i1,i2);
and n2(c1,i1,i2);
xor n3(sum,s1,c_in);
and n4(c2,s1,c_in);
or n5(c_out,c1,c2);
endmodule
OUTPUT:
![Page 8: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/8.jpg)
TRUTH TABLE:
i1 i2 C_in C_out Sum
0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1
SIMULATION OUTPUT:
RESULT:
Thus the FULL ADDER Circuit was designed and verified.
EX. NO: 02 A Date:
![Page 9: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/9.jpg)
HALF SUBTRACTOR
AIM:
To Write a Program in Verilog HDL for HALF SUBTRACTOR.
PROGRAM:
module halfsub2(i0, i1, bor, dif);
input i0;
input i1;
output bor;
output dif;
wire i0n;
not(i0n,i0);
xor(dif,i0,i1);
and(bor,i0n,i1);
endmodule
OUTPUT:
![Page 10: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/10.jpg)
TRUTH TABLE:
Input1 Input2 Borrow Difference0 0 0 00 1 1 11 0 0 11 1 0 0
SIMULATION OUTPUT:
RESULT:
Thus the HALF SUBTRACTOR Circuit was designed and verified.EX. NO: 02 B Date:
![Page 11: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/11.jpg)
FULL SUBTRACTOR
AIM:
To Write a Program in Verilog HDL for FULL SUBTRACTOR.
PROGRAM:
Module Full sub (b_in, i0, i1, dif, b_out);
input b_in;
input i0;
input i1;
output dif;
output b_out;
assign {b_out,dif}=i0-i1-b_in;
end module;
OUTPUT:
![Page 12: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/12.jpg)
TRUTH TABLE:
B_IN i1 i0 B_OUT DIFF0 0 0 0 00 0 1 0 10 1 0 1 10 1 1 0 01 0 0 1 11 0 1 0 01 1 0 1 01 1 1 1 1
SIMULATION OUTPUT:
RESULT:
Thus the FULL SUBTARCTOR Circuit was designed and verified.
EX. NO: 03 Date:
![Page 13: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/13.jpg)
MULTIPLEXER
AIM:
To Write a Program in Verilog HDL for MULTIPLEXER.
PROGRAM:
module Mux(i0, i1, i2, i3, s0, s1, out);
input i0;
input i1;
input i2;
input i3;
input s0;
input s1;
output out;
wire s1n,s0n;
wire y0,y1,y2,y3;
not (s1n,s1);
not (s0n,s0);
and (y0,i0,s1n,s0n);
and (y1,i1,s1n,s0);
and (y2,i2,s1,s0n);
and (y3,i3,s1,s0);
or (out,y0,y1,y2,y3);
end module;
![Page 14: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/14.jpg)
OUTPUT:
TRUTH TABLE:
S0 S1 OUTPUT
0 0 10 1 11 0 01 1 1
SIMULATION OUTPUT:
RESULT:
Thus the MULTIPLEXER Circuit was designed and verified.
EX. NO: 04 Date:
![Page 15: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/15.jpg)
DEMULTIPLUXER
AIM:
To Write a Program in Verilog HDL for DEMULTIPLEXER.
PROGRAM:
module Demux(in, s0, s1, out0, out1, out2, out3);
input in;
input s0;
input s1;
output out0;
output out1;
output out2;
output out3;
wire s0n,s1n;
not(s0n,s0);
not(s1n,s1);
and (out0,in,s1n,s0n);
and (out1,in,s1n,s0);
and (out2,in,s1,s0n);
and (out3,in,s1,s0);
endmodule;
![Page 16: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/16.jpg)
OUTPUT:
TRUTH TABLE:
s0 s1 out0 out1 out2 out30 0 0 1 1 10 1 1 0 1 11 0 1 1 0 11 1 1 1 1 0
SIMULATION OUTPUT:
RESULT:
Thus the DEMULTIPLEXER Circuit was designed and verified.
![Page 17: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/17.jpg)
EX. NO: 05 Date:
D-FLIP FLOP
AIM:
To Write a Program in Verilog HDL for D-FLIP FLOP.
PROGRAM:
module dff(clock, reset, d, q);
input clock;
input reset;
input d;
output q;
reg q;
always @(posedge clock or negedge reset)
if(~reset)q=0;
else q=d;
endmodule
OUTPUT:
![Page 18: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/18.jpg)
TRUTH TABLE:
SIMULATION OUTPUT:
RESULT:
Thus the D-FLIP FLOP Circuit was designed and verified.
CLOCK RESET INPUT (D) OUTPUT Q(~Q)
0 0 0 0(1)
1 0 0 0(1)
0 0 1 0(1)
1 0 1 0(1)
0 0 0 0(1)
1 0 0 0(1)
0 1 1 0(1)
1 1 1 1(0)
0 1 0 1(0)
1 1 0 0(1)
0 1 1 0(1)
1 1 1 1(0)
0 0 0 0(1)
1 0 0 0(1)
0 0 0 0(1)
![Page 19: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/19.jpg)
EX. NO: 06 Date:
T-FLIP FLOP
AIM:
To Write a Program in Verilog HDL for T-FLIP FLOP.
PROGRAM:
module Tff(Clock, Reset, t, q);
input Clock;
input Reset;
input t;
output q;
reg q;
always@(posedge Clock , negedge Reset)
if(~Reset) q=0;
else if (t) q=~q;
else q=q;
endmodule
OUTPUT:
TRUTH TABLE:
![Page 20: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/20.jpg)
CLOCK RESET Q(~Q) INPUT (T) OUTPUT
0 0 0 0(1)1 0 0 0(1)0 0 1 0(1)1 0 1 0(1)0 0 0 0(1)1 0 0 0(1)0 1 1 0(1)1 1 1 1(0)0 1 0 1(0)1 1 0 1(0)0 1 1 1(0)1 1 1 0(1)0 0 0 0(1)1 0 0 0(1)0 0 0 0(1)
SIMULATION OUTPUT:
RESULT:
Thus the T-FLIP FLOP Circuit was designed and verified.
EX. NO: 07 Date:
![Page 21: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/21.jpg)
JK-FLIP FLOP
AIM:
To Write a Program in Verilog HDL for JK-FLIP FLOP.
PROGRAM:
module JKff(Clock , Reset, j, k, q);
input Clock ;
input Reset;
input j;
input k;
output q;
reg q;
always@(posedge Clock, negedge Reset)
if(~Reset)q=0;
else
begin
case({j,k})
2'b00: q=q;
2'b01: q=0;
2'b10: q=1;
2'b11: q=~q;
endcase
end
endmodule
OUTPUT:
![Page 22: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/22.jpg)
TRUTH TABLE:
CLOCK RESET INPUT (JK) OUTPUT q(~q)
0 0 00 0(1)1 0 00 0(1)0 0 01 0(1)1 0 01 0(1)0 0 10 0(1)1 0 10 0(1)0 0 11 0(1)1 0 11 0(1)0 1 00 0(1)1 1 00 0(1)0 1 01 0(1)1 1 01 0(1)0 1 10 0(1)1 1 10 1(0)0 1 11 1(0)1 1 11 0(1)0 0 00 0(1)1 0 00 0(1)0 0 00 0(1)
![Page 23: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/23.jpg)
SIMULATION OUTPUT:
RESULT:
Thus the JK-FLIP FLOP Circuit was designed and verified.
EX. NO: 08 Date:
ENCODER
AIM:
To Write a Program in Verilog HDL for ENCODER.
PROGRAM:
module Encode(i0, i1, i2, i3, out0, out1);
input i0;
input i1;
![Page 24: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/24.jpg)
input i2;
input i3;
output out0;
output out1;
reg out0,out1;
always @(i0,i1,i2,i3)
case({i0,i1,i2,i3})
4'b1000:{out0,out1}=2'b00;
4'b0100:{out0,out1}=2'b01;
4'b0010:{out0,out1}=2'b10;
4'b0001:{out0,out1}=2'b11;
endcase
endmodule
OUTPUT:
TRUTH TABLE:
I0 I1 I2 I3 Out0 Out11 0 0 0 0 00 1 0 0 0 10 0 1 0 1 00 0 0 1 1 1
![Page 25: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/25.jpg)
SIMULATION OUTPUT:
RESULT:
Thus the ENCODER Circuit was designed and verified.
EX. NO: 09 Date:
DECODER
AIM:
To Write a Program in Verilog HDL for DECODER.
PROGRAM:
module Decode(i0, i1, out0, out1, out2, out3);
input i0;
input i1;
output out0;
output out1;
![Page 26: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/26.jpg)
output out2;
output out3;
reg out0,out1,out2,out3;
always @(i0,i1)
case({i0,i1})
2'b00:{out0,out1,out2,out3}=4'b1000;
2'b01:{out0,out1,out2,out3}=4'b0100;
2'b10:{out0,out1,out2,out3}=4'b0010;
2'b11:{out0,out1,out2,out3}=4'b0001;
endcase
endmodule
OUTPUT:
TRUTH TABLE:
I0 I1 Out0 Out1 Out2 Out30 0 1 0 0 00 1 0 1 0 01 0 0 0 1 01 1 0 0 0 1
![Page 27: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/27.jpg)
SIMULATION OUTPUT:
RESULT:
Thus the DECODER Circuit was designed and verified.
![Page 28: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/28.jpg)
VHDL
Expt. No. 1 A Date:
HALF ADDERSTRUCTURAL MODEL
AIM:
To write a program in VHDL for HALF ADDER.
PROGRAM:
library IEEE;
![Page 29: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/29.jpg)
use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity haladdbe is Port ( a : in std_logic; b : in std_logic; s : out std_logic; c : out std_logic);end haladdbe;
architecture Behavioral of haladdbe is
begins<=(a xor b);c<=(a and b);
end Behavioral;
OUTPUT
![Page 30: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/30.jpg)
RESULT:
Thus the HALF ADDER circuit was designed and verified.
Expt. No. 1B Date:
FULL ADDERSTRUCTURAL MODEL
AIM:
To write a program in VHDL for FULL ADDER.
PROGRAM:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;
![Page 31: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/31.jpg)
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full3 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; s: out std_logic; Carry:out std_logic);end full3;
architecture Behavioral of full3 is
begin s<=(a xor b) xor c; carry<=(a and b) or (a and c) or (b and c); end Behavioral;
OUTPUT
![Page 32: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/32.jpg)
RESULT:
Thus the FULL ADDER circuit was designed and verified.
Expt. No. 2 A Date:
HALF SUBTRACTORSTRUCTURAL MODEL
AIM:
To write a program in VHDL for HALF SUBTRACTOR.
PROGRAM:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hlfsub is Port ( a : in std_logic;
![Page 33: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/33.jpg)
b : in std_logic; y : out std_logic; x : out std_logic);end hlfsub;
architecture Behavioral of hlfsub is
begin y<= a xor b; x<= b and ( not(a));
end Behavioral;
OUTPUT
![Page 34: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/34.jpg)
RESULT:
Thus the HALF SUBTRACTOR circuit was designed and verified.
Expt. No. 2 B Date:
FULL SUBTRACTORSTRUCTURAL MODEL
AIM:
To write a program in VHDL for FULL SUBTRACTOR.
PROGRAM:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
![Page 35: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/35.jpg)
use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fulsubbe is Port ( x : in std_logic; y : in std_logic; z : in std_logic; d : out std_logic; b : out std_logic);end fulsubbe;
architecture Behavioral of fulsubbe is
begind<=x xor y xor z;b<=(not(x) and y) or (y and z) or (z and (not(x)));
end Behavioral;
OUTPUT
![Page 36: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/36.jpg)
RESULT:
Thus the FULL SUBTRACTOR circuit was designed and verified.
Expt. No. 5 Date:
![Page 37: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/37.jpg)
MULTIPLEXERAIM:
To write a program in VHDL for MULTIPLEXER.
PROGRAM:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux is Port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; s0 : in std_logic; s1 : in std_logic; q : out std_logic);end mux;
architecture Behavioral of mux is
beginprocess(s0,s1,a,b,c,d)beginif s0= '0' thenif s1= '0' thenq<=a;elseq<=b;end if;end if;if s0='1' thenif s1='0' thenq<=c;else q<=d;end if;end if;end process;
end Behavioral;
![Page 38: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/38.jpg)
OUTPUT:
RESULT:
Thus the MULTIPLEXER circuit was designed and verified.
Expt. No. 6 Date: 01/08/07
![Page 39: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/39.jpg)
DEMULTIPLEXERAIM:
To write a program in VHDL for DEMULTIPLEXER.
PROGRAM:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux is Port ( a : in std_logic; b : in std_logic; y0 : out std_logic; y1 : out std_logic; y2 : out std_logic; y3 : out std_logic);end demux;
architecture Behavioral of demux is
beginprocess(a,b)beginif a='0' thenif b='0' theny0<='0';y1<='1';y2<='1';y3<='1';elsey0<='1';y1<='0';y2<='1';y3<='1';end if;end if;if a='1' thenif b='0' theny0<='1';y1<='1';y2<='0';y3<='1';else
y0<='1';y1<='1';
![Page 40: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/40.jpg)
y2<='1';y3<='1';end if;end if;end process;
end Behavioral;
OUTPUT
RESULT:
Thus the DEMULTIPLEXER circuit was designed and verified.
Expt. No. 7 Date: 01/08/07
![Page 41: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/41.jpg)
ENCODER
AIM:
To write a program in VHDL for ENCODER.
PROGRAM:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder is Port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; x : out std_logic; y : out std_logic);end encoder;
architecture Behavioral of encoder is
beginprocess(a,b,c,d)beginif a='0' thenif b='0' thenif c='0' thenif d='0' thenx<='0';y<='0';elsif d='1' thenx<='0';y<='1';elsif c='1' thenx<='1';y<='0';elsif b='1' thenx<='1';y<='1';end if;end if;end if;
![Page 42: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/42.jpg)
end if;end process;
end Behavioral;
OUTPUT
RESULT:
Thus the ENCODER circuit was designed and verified.
![Page 43: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/43.jpg)
Expt. No. 8 Date: 01/08/07
DECODER
AIM:
To write a program in VHDL for DECODER.
PROGRAM:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is Port ( a : in std_logic; b : in std_logic; d1 : out std_logic; d2 : out std_logic; d3 : out std_logic; d4 : out std_logic);end decoder;
architecture Behavioral of decoder is
beginprocess(a,b)beginif a='0' thenif b='0' thend1<='1';d2<='0';d3<='0';d4<='0';elsed1<='0';d2<='1';d3<='0';d4<='0';end if;end if;if a='1' thenif b='0' then
![Page 44: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/44.jpg)
d1<='0';
d2<='0';d3<='1';d4<='0';elsed1<='0';d2<='0';d3<='0';d4<='1';end if;end if;end process;
end Behavioral;
OUTPUT
![Page 45: VLSI Lab Manual](https://reader034.fdocuments.net/reader034/viewer/2022042521/54739d02b4af9f0f788b46bd/html5/thumbnails/45.jpg)
RESULT:
Thus the DECODER circuit was designed and verified.
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EX. NO: 01 Date:
PIC Microcontroller
Introduction:
PIC16F877A-I/P Microcontroller, 40 DIP, 20 MHz
High-Performance, Enhanced PIC Flash Microcontroller in 40-pin PDIP
The PIC16F877A CMOS FLASH-based 8-bit microcontroller is upward compatible with the PIC16C5x, PIC12Cxxx and PIC16C7x devices. It features 200 ns instruction execution, 256 bytes of EEPROM data memory, self programming, an ICD, 2 Comparators, 8 channels of 10-bit Analog-to-Digital (A/D) converter, 2 capture/compare/PWM functions, a synchronous serial port that can be configured as either 3-wire SPI or 2-wire I2C bus, a USART, and a Parallel Slave Port.
Microchip PIC16F877A Microcontroller Features
High-Performance RISC CPU
Lead-free; RoHS-compliant Operating speed: 20 MHz, 200 ns instruction cycle Operating voltage: 4.0-5.5V Industrial temperature range (-40° to +85°C) 15 Interrupt Sources 35 single-word instructions All single-cycle instructions except for program
branches (two-cycle)
Special Microcontroller Features Flash Memory: 14.3 Kbytes (8192 words) Data SRAM: 368 bytes Data EEPROM: 256 bytes Self-reprogrammable under software control In-Circuit Serial Programming via two pins (5V) Watchdog Timer with on-chip RC oscillator Programmable code protection
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Power-saving Sleep mode Selectable oscillator options In-Circuit Debug via two pins
This
powerful (200 nanosecond instruction execution) yet easy-to-program (only 35 single word instructions) CMOS FLASH-based 8-bit microcontroller packs Microchip's powerful PIC® architecture into an 40- or 44-pin package and is upwards compatible with the PIC16C5X, PIC12CXXX and PIC16C7X devices. The PIC16F877A features 256 bytes of EEPROM data memory, self programming, an ICD, 2 Comparators, 8 channels of 10-bit Analog-to-Digital (A/D) converter, 2 capture/compare/PWM functions, the synchronous serial port can be configured as either 3-wire Serial Peripheral Interface (SPI™) or the 2-wire Inter-Integrated Circuit (I²C™) bus and a Universal Asynchronous Receiver Transmitter (USART). All of these features make it ideal for more advanced level A/D applications in automotive, industrial, appliances and consumer
applications.
Features
2 PWM 10-bit256 Bytes EEPROM data memoryICD25mA sink/source per I/OSelf ProgrammingParallel Slave Port
Parameter Name Value
Program Memory Type Flash Program Memory (KB) 14 CPU Speed (MIPS) 5 RAM Bytes 368 Data EEPROM (bytes) 256 Digital Communication Peripherals
1-A/E/USART, 1-MSSP(SPI/I2C)
Capture/Compare/PWM Peripherals
2 CCP
Timers 2 x 8-bit, 1 x 16-bit ADC 8 ch, 10-bit Comparators 2 Temperature Range (C) -40 to 125 Operating Voltage Range (V)
2 to 5.5
Pin Count 40
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Peripheral Features 33 I/O pins; 5 I/O ports Timer0: 8-bit timer/counter with 8-bit prescaler Timer1: 16-bit timer/counter with prescaler
o Can be incremented during Sleep via external crystal/clock Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler Two Capture, Compare, PWM modules
o 16-bit Capture input; max resolution 12.5 ns o 16-bit Compare; max resolution 200 ns o 10-bit PWM
Synchronous Serial Port with two modes: o SPI Master o I2C Master and Slave
USART/SCI with 9-bit address detection
Parallel Slave Port (PSP) o 8 bits wide with external RD, WR and CS controls
Brown-out detection circuitry for Brown-Out Reset
Analog Features 10-bit, 8-channel A/D Converter Brown-Out Reset Analog Comparator module
o 2 analog comparators o Programmable on-chip voltage reference module o Programmable input multiplexing from device inputs and internal VREF o Comparator outputs are externally accessible
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Result:
Thus the Architecture of PIC Microcontroller has been studied
EX. NO: 02 Date:
LED Display
AIM:
To Write a Program to test the working of LED using CCS C compiler and Proteus Simulator.
PROGRAM:
#include <16F877a.h>
#include <string.h>
#use delay (clock=20000000)
#bit LED1=0x7.0
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#bit LED2=0x7.1
Void main ()
{
set_tris_c(0x00);
LED1=LED2=1;
While (22)
{
LED2=LED1=0;
}
}
OUTPUT:
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RESULT:
Thus the Program for working of LED is compiled and simulated using CCS C compiler and Proteus Simulator.
EX. NO: 03 Date:
A Design of DC Motor Controller
AIM:
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To write a program for rotation of DC 12V Motor in forward and reverse direction using CCS C compiler and Proteus Simulator.
PROGRAM:
#include<16F877A.h>
#include<string.h>
#fuses NOWDT,PUT,HS,NOPROTECT
#use delay(clock=20000000)
#define m1f PIN_A2
#define m1r PIN_A5
unsigned int i,temp;
void main()
{
set_tris_a(0x00);
while(1)
{
output_low(m1f);
output_high(m1r);
delay_ms(1000);
output_high(m1f);
output_low(m1r);
delay_ms(1000);
}}
OUTPUT:
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RESULT:
Thus the Program for rotation of DC 12V Motor in forward and reverse direction is compiled and simulated using CCS C compiler and Proteus Simulator.
EX. NO: Date:
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Interfacing to LCD Display
AIM:
To write a program for LCD Display using CCS C compiler and Proteus Simulator.
PROGRAM:
#include<16f877a.h>
#include<stdlib.h>
#include <string.h>
#include<ctype.h>
#use delay (clock=20000000)
#fuses HS,NOWDT,NOPROTECT,NOBROWNOUT,PUT,NOLVP
#define dispfunc 0x38
#define dispccurr 0x0c
#define blkoff 0x06
#define selrow1 0x80
#define selrow2 0xc0
#define dispclear 0x01
#define RS PIN_B7
#define E PIN_B6
void command(unsigned char);
void display(unsigned char);
void disp_init(void);
void clr(unsigned char,unsigned char,unsigned char);
unsigned char adc();
unsigned char abc0, abc1,adcval_p;
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unsigned char p,a,c,d,b,ii,t,cc;
unsigned char k=0;
static unsigned char temp1,temp2;
static unsigned char temp3,temp4;
void command(unsigned char dat)
{
unsigned char i;
output_c(dat);
for(i=0;i<255;i++);
output_low(RS);
for(i=0;i<255;i++);
output_high(E);
for(i=0;i<255;i++);
output_low(E);
}
void display(unsigned char x)
{
unsigned char i;
output_c(x);
for(i=0;i<255;i++);
output_high(RS);
for(i=0;i<255;i++);
output_high(E);
for(i=0;i<255;i++);
output_low(E);
}
void disp_init(void)
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{
command(dispfunc);
command(dispccurr);
command(blkoff);
command(dispclear);
command(selrow2);
command(dispclear);
}
void main()
{
unsigned char k=0,val2;
unsigned int out1,out2,out,a,b;
char temp;
char temp4;
set_tris_c(0x00);
set_tris_e(0x00);
set_tris_b(0xf1);
output_low(RS);
output_low(E);
disp_init();
command(0X01);
command(0X80);
delay_ms(500);
printf(display,"Dr. M.G.R UNIVERSITY");
}
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OUTPUT:
RESULT:
Thus the Program for LCD Display is compiled and Simulated using CCS C compiler and Proteus Simulator.
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EX. NO: Date:
RS-232
AIM:
To write a program for sending data from PIC to PC through RS232 using CCS C compiler and Proteus Simulator.
PROGRAM:
#include<16f877a.h>
#include<stdlib.h>
#include <string.h>
#include<ctype.h>
#use delay (clock=20000000)
#use rs232(baud=9600, xmit=PIN_c6, rcv=PIN_c7,stream=com_1)
#fuses HS,NOWDT,NOPROTECT,NOBROWNOUT,PUT,NOLVP
void clr(unsigned char,unsigned char,unsigned char);
void get();
unsigned char adc0();
static unsigned char temp0,temp1,t1;
unsigned char adc0(void)
{ unsigned char temp0;
set_adc_channel(0); delay_ms(10);
temp0 = read_adc(); delay_ms(10);
return temp0; }
void main(){
setup_adc_ports(A_ANALOG);
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setup_adc(ADC_CLOCK_INTERNAL);
setup_counters(RTCC_INTERNAL,RTCC_DIV_1);
while(1) {
t1=adc0();
fputc('A',com_1); delay_ms(5000);
}}
OUTPUT:
RESULT:
Thus the Program for sending data from PIC to PC through RS232 is compiled and Simulated using CCS C compiler and Proteus Simulator.