Ecad & Vlsi Lab Manual
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Transcript of Ecad & Vlsi Lab Manual
HALF ADDER
Fig : half adder circuit
Expected waveforms
PROGRAM FOR HALF ADDER:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity halfadder is
Port ( a,b : in STD_LOGIC;
S,c : out STD_LOGIC);
end halfadder;
architecture Behavioral of halfadder is
begin
s <= a xor b;
c <= a and b;
end Behavioral;
2X4 DECODER
Fig : 2X4 decoder
Expected waveforms
2X4 DECODER PROGRAM
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dec2_4 is
Port (i0, i1, en : in STD_LOGIC;
y0, y1, y2, y3 : out STD_LOGIC);
end dec2_4;
architecture Behavioral of dec2_4 is
begin
process (i0, i1, en)
begin
if (en='1') then
y0 <= (not i1) and (not i0);
y1 <= (not i1) and (i0);
y2 <= (i1) and (not i0);
y3 <= (i1) and (i0);
end if;
end process;
end Behavioral;
3x8 DECODER
Fig : 3X8 decoder
Expected waveforms
PROGRAM:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dec3_8 is
Port (i0, i1, i2, en: in STD_LOGIC;
y0, y1, y2, y3, y4, y5, y6, y7 : out STD_LOGIC);
end dec3_8;
architecture structural of dec3_8 is
Component deco2_4 is
Port (i0, i1, e: in STD_LOGIC;
y0, y1, y2, y3 : out STD_LOGIC);
end component;
component and2 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end component;
signal s:std_logic_vector(1 downto 0); begin
stage1:and2 port map (not i2, en, s(0));
stage2:and2 port map (i2, en, s(1));
stage3:deco2_4 port map (i0, i1, s(0), y0, y1, y2, y3);
stage4:deco2_4 port map (i0, i1, s(1), y4, y5, y6, y7);
end structural;
PRORITY ENCODER
PROGRAM:
PROGRAM FOR OR2:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or2 is
Port (a: in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end or2;
architecture Behavioral of xorgate3 is
begin
y<= a or b;
end Behavioral;
PROGRAM FOR AND2:
entity and2 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end and2;
architecture Behavioral of andgate2 is
begin
y <= a and b;
end Behavioral;
PROGRAM FOR PRORITY ENCODER:
entity priorityencoder is
Port ( i0,i1,i2,i3 : in STD_LOGIC;
y0,y1,v : out STD_LOGIC);
end priorityencoder;
architecture structural of priorityencoder is
component OR2 is
Port ( a, b: in STD_LOGIC;
y : out STD_LOGIC);
end component;
component and2 is
Port ( a, b : in STD_LOGIC;
y: out STD_LOGIC);
end component;
component or4 is
Port ( a, b, c, d : in STD_LOGIC;
y: out STD_LOGIC);
end component;
signal s: std_logic;
begin
stage1:and2 port map (i1, not i2, s);
stage2:or2 port map (i2, i3, y0);
stage3:or2 port map(s, i3, y1);
stage4:or4 port map (i0, i1, i2, i3, v);
end structural;
8x1 MULTIPLEXER
Fig : 8x1 mux circuit
Expected waveforms
PROGRAM:
Program for and4:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and4 is
Port ( a,b,c,d : in STD_LOGIC;
y : out STD_LOGIC);
end and4;
architecture Behavioral of and4 is
begin
y <= (a and b and c and d);
end Behavioral;
Program for OR8:
entity or8 is
Port ( i : in STD_LOGIC_VECTOR (7 downto 0);
y : out STD_LOGIC);
end or8;
architecture Behavioral of or8 is
begin
y <= i(0) or i(1) or i(2) or i(3) or i(4) or i(5) or i(6) or i(7);
end Behavioral;
Program for multiplexer 8x1:
entity mux8_1 is
Port ( i : in STD_LOGIC_VECTOR (7 downto 0);
a,b,c, : in STD_LOGIC;
y : out STD_LOGIC);
end mux8_1;
architecture structural of mux8_1 is
component and4 is
Port ( a : in STD_LOGIC;
b,c,d : in STD_LOGIC;
y : out STD_LOGIC);
end component;
component OR8 is
Port ( i : in STD_LOGIC_VECTOR (7 downto 0);
y : out STD_LOGIC);
end component;
signal s: std_logic_vector(7 downto 0); begin
stage1 : and4 port map(i(0), not a, not b, not c, s(0));
stage2 : and4 port map(i(1), not a,not b, c, s(1));
stage3 : and4 port map(i(2), not a, b, not c, s(2));
stage4 : and4 port map(i(3), not a, b, c, s(3));
stage5 : and4 port map(i(4), a, not b, not c, s(4));
stage6 : and4 port map(i(5), a, not b, c, s(5));
stage7 : and4 port map(i(6), a, b, not c, s(6));
stage8 : and4 port map(i(7), a, b, c, s(7));
stage9 : or8 port map(s, y);
end structural;
1-bit COMPARATOR
Expected waveforms:
1-bit COMPARATOR PROGRAM:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PROGRAM FOR AND2:
entity and2 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end and2;
architecture Behavioral of and2 is
begin
y <= a and b;
end Behavioral;
PROGRAM FOR XNOR2:
entity xnor2 is
Port (a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end xnor2;
architecture Behavioral of xnor2 is
begin
y <= a xnor b;
end Behavioral;
PROGRAM FOR COMPARATOR:
entity comparator is
Port (a,b: in STD_LOGIC;
Aeb,agb,alb : out STD_LOGIC);
end comparator;
architecture structural of comparator is
component and2 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end component;
component xnor2 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end component;
begin
stage1: xnor2 port map(a, b, aeb);
stage2: and2 port map(a, (not b), agb);
stage3: and2 port map( (not a), b, alb);
end structural;
D FLIP FLOP
Fig : d flipflop
Expected waveforms
D FLIP FLOP PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
Port ( q : in STD_LOGIC;
d : in STD_LOGIC;
clk : in STD_LOGIC;
y : out STD_LOGIC);
end dff;
architecture Behavioral of dff is
begin
process(d,q)
begin
if clk='1' then
if (q='0' and d='0') then y <='0';
elsif(q='0' and d='1') then y <='1';
elsif(q='1' and d='0') then y <='0';
elsif(q='1' and d='1') then y <='1';
end if;
end if;
end process;
end Behavioral;
T FLIP FLOP
Fig : d flipflop
Expected waveforms
T FLIP FLOP PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tff is
Port ( q : in STD_LOGIC;
t : in STD_LOGIC;
clk : in STD_LOGIC;
y : out STD_LOGIC);
end tff;
architecture Behavioral of tff is
begin
process(t,q)
begin
if clk='1' then
if (q='0' and t='0') then y <='0';
elsif(q='0' and t='1') then y <='1';
elsif(q='1' and t='0') then y <='1';
elsif(q='1' and t='1') then y <='0';
end if;
end if;
end process;
end Behavioral;
S-R FLIP FLOP PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity srff is
Port ( q : in STD_LOGIC;
s,r : in STD_LOGIC;
clk : in STD_LOGIC;
y : out STD_LOGIC);
end srff;
architecture Behavioral of srff is
begin
process(s,r,q)
begin
if clk='1' then
if (s='0' and r='0') then y <=q;
elsif(s='0' and r='1') then y <='0';
elsif(s='1' and r='0') then y <='1';
elsif(s='1' and r='1') then y <='-';
end if;
end if;
end process;
end Behavioral;
J-K FLIP FLOP PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jkff is
Port ( q : in STD_LOGIC;
j,k : in STD_LOGIC;
clk : in STD_LOGIC;
y : out STD_LOGIC);
end jkff;
architecture Behavioral of jkff is
begin
process(t,q)
begin
if clk='1' then
if (j='0' and k='0') then y <=q;
elsif(j='0' and k='1') then y <='0';
elsif(j='1' and k='0') then y <='1';
elsif(j='1' and k='1') then y <= not q;
end if;
end if;
end process;
end Behavioral;
UP COUNTER
Fig : d flipflop
Expected waveforms
UP COUNTER PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity upcounter is
Port ( re : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end upcounter;
architecture Behavioral of upcounter is
signal s:std_logic_vector(3 downto 0):="0000";
begin
process(clk,re)
begin
if re='0' then
s <= "0000";
elsif clk'event and clk='1' then
s <= s + "0001";
end if;
q <= s;
end process;
end Behavioral;
DOWN COUNTER PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity upcounter is
Port ( re : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end upcounter;
architecture Behavioral of upcounter is
signal s:std_logic_vector(3 downto 0):="1111";
begin
process(clk,re)
begin
if re='0' then
s <= "1111";
elsif clk'event and clk='1' then
s <= s - "0001";
end if;
q <= s;
end process;
end Behavioral;
PARITY GENERATOR & CHECK
PARITY GENERATOR & CHECKPROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity paritychecker is
Port ( x0,x1,x2 : in STD_LOGIC;
epg,c : out STD_LOGIC);
end paritychecker;
architecture structural of paritychecker is
component xor3 is
Port ( a,b,c : in STD_LOGIC;
y : out STD_LOGIC);
end component;
component xor4 is
Port ( a,b,c,d : in STD_LOGIC;
y : out STD_LOGIC);
end component;
component and1 is
Port ( a : in STD_LOGIC;
o : out STD_LOGIC);
end component;
signal s: std_logic; begin
stage1:xor3 port map(x0,x1,x2,s);
stage2:xor4 port map(s,x0,x1,x2,c);
stage3:and1 port map(s,epg);
end structural;
SERIAL ADDER
Fig : serial adder
Expected waveforms
SERIAL ADDER PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity serialadder is
Port ( i : in STD_LOGIC_VECTOR (15 downto 0);
o : out STD_LOGIC_VECTOR (7 downto 0);
a_i, b_i ,c_i, c_o , s_o: out STD_LOGIC;
clk,load : in STD_LOGIC);
end serialadder;
architecture Behavioral of serialadder is
signal ina,inb,oreg:std_logic_vector(7 downto 0);
signal so,ci,co:std_logic;
begin //--------------------regina
process(clk)
begin
if clk'event and clk='1' then
if(load='1') then
ina<=i(15 downto 8);
else
ina<='0'&ina(7 downto 1);
end if;
end if;
end process;
end Behavioral;