VLSI DESIGN FLOW / TRENDS
Transcript of VLSI DESIGN FLOW / TRENDS
Slide 1
18 - 322 Lecture 26
VLSI DESIGN FLOW / TRENDS
Questions for :What kind of company are you?What product do you make?How do you design and fab product?
Three Design StrategiesFull-custom, Semi-custom, Structure ASICs, Programmable Logic
The Productivity Gap
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Semiconductor Companies
• Semiconductor Companies (with Fab)
Intel, National, Motorola, Lucent
• Fabless Semiconductor Companies: Sun, Xilinx, Altera
• Merchant Fabs: TSMC, UMC, Charter Semi, Seiko…
• The Product:
• How many do you make/sell?
• How many other companies make it?
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Product Life Cycle
[# waf./day]
Time
[%]
Time
Volume
Yield
Volume after testing
(b)
[#die/day]V(t)
Y0
N ( t )w
Y(t)
t1p t2
t1p t 2
[$]
Unit price P(t)
Time
(d)(a)
Revenue R(t)
t1p t2
Time
(e)[$/day]
(c)
Time
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Product Life Cycle
[# waf./day]
Time
[%]
Time
Volume
Yield
Volume after testing
(b)
[#die/day]V(t)
Y0
N ( t )w
Y(t)
t1p t2
t1p t 2
(a)
[$]
Unit price P(t)
Time
(d)
Revenue R(t)
t1p t2
Time
(e)[$/day]
(c)
Time
RV(t) =N ( t )Y(t) N (w= wch )a ,b ,
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Product Life Cycle
[# waf./day] Time
[%]
Time
Volume
Yield
Volume after testing[#die/day]
V(t)
Y0
N ( t )w
Y(t)
t1t1p t2
t1p t 2
(b)
[$]
Unit price P(t)
Time
(d)(a)
Revenue R(t)
t1p t2
Time
(e)[$/day]
(c)
TimeRV(t) =N ( t )Y(t) N (w= wch )a ,b ,
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Product Life Cycle
[#/day]Volume
t1p t
(a)
(d)Design Cost Rate[$/day]Time2
[$]Wafer Cost
Time
[$/day]Manufacturing Costs
t 1p t2
Time
(b)
(c)
Time
Cost Rate [$/day
Time
] (e)
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Product Life Cycle
[#/day]Volume
t1p t
(a)
(d)Design Cost Rate[$/day]Time2
[$]Wafer Cost
Time
[$/day]Manufacturing Costs
t 1p t2
Time
(b)
(c)
Time
Cost Rate [$/day
Time
] (e)
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Objective of VLSI Design
[$/day]
Time
Revenue Rate
Cost RateC(t)
R(t)
t1t1p
t2
⌡Profit = [R(t) - C(t)] dt
t1
t 2⌡
[$/day]
MAX { Profit [ Price (Performance),Cost,Time]}
Slide 9
Economic Reality of VLSI Production
Rising cost of manufacturing facilities;
Shrinking profit margins;
Shrinking product opportunity windows;
Two main objectives of any IC development cycle:
1. Highest possible manufacturing efficiency.
2. Shortest possible time-to-market
[$]
t
Price"war"
COSTS
REVENUE
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Volume Issues
[$]
t
COSTS
High Volume
[$]
t
COSTS
Low Volume
Minimize Design Time & Cost!Minimize Manufacturing Cost!
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Design Methodologies
• Full Custom
• Semi-custom
• Standard Cells
• Mask Programmable Gate Arrays (MPGA)
• Via Patterned Gate Arrays / Structured ASICs
• Programmable Logic
• Field Programmable Gate Arrays (FPGA)
• Complex Programmable Logic Devices (CPLD)
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Design Styles - Full Custom
PowerPC 750
Design Cost & Time: HIGH
Manufacturing Cost: LOW
Examples: microprocessors, RAMs
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Design Styles - Semi-Custom
Standard Cell: Place and Routepre-characterized cells
MPGA: Transistors already placed,only change metal masks
Design Cost & Time: Medium
Manufacturing Cost: Medium
Examples: PC chipsets, modems, cell phones ...
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Design Styles - Programmable Logic
FPGA: Pre-fabbed chip (high volume)configurable after fab
Design Cost & Time: LOW
Manufacturing Cost: HIGH
Examples: prototypes, network devices, telecom...
Slide 15
Standard Cell Design Process
Design Entry and Simulation» Schematics» Verilog / VHDL
Logic Synthesis» Input: Verilog/VHDL and Cell Library» Estimated Timing» Simulation
Timing Analysis» Determine worst-case clock speed
Formal Verification» Check equivalence of Gates and Specification
Design Hand-off
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Standard Cell Design ProcessFloorplanning
» Localize major functions of the chip» Consider global timing» Partition design
Placement» Find locations for all circuits» Consider detail timing» Assure proximity of critical nets
Global Routing» Resolve congestion» Localize nets» Give critical nets best paths
Detail Routing» Locate shortest paths» Create net geometry» Route critical nets first
Tape-out to manufacturing
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D Flip Flop: Standard Cell
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Design Styles - MPGAs
a.k.a.: Sea-of-gates, or just Gate Array
Chip cost ~ # of masks
VDD
PMOS
NMOS
GND
Four input NORPolysilicon
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Design Styles - MPGAs
IO
IO
IO
IO
IO IO IO IO IO IO
IO
IO
IO
IO
IO IO IO IO
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MPGAs: Gate Isolation
VDD
PMOS
NMOS
GND
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MPGAs: Isolation
VDD
PMOS
NMOS
GND
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MPGAs: Destiny
1980s: ASICs are 1 or 2 metal
Transistor masks dominate costs
MPGAs are significantly cheaper
1990s: ASICs move to 3, 4, 5, and 6 metal layers
Metal masks dominate costs
MPGAs are not nearly as cheap
Emergence of the FPGA
Rebirth in the “Structured ASIC”
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Manufacturing Costs
00.20.40.60.8
11.21.41.61.8
2
250 nm 180 nm 130 nm 90 nm 65 nm
Technology Generation
Mas
k C
osts
(in
mill
ion
$)
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Geometrical Regularity• Difficult to anticipate potential nanoscale failures • Increasing problems with printability
– Optical wavelengths approach critical distances– Resolution enhancement becomes challenging as we scale to 65nm and
below
130 nm lithography with OPC (courtesy of IBM)
130 nm lithography without OPC
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Structured ASIC Idea
• Make more of the design “regular”– Replicated across the die– Used by multiple customers
• Provide some mechanism for “customization”– A restricted set of metal masks– Restricted rules on the routing of metal– Vias and only vias (VPGA)
Slide 32
VPGA• Via Patterned Gate Array
– Regular logic blocks that are via configurable– Mask (through M2) and design amortization over multiple applications– Regular power distribution and clock like an FPGA– Carefully crafted regular geometrical patterns and redundant vias– Simplified physical design and verification – Predictable and testable– Ability to contain more of the
proprietary fab information
Slide 33
Design Styles - Programmable Logic
FPGA: Pre-fabbed chip (high volume)configurable after fab
Design Cost & Time: LOW
Manufacturing Cost: HIGH
Examples: prototypes, network devices, telecom...
Slide 34
Programmable Logic: FPGAs
LogicBlock
LogicBlock
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Programmable Logic: Logic Blocks
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Programmable Logic: LUTs
LUTs are little RAMs
INPUTS XOR000 0001 1010 1011 0100 1101 0110 0111 1
ConfigurationShift Register
InputsMUX
Output(XOR)
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Programmable Logic: Interconnect
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Another FPGA Architecture: FLEX 8k
LAB
IOE
LAB LAB
IOE
LAB LAB LAB
IOE IOE IOE
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FLEX 8k LAB
• Logic Array Block– Complete Interconnect To Row
Interconnect
4 LUT4 LUT4 LUT4 LUT4 LUT4 LUT4 LUT4 LUT
Loca
l Int
erco
nnec
t
8
4FromGlobal
24
To Column Interconnect
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FLEX 8k Place and Route
• Every LUT drives one row channel• Every LUT drives up to 2 column channels• Can’t connect ANY two LUTs
– Not every row channel visible– Small netlist changes -> Huge physical changes– Place so routable
• Predictable timing– Three Rules– Global Interconnect = Long Delay
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FPGA Design Flow
• Synthesis• Technology Mapping• Placement• Routing• Timing Analysis• Bitstream Generation and Download
What’s missing?(simulation)
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Design Styles -Standard Cell vs. FPGA
Warning: Your mileage WILL vary!10,000 Gate ChipStandard Cell FPGA
Design Cost $20,000 $8,000Days 50 20Cost/Day $400 $400
CAD Software $40,000 $1,000
Design for Test $2,000 $0Days 5 0Cost/Day $400
NREMasks $50,000 $0Test Progra $10,000 $0
Total Fixed Costs $122,000 $9,000
Part Cost $8 $39
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An “X” Graph
FPGA
ASICCost/part
Volume
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Implications of SIA Road Map: Design
Transistors/chip [k]1,000,000 10,000,000
1800 Staff Yrs.
800 Staff Yrs.100,000 1,000,000
10,000 100,000
1,000 10,000
1000
** *
Transistors/Staff-No.100
1092 94 96 98 2000 02 04 06 08 Year
SEMATECH
Slide 45
Implications of SIA Road Map: Design
Designer Productivity GapDesigner Productivity Gap•• Size of ICs growing faster than our ability to design themSize of ICs growing faster than our ability to design them•• Shortened product life cycles put greater timeShortened product life cycles put greater time--toto--market pressuremarket pressure
Companies that can address the Companies that can address the productivity gap will thrive.productivity gap will thrive.
Others will die.Others will die.
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Productivity Gap: Product Standardization
Inherent Conflict:• Build fewer products: reduce design cost, tune process for one product
• Differentiate products more
The Universal Compute Engine (?!?)• All product differentiation is “software”
• Candidates:
• Microproccesor ?
• FPGAs ?
• Hybrid ?
Slide 47
Software Differentiation
Observation: Software last longer than hardware
Case-in-point: Y2K!
Requirements for a Universal Compute Engine
a.) Execute old code, but do it faster than before
b.) Execute lots of different code: X86, IA64, JVM
Microprocessors have done (a.) really well.
Do this requirements eliminate the FPGA?
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Virtual Hardware
• Like Virtual Memory:– If you don’t have enough real memory– Time-multiplex the memory that you do have
• Observation:– Hardware design in FPGAs is specification of BITS– Move it into executing hardware when it it needed– Move it to memory when it is not needed
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Virtual Hardware: Scenario
Virtual JPEG Design(DCT, Quantization, Entropy)
Still Camera Video CameraLow cost,Low performance
High cost,High performance
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Pipelined Applications
• Example: FIR Filter
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x y
W2x + y
x y
W1x + y
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Time-Multiplexing on FPGAs
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tic Im
plem
enta
tion:
Reconfigure
Tim
e
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Reconfigure
Dyn
amic
Impl
emen
tatio
n:
FPGARAM
RAM
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Pipeline Reconfiguration
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Clock1
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FPGA
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Pipeline Reconfiguration
More hardware = More Throughput
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PipeRench Architecture
• Objective: Configure 1 stage per cycle1
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FPGA Fabric
Configuration Cache
On-chip ConfigurationWide Configuration Bus
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Productivity Gap: “Evolva-ware”
Human solution to complexity: divide and conquer• Standard cells, logical design, core-based design
Nature’s solution to complexity: natural selection• Mutate, select using criteria (survival)
• Can this be used to design chips?
001010010100101010100101001001001110010101101010100101101010100101010010100101111010101010101010110101
001010010100101010100101001001001110010101101010100101101010100101010010100101111010101010101010110101
001010010100101010100101001001001110010101101010100101101010100101010010100101111010101010101010110101
001010010100101010100101001001001110010101101010100101101010100101010010100101111010101010101010110101
001010010100101010100101001001001110010101101010100101101010100101010010100101111010101010101010110101
001010010100101010100101001001001110010101101010100101101010100101010010100101111010101010101010110101
FPGA
Mutate, crossover, selectConfigurations New Configurations
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A Curious Evolvable HW Experiment
• Goal: Get FPGA to detect 100 Hz input (light up LED)
• Progressively harder goals:– Light up the LED– Have the LED occasionally toggle– Have the LED on when fast frequency on input, off when
low frequency– Those designs that fail to meet the goal die and do not
reproduce
• After 400 generations, it worked!
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Mysterious Results
• Only one particular FPGA worked– Only at a particular temperature
• It was not clear how this worked… – Analog behavior, coupling between wires, etc– Not the traditional breakdown approach