Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 1

Vertex Readout

Joel Goldstein

PPd, RAL

4th ECFA/DESY LC Workshop

DAQ Session

1st April 2003

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 2

Outline

1. Vertex detector conceptual design

2. CP CCD technology option

3. Planned readout scheme

4. Other scenarios

(More demanding TESLA environment used throughout)

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 3

The Vertex Detector

• 5 layers (15-60mm)

• ~ 0.1% X0 per layer

• 20 m 20 m pixels

• 800 million channels

• Background rates force readout – 50 s for Layer 1– 250 s for Layer 2

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 4

Column Parallel CCDs

• Separate readout for each column

• Readout chip bump-bonded to CCD

• Chips contain:– Amplifiers

– 5-bit FADCs

– Filters

– Sparsification logic

– Local memory

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 5

Detector Parameters

LayerRadius

/mm

CCD

LW/mm

CCDs

/ladder

No. of

lad’sClock

/MHz

RO

Time/s

BkgdkHits

/train

1 15 10013 1 8 50 50 761

2 26 12522 2 8 25 250 367

3 37 12522 2 12 25 250 141

4 48 12522 2 16 25 250 28

5 60 12522 2 20 25 250 28

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 6

Ladder Readout

• Layer 1 read out 20 times per bunch train 50k z pixels

• Layer 2 read out 5 times per bunch train 31k z pixels

– 31 bits/4 bytes pixel address

CPR

6250 rows x 5 readout frames = 31250 z-address range(15 bits)

1100 f-addressrange

(11 bits)L2 - L5 CCDs

31 bits

+CPR

2500 rows x 20 readout frames= 50000 z-address range

(16 bits)

650 f-addressrange

(10 bits)L1 CCDs31 bits 31 bits

+-CPR

CPR31 bits

-

L2 - L5 CCDs

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 7

DAQ Plan

4.4 billion pixels 5 bits = a lot of data!

So,

1. Sparsify locally into clusters (22,…)

2. Store on chip

3. Readout during 200ms dead time

1.3 million hits = 20 Mbytes per bunch train

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 8

CCDoutputstage

CCDoutputstage

Bumpbond

Bumpbond

Comp CompPixel

thresh

Pipeline 2 x 2kernel

Pipelineto

adjacentkernel logic

toadjacent

kernel logic

d/dtd/dt

to otherreadout

channels

G

ADC

Gate

FIFO

Memory

64-column Multiplexer

CompClusterthresh

G

ADC

Gate

FIFOVerticaladdress

fromcol (n-2)

col 1 col (n-1) col n col 64

fromcol (n+1)

CCD

ReadoutChip

CCDoutputstage

CCDoutputstage

to otherreadout

channels

ERF ERFDetector

Level

DAQ

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 9

Front End Readout Chain

Dataformatting

De-serialiser

De-serialiser

De-serialiser

De-serialiser

De-serialiser

Data collection sequencing

Readout Control (FPGA)

L1

L2

L3

L4

L5

6.1 Mbytes (120 msec)

2.9 Mbytes (58 msec)

1.1 Mbytes (22 msec)

220 kbytes (4 msec)

220 kbytes (4 msec)

Pipeline ring busflex-circuitCPCCD

readoutchips

5 LVDS serial bitstreams(400 Mbit/s)

L5L4L3L2L1 Readout chip control

Secondarystorage

(10 Mbytes)

OpticalTx

Serialiser

Single opticalfibre (1 Gbit/s)

OpticalRx

Single opticalfibre (1 Gbit/s)

De-serialiser

Dataout

Controlin

Dataformatting

De-serialiser

De-serialiser

De-serialiser

De-serialiser

De-serialiser

Data collection sequencing

Readout Control (FPGA) DAQ Card

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 10

Other Scenarios

NLC:• Bkgd hits/train ~ 0.1TESLA• Readout in 8.3 ms dead time

TESLA 800:• 2bunches/train• Same CCD clock speed• More capacity in readout?

– Memory, datalinks etc.

– Still to be looked at

Active Pixels:• Similar schemes feasible

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 11

Summary

• 800 MPixel CP CCD vertex detector

• Clustering and sparsification performed on readout chip

• ~10 Mbytes per bunch train per end

• Single interface card per end, outside tracking volume

• Minimal external connections

– input control fibre, output data fibre, power

• Other technologies similar

• Testing of first CP CCDs and readout chips starting