Vertex Detector Overview and DSSD readout/trigger M. Hazumi (KEK)

miniDAQ workshop October 29 – 30, 2002 M. Hazumi

Vertex Detector Overview and DSSD readout/trigger

M. Hazumi (KEK)

• Overall Design Consideration• Silicon Strip Readout Scheme• Fast Trigger• Plan

Outline


Overall Design Consideration

• Time-dependent CP Violation– In physics beyond the SM (e.g. B0 ’Ks, Ks)– Time-dependent analyses for 1, 2

• Time dependence in rare decays

• Special time-dependence [e.g. sin(21+3)]

Present resolution is adequate for signal events. However,

Better resolution is required to separate signal from continuum

Physics Requirements

Better resolution is required for signal events.


z resolution function

• Resolution is improved by• narrower main Gaussian

• smaller 2nd Gaussian component (e.g. tail)

smaller beampipe radiusless material

robustness against fake hitssmall background occupancymore layers


Z r

Impact parameter resolution (SVD1.4)　

Sufficient to measure sin2phi1, but not for rare decays


SVD1.4

5-layer SVD (a la Inner Tracker taskforce)

Resolution with Rbp=1cm and Strip pitch = 50um

Meet the Super KEKB requirementFurther improvement possible by reducing material (expecially beampipe and the innermost pixel, as well as having a larger lever arm


Better Impact Parameter Resolution

• Smaller-radius beampipe Rbp = 1cm

• Good intrinsic resolution 50um or less

• Smaller amount of material need studies

½ of present resolution seems feasible.1/3 of present should be tried !


Occupancy guesstimation vs. R (= DSSD radius)

Occupancy vs. DSSD radius

1

10

100

1000

0 2 4 6 8

radius (cm)

occupancy (%)

VA1(Tp=1us)

VATA(Tp=0.5us)

Pipeline(150nswindow)

Trigger simulation study desirable

Pixel for R < 3cmPipeline for R < 10cm

Large ambiguity even with dedicated simulation.Need to take the safe side.


Rbp = 1cm2-layer Pixel3 or more DSSDsRcdc > 15cm

Configuration of SuperB VXD

15cm

Extrapolating present hit rate and requiring the hit rate being less than the present,Rcdc > 12cm is“probably no problem”.

DSSD w/Pipeline readout

CDC

Additional DSSD layers


Requirements on Silicon Strip Readout

• Good S/N (> 20)• Small Occupancy (< 5%)• Small Deadtime ( < 10usec/event )• Radiation Hardness (up to 40Mrad)• Fast Trigger Capability• External Noise Immunity (tolerance for CMN ~1000e-)• Readiness in 2006 (“Evolution” rather than “Revolution”)

Choice of readout chip is essential.


Readout chips for DSSDsExp chip process pipeline fasttrig principle

Belle VATA AMS 0.8um x o cnt. Shaping. AnalogueBaBar AtoM Honeywell o x Time-over-ThresholdCLEO FE/BE Honeywell x x on-hybrid ADC, DigitalZEUS Helix AMS 128cells x Analogue

(non-radhard)CDF II SVX4 IBM ? um 47cells x FE/BE architecture

double-corr. Sampling periodic reset, Digital

CMS APV25 IBM 0.25um 192cells x AnalogueATLAS ABCD? 132cells x BinaryLHCb SICA-VELO DMILL

BEETLE 0.25um 160cells ? Analogue (Belle FELIX(+TA) AMS0.35um O(100) o Analogue)


APV25 for CMS Silicon Tracker• Tp = 50nsec, 40MHz sampling• Pipeline depth = 192cells 4.8usec• 128ch/chip readout latency well below 10usec• Reasonable S/N

– 246e- + 36e-/pF ( + deconvolution effect)

Usage for “DC beam” (B factory) S/N degradation by ~12%


Deadtime-less pipeline

•Readout time = 1/20MHz x 128ch = 6.4us•No deadtime during readout (unless the address FIFO is full).•Also periodic reset is not necessary (continuous shaping).

192-cell ring buffer (4.8us)

address stored in 32-depth FIFOis skipped.

write pointer

read pointer

Trigger

32-depth FIFO(to store cell address)

(3 consecutive cells / event)


APV25 test setup in Vienna

APV HybridandAPV Hybrid+silicon detector

Repeater

APV sequencer

VME-I2C

VME-ADC

VMEPC

controlsoftware

clock/trig/reset/power

Clock

Analog Data

I2C

Contract-related issuesshould be solved to use APV25at Super KEKB.


K. Uchida


L1.5-like L1 with APV25

• SVD2 adopts L1.5 trigger• used as “abort” for other CDC/ACC/TOF/ECL/KLM …• work as “L1” for SVD

• L1.5-like L1 for all detector components as SuperB• A plausible solution• CDC trigger used as “L0” for SVD (latency should be less than 4us)• Cost ?

Proposal by Manfred Pernicka (Vienna)

APV25 ADC

20MHz (or 40MHz) 128ch 6.4us (= T0)

L1.5-likeL1 trigger

FPGACDC trigger

L1~2T0 2T0 +

Total latency dependson the choice ofthe chip

can be shorter


Real L1 trigger from VXD

• No “readily available” solution

• Chip modifications ?– APV25 with fast trigger– Felix + TA (“all IDEAS” solution)

• Pipelined VATA in other words

• Dedicated detector ?– Straw tube (high resistivity) for z information ?

Large amount of R&D may be required. Need to know if L1 from VXD is really needed (e.g. simulation studies).


Three issues

• Short bunch-crossing period at KEKB (2ns)– Essentially DC beam (collisions happen anytime)– 40MHz pipeline can be off-timing by 12.5ns; ¼ of the peakin

g time (Tp = 50ns) S/N degradation probably tolerable• Requirement for fast SVD trigger (L1)

– L1 group thinks it essential to have the fast SVD trg.– No available readout chip that has both pipeline readout and f

ast triggering capability.– L1.5-like L1 seems the plausible solution (other detector com

ponents need sufficient buffer length)• Contract

– It may not be so easy to use existing chips • Development of our own pipeline chips ?


Possible scenario for VTX readout

• Default option– hybrid pixel detector for the innermost layer (or two)

– DSSD with pipeline readout for other layers

– L1.5-like L1 trigger

• Backup for pixel– mini-strip DSSD with pipeline readout on Day 1

– real pixel detector for upgrade

• Option– TA-like fast trigger (need a pipelined VATA)


Schedule

• Oct. 26, 02 1st SuperB VTX meeting• late Nov.02 2nd SuperB VTX meeting• late Dec.02

or Jan.03 3rd SuperB VTX meeting• Feb.03 LCPAC report

• …. monthly meetings for progress reports ….

• Aug.03 or Sep.03 HL04 workshop LoI• Feb (?) 04 Official proposal to LCPAC


R&D items for Pixel: initial assignments

• Sim. study for Pixel requirements• Background study and IR design (Yamamoto)• TRACKERR study on thickness and pixel size (Trabelsi)• GEANT preparation (if necessary) (Hara)

• Hybrid pixel detector development• joint effort with HPK (e.g. floating pixel) (Hazumi)• Bump bonding (with HPK or else)• Thinning

• Monolithic pixel detector development (Palka)

• Pixel readout chip selection • gaining experience with ALICE pixel (Kawasaki, Tanaka)• Hawaii R&D beamtest ? (Varner)

• Cooling, mechanical structure (Rosen)

• Monitoring (Tsuboyama)


R&D items for DSSD: initial assignments

• pipeline readout chip• gaining experience with APV25 (Kawasaki) • Discussion with IDEAS (Hazumi)

• Backend electronics • Trigger

• L1.5-like L1 (Pernicka**)

• Detector configuration• Large-area detector

• floating strip design (Tsuboyama, Hazumi)

• Cooling, mechanical structure (Rosen)

• Monitoring (Tsuboyama)

** To be confirmed


Backup Slides


Hit rate (occupancy) guesstimation• SVD occupancy (now) = 3~5% (innermost)• Assume occupancy annual dose

– Annual dose estimated to be 7.3MRad at super KEKB (r=1cm beampipe, see EoI for detail)

• Assume DSSD with the same pitch but with the length scaled to be half

• For r=1cm beampipe, DSSD occupancy ~ 274% for an area of 50um x 2.7cm and Tp = 1usec (time window for noise ~ 3usec.)– Need pixel detectors

• To achieve 1% occupancy, pixel size of 50um x 100um is required. – Requirement relaxed for faster time window.


Inner Tracker Task Force (2000)

Rbp = 1cm5layer DSSDsVATA1 readoutFast trigger


Material Budget

LC VTX more ambitious design.Cf. NIM A473 (2001) 86

Thin CCD (0.12% X0)Beryllium substrate (0.09% X0) Goal : 4 4/(psin3/2theta) (um) !

SVD1.4 2.60% (X0)5layer 3.37% (X0)


Requirement on readout latency

Trigger Rate for 10^35cm^-2s^-1expect. design

Background 2kHz 5kHzPhysics 1kHz 1kHzDatasize 100kB 100kBL1 Data flow 300MB/s 600MB/sAt storage 150MB/s 225MB/s

~10usec/event for 5% deadtime @ 5kHz trigger rate

Rather difficult with present schemePipeline scheme is better.


Fast readout

• Column-parallel CCDs– Incread readout speed by two orders of magnitude

• Provide each column with its own output port

• Clocking the imaging region at 50MHz

– ~65Gpixels/s readout time of ~50us

– Beampipe radius = 10mm


Requirements on pixel

• Size ~ 50um x 100um for occupancy ~1%• Thickness < 300um to minimize Coulomb scat

tering• Rad hard up to 30MRad (for 4years operation)• S/N >= 20• CMN < 500e-• Fast readout


R&D on a fast CCD vertex detector(A. R. Gillman NIM A473 (2001)

86)• Demand for LC

• Present best = SLD VXD3– Res.(rphi) = 9 + 33/(p x sin3/2theta) [um]– Res.(rz) = 17+33/(p x sin3/2theta) [um]– Material : 0.4% X0/layer)– Beampipe radius = 24mm


Requirements for LC VXD

• SLD VXD3 LC VXD– Res.(rphi) = 4 + 4/(p x sin3/2theta) [um]– Res.(rz) = 4 + 4/(p x sin3/2theta) [um]– Material : 0.06% X0/layer)– Beampipe radius = 10mm


CLEO III FE/BE• FE (front-end chip)

– Preamp+shaper+gainstage– CR-RC shaper– Shaping time 0.7 ~ 3.0us– Baseline subtraction circuit– Similar to VA

• BE (back-end chip)– Based on SVX-2b back-end– 128 8-bit Wilkinson ADCs, comparators and F

IFO buffers


• Better impact parameter resolution– Smaller-radius beampipe Rbp = 1cm– Good intrinsic resolution 50um good enough– Optimized material budget Yamada-san will think about it.

• Reasonable hit rate (occupancy)– IR and mask design Simulation done with Rbp = 1cm– Higher CDC hit rate DSSD up to R = 15cm (2PXD + 4~5DSSD)

• Readout electronics ~ 10us/event for 5% deadtime at 5kHz – Fast readout for pixel Talk by Andrzej Bozek– Pipeline readout for strip APV25 etc. : optimization for DC beam ?

• Trigger capability– Fast (level 1) trigger ? ? : APV25 with fast trig, Felix+TA– Level 2 trigger Feasible (difficulty depends on required latency)

• Radiation hardness– Deep-submicron technology 0.25um OK up to 30Mrad

• Choice of sensors– Pixel (MAPS, hybrid, CCD) Talk by Andrzej Bozek– Large area DSSDs Technology already available

• Installation in 2006 Established technologies as much as possible

Overall Design Consideration (Summary)

Vertex Detector Overview and DSSD readout/trigger M. Hazumi (KEK)

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