Verilog Simulator - Silvaco...• IEEE-1364-2001 compliant Verilog simulator with Programming...

4
• IEEE-1364-2001 compliant Verilog simulator with Programming Language Interface (PLI) supports language extensions • Productive debugging environment with graphic data analyzer, trace mode, hierarchy explorer, and interactive source code editor • Embedded lint tool that can make comprehensive syntax, semantic and design rule checking with over 500 checking rules. Can check for simulation and synthesis mismatches, race condition, clock domain synchronization and more • Ensures comprehensive verification with integrated code coverage • Supports compliance testing for RTCA/DO-254, “Design Assurance Guidance for Airborne Electronic Hardware,” Appendix B • Silvaco’s strong encryption is available to protect valuable customer and third party intellectual property Silos is an easy-to-use IEEE-1364-2001 compliant Verilog simulator used by leading IC designers. An industry standard since 1986, its powerful interactive debugging features provide today’s most productive design environment for FPGA, PLD, ASIC and custom digital designs. Silos Verilog Simulator

Transcript of Verilog Simulator - Silvaco...• IEEE-1364-2001 compliant Verilog simulator with Programming...

Page 1: Verilog Simulator - Silvaco...• IEEE-1364-2001 compliant Verilog simulator with Programming Language Interface (PLI) supports language extensions • Productive debugging environment

• IEEE-1364-2001 compliant Verilog simulator with Programming Language Interface (PLI) supports language extensions

• Productive debugging environment with graphic data analyzer, trace mode, hierarchy explorer, and interactive source code editor

• Embedded lint tool that can make comprehensive syntax, semantic and design rule checking with over 500 checking rules. Can check for simulation and synthesis mismatches, race condition, clock domain synchronization and more

• Ensures comprehensive verifi cation with integrated code coverage

• Supports compliance testing for RTCA/DO-254, “Design Assurance Guidance for Airborne Electronic Hardware,” Appendix B

• Silvaco’s strong encryption is available to protect valuable customer and third party intellectual property

Silos is an easy-to-use IEEE-1364-2001 compliant Verilog simulator used by leading IC designers. An industry standard since 1986, its powerful interactive debugging features provide today’s most productive design environment for FPGA, PLD, ASIC and custom digital designs.

Silos

Verilog Simulator

Page 2: Verilog Simulator - Silvaco...• IEEE-1364-2001 compliant Verilog simulator with Programming Language Interface (PLI) supports language extensions • Productive debugging environment

• Easy-to-usegraphicuserinterfaceprovidesproductiveenvironmentfornovicesandexperts–SilosselectedbysevenpopularVerilogtextbooksandusedinthemajorityofuniversityVLSIdesigncourses

• HierarchyExploreroffersafamiliarviewofahierarchicaldesignwith“drag&drop”forrapidcaptureanddisplayofanyvariablesinthedesign

• SilosInteractiveEnvironmentenablesreal-timeaccessandanalysisofallexpressions,variables,modules, signals, vectors, and registers

• Consistentinteractivemethodsforsignalselection,settingtime-scale,busradix,statuswindow,timingmarker,bookmark,andbusdefinition

• InteractiveSourceCodeEditordisplayslinenumbersforstop,start,andbreakpoints,DataTipstoviewthevaluesofvariablesandexpressions,andcodecoverageinformation

Ease of Use

Functionality• IEEE1364CompliantVerilogwith2001Extensionsincludingthegeneratestatement

and wildcards

• Multi-levelHDLsimulatoratswitch,gate,andbehaviorallevels

• ComprehensiveProjectManagersavespreferences,settings,directories,andoptionsinafileforefficientmulti-projectsetup

• SaveAllenablesdesignerstoviewthecompletesimulationhistory

• SaveandRestoresavesthecompletestateofthesimulatortoafilethatcanbeusedtorestartsimulationatthepointofthesave

• IEEE1364ProgrammingLanguageInterface(PLI)enablesdesignersandFPGAvendorstocreateVerilogextensionsasdynamicallylinkedlibraries

AnyVerilogexpressioncanbeviewedasawaveformbydragginganddroppingtheexpressionintotheDataAnalyzer.

Data Analyzer uses the Trace Signal Window and the Source CodeWindowtotracethecauseofanunknownvalue.

Page 3: Verilog Simulator - Silvaco...• IEEE-1364-2001 compliant Verilog simulator with Programming Language Interface (PLI) supports language extensions • Productive debugging environment

Lint Capability

Productivity – Interactive Simulation Environment

• HighPerformancesimulationengineachievesfastsimulationresultsrivalingcompiledVerilogforinteractivedebuggingofdesignsuptoseveralhundredthousandgates(withnocompiletimes)

• Interactive,interpretedVerilogenvironmentprovidesasetofmulti-taskingutilitiestoeditHDLsource,setincrementalbreakpoints,steppingortimedsimulation,real-timeviewing,anderrordetection

• Multi-windowcustomizableDataAnalyzercontrolspanandzoom,timingmarkers,usinginteractive“drag&drop”capture,anddisplayforsignalsandexpressionsforanaloganddigitalwaveforms

• TraceModegraphicallytracesallfan-inconnectionstoanysignalthroughalllevelsofcircuithierarchyinstantly

• Watcheswindowdisplaysorforcesstatevaluesofspecifiedsignalsandvariableswhilesingle-stepping–allsetupthrough“drag&drop”fordesignerconvenience

• Checksformorethan500designrules

• Checksraceconditionsandclockdomainsynchronization

• Checksforsynthesizability,andreportspotentialsynthesisandsimulationmismatches

• Optimizesgateusagewithdetailedreportsofinferredregisters,latches,state-machinesandothersequentialelementsthatwillbesynthesizedintosynchronoushardware

• ExtractsFiniteStateMachines(FSM)andanalysesforredundantorunreachablestates

• Offersdesign-for-testabilitychecksforup-frontidentificationofun-testablecircuits

• Comprehensivereportfilteringsystemdeliverspreciseinformationtoisolateandfixproblem

DataTipsintheSourceWindowdisplayvalue,scope,andtimeofthehighlightedexpressionattheT1markerintheDataAnalyzer.

Analogwaveformscanbedisplayedineitherpiecewiselinearformator stepping format.

Page 4: Verilog Simulator - Silvaco...• IEEE-1364-2001 compliant Verilog simulator with Programming Language Interface (PLI) supports language extensions • Productive debugging environment

Silos Inputs/Outputs

Silos

Verilog Source

SDF Back Annotation

Code Coverage Reports

Waveforms

Log and Trace Files

IEEE 1364 PLIProgramming

Language Interface

Command Files

Verilog Libraries Lint Report

Support for FAA Standard DO254 Testing

• RTCA/DO-254,DESIGNASSURANCEGUIDANCEFORAIRBORNEELECTRONICHARDWAREisastandardrecognizedbytheFederalAviationAdministration(FAA)asameanstoensurethesafetyofelectronicairbornesystemsbyverifyingthedesignofcomplexelectronichardwareinairbornesystems

• TheSiloscodecoveragereportingfeaturesupportscompliancetestingforRTCA/DO-254“DesignAssuranceGuidanceforAirborneElectronicHardware,”forlevelsAandBasspecifiedtomeet“ElementalAnalysis”inAppendixB

• Silosgeneratescodecoveragereportsincluding“Line/StatementCoverage,”“Operator/ExpressionCoverage”and“BranchCoverage.”ReportscanbeexportedastextfilesandcanalsobeexaminedinteractivelyusingtheSilosgraphicaluserinterface(GUI).CodeCoveragedatafrommultipleindependent simulation runs can be merged into a single report

• Theusercanenableanddisablecoveragereportingforspecificlinesandblocksofbehavioralsourcecode.Spurioustime0eventsareautomaticallyeliminatedfromthecoverageresults

HEADQUARTERS

4701 Patrick Henry Drive, Bldg. 2

Santa Clara, CA 95054 USA

Phone: 408-567-1000

Fax: 408-496-6080

JAPAN [email protected]

EUROPE [email protected]

KOREA [email protected]

TAIWAN [email protected]

SINGAPORE [email protected]

CALIFORNIA [email protected]

408-567-1000

MASSACHUSETTS [email protected]

978-323-7901

TEXAS [email protected]

512-418-2929

WWW.SILVACO.COMRev.042513_23

https://www.facebook.com/pages/Silvaco/193512520767995
https://twitter.com/SilvacoSoftware
http://www.youtube.com/user/SilvacoUSA
www.silvaco.com

Verilog Hardware Description Language (Verilog HDL)

Verilog Hardware Description Language (Verilog HDL)

Verilog Hardware Description Language (Verilog HDL) · PDF fileVerilog HDL Edited by Chu Yu 4 Verilog HDL zHDL – Hardware Description Language A programming language that can describe

Verilog Hardware Description Language (Verilog HDL) · PDF fileVerilog HDL Edited by Chu Yu 4 Verilog HDL zHDL – Hardware Description Language A programming language that can describe

Verilog-to-C-Compiler: Simulator Generator · PDF fileCertified that the work contained in the thesis entitled “Verilog-to-C-Compiler: Simulator Generator ... Verilog or other HDL

Verilog-to-C-Compiler: Simulator Generator · PDF fileCertified that the work contained in the thesis entitled “Verilog-to-C-Compiler: Simulator Generator ... Verilog or other HDL

Fpga Programming Using Verilog Hdl Language

Fpga Programming Using Verilog Hdl Language

Silos – Verilog Simulator

Silos – Verilog Simulator

The Verilog Language

The Verilog Language

Verilog Hardware Description Language (Verilog HDL) · PDF fileVerilog HDL 2 Edited by Chu Yu Verilog HDL Brief history of Verilog HDL 1985: Verilog language and related simulator

Verilog Hardware Description Language (Verilog HDL) · PDF fileVerilog HDL 2 Edited by Chu Yu Verilog HDL Brief history of Verilog HDL 1985: Verilog language and related simulator

The Verilog Language - robo-tronix.weebly.com

The Verilog Language - robo-tronix.weebly.com

Verilog Simulator

Verilog Simulator

Verilog Fundamentals · Verilog Fundamentals. VERILOG FUNDAMENTALS ... Verilog is a HARDWARE DESCRIPTION LANGUAGE. ... Level 2 : Design a digital system using Verilog . (weightage

Verilog Fundamentals · Verilog Fundamentals. VERILOG FUNDAMENTALS ... Verilog is a HARDWARE DESCRIPTION LANGUAGE. ... Level 2 : Design a digital system using Verilog . (weightage

Using the ModelSim-Intel FPGA Simulator with Verilog ......USING THE MODELSIM-INTEL FPGA SIMULATOR WITH VERILOG TESTBENCHES For Quartus® Prime 18.0 2Getting Started The ModelSim Simulator

Using the ModelSim-Intel FPGA Simulator with Verilog ......USING THE MODELSIM-INTEL FPGA SIMULATOR WITH VERILOG TESTBENCHES For Quartus® Prime 18.0 2Getting Started The ModelSim Simulator

Cadence® NC-Verilog® Simulator Helpread.pudn.com/downloads311/ebook/1379832/ncvlog.pdf · 2004. 1. 19. · NC-Verilog Simulator Help September 2003 4 Product Version 5.1 Related

Cadence® NC-Verilog® Simulator Helpread.pudn.com/downloads311/ebook/1379832/ncvlog.pdf · 2004. 1. 19. · NC-Verilog Simulator Help September 2003 4 Product Version 5.1 Related

Silos – Verilog Simulator - Silvaco · SILOS – Verilog Simulator Starting Silos 8 “Contents” will display the contents for the Silos User’s Manual. The “New Features”

Silos – Verilog Simulator - Silvaco · SILOS – Verilog Simulator Starting Silos 8 “Contents” will display the contents for the Silos User’s Manual. The “New Features”

05-Verilog Language Concepts - Amazon S3 · PDF file2 CSE 467 Verilog Digital System Design 3 Verilog Language Concepts Module Basics (cont.) Arrays Verilog operators Verilog data

05-Verilog Language Concepts - Amazon S3 · PDF file2 CSE 467 Verilog Digital System Design 3 Verilog Language Concepts Module Basics (cont.) Arrays Verilog operators Verilog data

Designing of cordic processor in verilog using xilinx ise simulator

Designing of cordic processor in verilog using xilinx ise simulator

Outline The Verilog Language - UAH - Engineeringmilenka/cpe527-07F/lectures/verilog_tut.pdf · The Verilog Language ... Verilog programs built from modules Each module has an interface

Outline The Verilog Language - UAH - Engineeringmilenka/cpe527-07F/lectures/verilog_tut.pdf · The Verilog Language ... Verilog programs built from modules Each module has an interface

1 Verilog Digital System Design Z. Navabi, 2006 Verilog Language Concepts.

1 Verilog Digital System Design Z. Navabi, 2006 Verilog Language Concepts.

Verilog Hardware Description Language (HDL)

Verilog Hardware Description Language (HDL)

05-Verilog Language Concepts

05-Verilog Language Concepts

The Verilog Hardware Description Language

The Verilog Hardware Description Language