VARIUS-TC: A Modular Architecture- Level Model of...

LTAI

VARIUS-TC: A Modular Architecture-Level Model of Parametric Variation

for Thin-Channel Switches

S. Karen Khatamifard, Michael Resch, Nam Sung Kim†, Ulya R. Karpuzcu

University of Minnesota †University of Illinois

{khata006, resc0059, ukarpuzc}@umn.edu [email protected]

10/5/2016

ICCD’16

• Manufacturing process becomes less controllable under aggressive scaling.

Motivation

2VARIUS-TC: A Modular Architecture-Level Model of

Parametric Variation for Thin-Channel Switches10/5/2016

ICCD’16

• Manufacturing process becomes less controllable under aggressive scaling.Deviation of device parameters from nominal becomes more likely.

Motivation



ICCD’16


Performance and power of manufactured hardware become unpredictable.

Motivation



ICCD’16



We need system-level models of variation at early stages of the design.

Motivation



ICCD’16




• Contribution: VARIUS-TC

Motivation



ICCD’16




• Contribution: VARIUS-TCModeling process variation in emerging devices at architecture-level.

Motivation



ICCD’16

Thin Channel (TC) devices



[K. Ahmed, and K. Schuegraf. "Transistor wars." IEEE Spectrum48.11 (2011): 50-66.].

ICCD’16





Traditional Planar CMOS

ICCD’16





Channel Thickness

Traditional Planar CMOS

ICCD’16





Channel Thickness

Traditional Planar CMOS SOI

ICCD’16





Channel Thickness

Traditional Planar CMOS SOI FinFET

ICCD’16

VARIUS-TC: Overview



ICCD’16

VARIUS-TC: Overview



VARIUS-TC

ICCD’16

VARIUS-TC: Overview



VARIUS-TCLUT

DEVICE

MODULE

ICCD’16

VARIUS-TC: Overview



VARIUS-TCLUT

DEVICE

MODULE

CIRCUIT

MODULE

ICCD’16

VARIUS-TC: Overview



VARIUS-TCLUT

DEVICE

MODULE

CIRCUIT

MODULE

ARCHITECTURE

MODULE

1/f

1 / 𝐟𝐍𝐎𝐌

Path delay distribution

ICCD’16

VARIUS-TC: Overview



VARIUS-TCfloorplan

LUT

DEVICE

MODULE

CIRCUIT

MODULE

ARCHITECTURE

MODULE

1/f



ICCD’16

VARIUS-TC: Overview



VARIUS-TCfloorplan

LUT

DEVICE

MODULE

CIRCUIT

MODULE

ARCHITECTURE

MODULE

1/f



device parameters

ICCD’16

VARIUS-TC: Overview



VARIUS-TCfloorplan

LUT

DEVICE

MODULE

CIRCUIT

MODULE

ARCHITECTURE

MODULE

1/f



device parameters

1/f

𝟏

𝐟𝐍𝐎𝐌

𝟏

𝐟𝐕𝐀𝐑


ICCD’16

VARIUS-TC: Overview



VARIUS-TCfloorplan

LUT

DEVICE

MODULE

CIRCUIT

MODULE

ARCHITECTURE

MODULE

1/f



device parameters

1/f

𝟏

𝐟𝐍𝐎𝐌

𝟏

𝐟𝐕𝐀𝐑


# Memory Blocks

VMIN

ICCD’16

Hierarchical Variation Modeling



Systematic variation

ICCD’16





• Spatial correlation

ICCD’16





• Spatial correlation• Grid granularity

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• Spatial correlation• Grid granularity

Random variation

• Independent• Device granularity

+

ICCD’16

VARIUS-TC: Overview



VARIUS-TCfloorplan

LUT

DEVICE

MODULE

CIRCUIT

MODULE

ARCHITECTURE

MODULE

1/f



device parameters

1/f

𝟏

𝐟𝐍𝐎𝐌

𝟏

𝐟𝐕𝐀𝐑


# Memory Blocks

VMIN

ICCD’16

Look-Up Table



ICCD’16

LUTOutput

Look-Up Table



VoltagesTechnology Parameters

Temperature Current

Input

ICCD’16

LUTOutput

Look-Up Table



Voltages


Temperature Current

Input

ICCD’16

LUTOutput

Look-Up Table



Temperature

Voltages


Temperature Current

Input

ICCD’16

LUTOutput

Look-Up Table



Temperature

Technology Parameters

Voltages


Temperature Current

Input

ICCD’16

LUT

Look-Up Table



Temperature


Voltages

Current


Temperature Current

Input Output

ICCD’16

LUT

• LUT vs. closed-form formula:

Look-Up Table



Temperature


Voltages

Current


Temperature Current

Input Output

ICCD’16

LUT

• LUT vs. closed-form formula:• Modularity eases experimentation with different designs (e.g., SOI variants)

Look-Up Table



Temperature


Voltages

Current


Temperature Current

Input Output

ICCD’16

LUT

• LUT vs. closed-form formula:• Modularity eases experimentation with different designs (e.g., SOI variants)

• Robust closed-form formula may not always be available for emerging switches

Look-Up Table



Temperature


Voltages

Current


Temperature Current

Input Output

ICCD’16

VARIUS-TC: Overview



VARIUS-TCfloorplan

LUT

DEVICE

MODULE

CIRCUIT

MODULE

ARCHITECTURE

MODULE

1/f



device parameters

1/f

𝟏

𝐟𝐍𝐎𝐌

𝟏

𝐟𝐕𝐀𝐑


# Memory Blocks

VMIN

ICCD’16

Logic Timing Model



ICCD’16

pd

f

τ

Logic Timing Model



ICCD’16

pd

f

τ

Probability of a path with τ= τi being exercised

Logic Timing Model



τi

ICCD’16

pd

f

τ

Logic Timing Model



ICCD’16

pd

f

τ

Logic Timing Model



τNOM

ICCD’16

pd

f

τ

Logic Timing Model



τMINτNOM

ICCD’16

pd

f

τ

Logic Timing Model



τMINτNOM

Safe operating point

ICCD’16

pd

f

τ

Logic Timing Model



τMINτNOM


fMAX=1/τMIN

ICCD’16

pd

f

τ

Logic Timing Model



τMINτNOM

Error probability if

clocked at τNOM


fMAX=1/τMIN

ICCD’16

VARIUS-TC: Overview



VARIUS-TCfloorplan

LUT

DEVICE

MODULE

CIRCUIT

MODULE

ARCHITECTURE

MODULE

1/f



device parameters

1/f

𝟏

𝐟𝐍𝐎𝐌

𝟏

𝐟𝐕𝐀𝐑


# Memory Blocks

VMIN

ICCD’16

Memory Model



ICCD’16

• Supports 6T and 8T memory cell

Memory Model



ICCD’16


• Timing errors• Write timing

• Read timing

Memory Model



ICCD’16


• Timing errors• Write timing

• Read timing

• Stability errors• Hold error

• Write Stability

Memory Model



ICCD’16

Hold Error



ICCD’16

Hold Error



• The cell is not accessed.

ICCD’16

Hold Error




• Node VL looses its state.

ICCD’16

Hold Error




• Node VL looses its state.• Excessive leakage

ICCD’16

Hold Error




• Node VL looses its state.• Excessive leakage

VARIUS-TC

• Minimum Vdd (VMIN) to exclude state loss

ICCD’16

Evaluation Setup



ICCD’16

Evaluation Setup



• Device parameters• PTM, FinFET, 16nm

ICCD’16

Evaluation Setup




• Parametric sweep• LFin, TFin, φg

ICCD’16

Evaluation Setup





• 3 levels of variation• low, medium, high

ICCD’16

Evaluation Setup






• Many-core system• 16 tiles

ICCD’16

Evaluation Setup






• Many-core system• 16 tiles

• 4 core per tile

• Private L1, Shared L2

ICCD’16

Impact on Logic Timing



ICCD’16




Planar CMOS

ICCD’16




FinFET

Planar CMOS

ICCD’16




ICCD’16




more variation

ICCD’16




more variation

PV can still cause significant performance loss.

ICCD’16

Impact on VMIN



ICCD’16

Impact on VMIN



more variation

ICCD’16

Impact on VMIN



more variation

PV can still increase the minimum operating voltage significantly.

ICCD’16

Example Use Case



ICCD’16

• Reducing operating voltage reduces power consumption.

Example Use Case



ICCD’16

• Reducing operating voltage reduces power consumption. Frequency reduces, too.

Example Use Case



ICCD’16


Example Use Case



Throughput ∝ Ncores × fcores

ICCD’16


• Process Variation …

Example Use Case




ICCD’16



Example Use Case




VNOM

ICCD’16



Example Use Case




VNOM

VMIN

ICCD’16



Example Use Case




ICCD’16


• Process Variation …• If > 2x area increase is not

affordable…

Example Use Case




ICCD’16



affordable…

Example Use Case




0.5V

ICCD’16



affordable…

Example Use Case




0.5V 0.6V

ICCD’16

Related Work



ICCD’16

• VARIUS-NTV is tailored for planar CMOS only.

Related Work



ICCD’16


• FinCANON and McPAT-PVT are architecture-level FinFET-based models.

Related Work



ICCD’16


• FinCANON and McPAT-PVT are architecture-level FinFET-based models.• Modular

Related Work



ICCD’16



• TCAD-based device-level simulations

Related Work



ICCD’16




• VARIUS-TC’s strength

Related Work



ICCD’16




• VARIUS-TC’s strength• Probabilistic model to analyze processor logic and error modes of memory

Related Work



ICCD’16

Conclusion



ICCD’16

• VARIUS-TC

Conclusion



ICCD’16

• VARIUS-TC• Models process variation in emerging devices at architecture-level.

Conclusion



ICCD’16


• VARIUS-TC facilities

Conclusion



ICCD’16


• VARIUS-TC facilities• Extraction of a safe operating frequency and voltage

Conclusion



ICCD’16



• Generation of critical path delay, power, and VMIN distributions

Conclusion



ICCD’16




• Calculation of error probabilities for

Conclusion



ICCD’16





• logic (timing)

Conclusion



ICCD’16





• logic (timing)

• memory (timing and stability) error modes

Conclusion



ICCD’16





• logic (timing)


• Design space exploration

Conclusion



ICCD’16





• logic (timing)


• Design space exploration

• Modularity eases experimentation with different designs (e.g., SOI variants)

Conclusion



LTAI

VARIUS-TC: A Modular Architecture-Level Model of Parametric Variation

for Thin-Channel Switches

S. Karen Khatamifard, Michael Resch, Nam Sung Kim†, Ulya R. Karpuzcu

University of Minnesota †University of Illinois

{khatami, resc0059, ukarpuzc}@umn.edu {nskim}@illinois.edu

10/5/2016

http://altai.ece.umn.edu/varius

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