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Transcript of Unversity of Microchip
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©2005 Microchip Technology Incorporated. All Rights Reserved.©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 1
11002 GS2
Getting Started withPIC® MCU Mid-Range
A r c h i t e c t u r e , I n s t r u c t i o n Se t a n d A s s em b l y L a n g u a g e Pr o g ram m in g
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 2
Class ObjectiveWhen you finish this class you will:
− Understand the basics of the innerworkings of a PIC16
− Understand most instructions− Understand memory organization
− Understand how to write simpleprograms
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 3
AgendaO Architecture Basics
O Instruction Set OverviewO Memory Organization and
Addressing ModesO Special Features
O
Hands-on Exercises
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 4
ArchitectureO The high performance of the PIC®
microcontroller can be attributed to the
following architectural features:− Harvard Architecture
− Instruction Pipelining
− Large Register File
− Single Cycle Instructions
− Single Word Instructions
− Long Word Instructions
− Reduced Instruction Set
− Orthogonal Instruction Set
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 5
Harvard ArchitectureO Von Neumann
Architecture:
− Fetches instructions anddata from a single memoryspace
− Limits operating bandwidth
O Harvard Architecture:
− Uses two separate memoryspaces for program
instructions and data− Improved operating
bandwidth
− Allows for different buswidths
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 6
Instruction PipeliningO Instruction fetch is overlapped with execution of previously
fetched instruction
call SUB1
addwf REG2
movf PORTB,w
return
movf PORTC,w
return
SUB1
SUB2
movlw 0x05 MAIN
movwf REG1
1
2
3
4
51
52
53
54
Example ProgramFetch Execute
T0
Flush
T1 T2 T3 T4 T5
Instruction Cycles
T6
Fetch Execute
Fetch Execute
Fetch
Fetch Execute
Fetch Execute
Fetch Flush
Fetch
T7
Time to execute normal instruction
Time to execute call
instruction includespipeline flush
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 7
Instruction Pipelining
call SUB1
addwf REG2
movf PORTB,w
return
movf PORTC,w
return
SUB1
SUB2
movlw 0x05 MAIN
movwf REG1
1
2
3
4
51
52
53
54
Example ProgramFetch
T0
Instruction Cycles
movlw 0x05 -
Pre-Fetched Instruction Executing Instruction
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 8
Instruction Pipelining
call SUB1
addwf REG2
movf PORTB,w
return
movf PORTC,w
return
SUB1
SUB2
movlw 0x05 MAIN
movwf REG1
1
2
3
4
51
52
53
54
Example ProgramFetch Execute
T0 T1
Instruction Cycles
Fetch
movwf REG1 movlw 0x05
Pre-Fetched Instruction Executing Instruction
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 9
Instruction Pipelining
call SUB1
addwf REG2
movf PORTB,w
return
movf PORTC,w
return
SUB1
SUB2
movlw 0x05 MAIN
movwf REG1
1
2
3
4
51
52
53
54
Example ProgramFetch Execute
T0 T1 T2
Instruction Cycles
Fetch Execute
Fetch
call SUB1 movwf REG1
Pre-Fetched Instruction Executing Instruction
Time to execute normal instruction
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 10
Instruction Pipelining
call SUB1
addwf REG2
movf PORTB,w
return
movf PORTC,w
return
SUB1
SUB2
movlw 0x05 MAIN
movwf REG1
1
2
3
4
51
52
53
54
Example ProgramFetch Execute
T0 T1 T2 T3
Instruction Cycles
Fetch Execute
Fetch Execute
Fetch
addwf REG2 call SUB1
Pre-Fetched Instruction Executing Instruction
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 11
Instruction Pipelining
call SUB1
addwf REG2
movf PORTB,wreturn
movf PORTC,w
return
SUB1
SUB2
movlw 0x05 MAIN
movwf REG1
1
2
3
4
5152
53
54
Example ProgramFetch Execute
T0
Flush
T1 T2 T3 T4
Instruction Cycles
Fetch Execute
Fetch Execute
Fetch
Fetch
movf PORTB,w call SUB1
Pre-Fetched Instruction Executing Instruction
Time to execute call
instruction includespipeline flush
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 12
Instruction Pipelining
call SUB1
addwf REG2
movf PORTB,wreturn
movf PORTC,w
return
SUB1
SUB2
movlw 0x05 MAIN
movwf REG1
1
2
3
4
5152
53
54
Example ProgramFetch Execute
T0
Flush
T1 T2 T3 T4 T5
Instruction Cycles
Fetch Execute
Fetch Execute
Fetch
Fetch Execute
Fetch
return movf PORTB,w
Pre-Fetched Instruction Executing Instruction
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 13
Instruction Pipelining
call SUB1
addwf REG2
movf PORTB,wreturn
movf PORTC,w
return
SUB1
SUB2
movlw 0x05 MAIN
movwf REG1
1
2
3
4
5152
53
54
Example ProgramFetch Execute
T0
Flush
T1 T2 T3 T4 T5
Instruction Cycles
T6
Fetch Execute
Fetch Execute
Fetch
Fetch Execute
Fetch Execute
Fetch
movf PORTC,w return
Pre-Fetched Instruction Executing Instruction
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 14
Instruction Pipelining
call SUB1
addwf REG2
movf PORTB,wreturn
movf PORTC,w
return
SUB1
SUB2
movlw 0x05 MAIN
movwf REG1
1
2
3
4
5152
53
54
Example ProgramFetch Execute
T0
Flush
T1 T2 T3 T4 T5
Instruction Cycles
T6
Fetch Execute
Fetch Execute
Fetch
Fetch Execute
Fetch Execute
Fetch Flush
Fetch
T7
addwf REG2 return
Pre-Fetched Instruction Executing Instruction
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 15
Long Word Instruction8-bit Program Memory
14-bit Program Memory
11 00 00 00 00 11 11 00
kk kk kk kk kk kk kk kk
11 11 00 00 00 00 kk kk kk kk kk kk kk kk
8-bit Instruct ion on typical 8-bit MCU
Example: Freescale ‘Load Accumulator A’:
•2 Program Memory Locations
•2 Instruction Cycles to Execute
14-bit Instruction on PIC16 8-bit MCU
Example: ‘Move Literal to Working Register’
•1 Program Memory Location
•1 Instruction Cycle to Execute
O
LimitsBandwidth
O IncreasesMemory SizeRequirements
O Separate busses allow different widths
O 2k x 14 is roughly equivalent to 4k x 8
ldaa #k
movlw k
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 16
Register File Concept
D a t a
B u s
D a t a
B u s
d
OpcodeOpcode dd AddressAddressDecoded Instruction
from Program
Memory:
Ar ithmetic/Logic
Function to be Performed Result
Destination
Address of Second
Source Operand
O Register File Concept:
All of data memory is
part of the register
file, so any location in
data memory may beoperated on directly
O All peripherals are
mapped into data
memory as a series of
registersO Orthogonal
Instruction Set: ALL
instructions can
operate on ANY data
memory locationO The Long Word
Instruction format
allows a directly
addressable register
file
w f
w f
ALU
WW
Data Memory
(Register File)
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 17
Instruction Set Overview
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 18
Instruction Set Overview
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 19
Instruction Set Overview
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 20
PIC16 Instruction SetByte Oriented OperationsByte Oriented Operations Bit Oriented OperationsBit Oriented Operations
addwf f,daddwf f,d
andwf f,dandwf f,d
clrf f clrf f
clrw -clrw -
comf f,dcomf f,d
decf f,ddecf f,d
decfsz f,ddecfsz f,d
incf f,dincf f,d
incfsz f,dincfsz f,d
iorwf f,diorwf f,d
movf f,dmovf f,d
movwf f movwf f
nop -nop -
rlf f,drlf f,d
rrf f,drrf f,d
subwf f,dsubwf f,d
swapf f,dswapf f,d
xorwf f,dxorwf f,d
Add W and f Add W and f
AND W with f AND W with f
Clear f Clear f
Clear WClear W
Complement f Complement f
Decrement f Decrement f
Decrement f, Skip if 0Decrement f, Skip if 0
Increment f Increment f
Increment f, Skip if 0Increment f, Skip if 0
Inclusive OR W with f Inclusive OR W with f
Move f Move f
Move W to f Move W to f
No OperationNo Operation
Rotate Left f through CarryRotate Left f through Carry
Rotate Right f through CarryRotate Right f through Carry
Subtract W from f Subtract W from f
Swap nibbles in f Swap nibbles in f
Exclusive OR W with f Exclusive OR W with f
bcf f,bbcf f,b
bsf f,bbsf f,b
btfsc f,bbtfsc f,b
btfss f,bbtfss f,b
Bit Clear f Bit Clear f
Bit Set f Bit Set f
Bit Test f, Skip if ClearBit Test f, Skip if Clear
Bit Test f, Skip if SetBit Test f, Skip if Set
Literal and Control OperationsLiteral and Control Operations
addlw kaddlw k
andlw kandlw k
call kcall k
clrwdt -clrwdt -
goto kgoto k
iorlw kiorlw k
movlw kmovlw k
retfie -retfie -
retlw kretlw k
return -return -
sleep -sleep -
sublw ksublw k
xorlw kxorlw k
Add literal and WAdd literal and W
AND literal with WAND literal with W
Call subroutineCall subroutine
Clear Watchdog TimerClear Watchdog Timer
Go to addressGo to address
Inclusive OR literal with WInclusive OR literal with W
Move literal to WMove literal to W
Return from interruptReturn from interrupt
Return with literal in WReturn with literal in W
Return from SubroutineReturn from Subroutine
Go into standby modeGo into standby mode
Subtract W from literalSubtract W from literal
Exclusive OR literal with WExclusive OR literal with W
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 21
PIC16 Visual Interpreter
ADDLW 0x0A Execute
Register File Address
d
FFFFFFW Register
FFFFFFFFFFFFFFFFFF
181818FFFFFFFFFFFF
FFFFFFFFFFFFFFFFFF
FFFFFF
00h
01h
02h
03h04h
05h
06h
07h08h
09h
0Ah
0Bh
w f
w f
ALU
111 00 000Z DC C
STATUS
Data
Bus
Reset
Hex
Dec
Bin
Literal Data fromInstruction Word
,,
012
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 22
Data Memory Organization
Accesses
70h – 7Fh
Accesses
70h – 7Fh Accesses
70h – 7Fh
Accesses
70h – 7Fh Accesses
70h – 7Fh
Accesses
70h – 7Fh
Bank 0 Bank 1 Bank 2 Bank 3
PIC16F876/877 Register File Map
368 Bytes of General Purpose RAM Plus Special Function Registers
000h
01Fh
020h
07Fh
080h
09Fh
0A0h
0FFh
100h
110h
17Fh
180h
190h
1FFh
0EFh 16Fh 1EFh
10Fh 18Fh
128 Bytes
SFR SFR SFR SFR
GPR
96 Bytes
GPR
80 Bytes
GPR
96 Bytes
GPR
96 Bytes
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 23
Data Memory Organization
INDFINDF
TMR0TMR0
PCLPCL
STATUSSTATUS
FSRFSR
PORTAPORTA
PORTBPORTB
PORTCPORTC
PORTDPORTD
PORTEPORTE
PCLATHPCLATH
INTCONINTCON
INDFINDF
OPTION_REGOPTION_REG
PCLPCL
STATUSSTATUS
FSRFSR
TRISATRISA
TRISBTRISB
TRISCTRISC
TRISDTRISD
TRISETRISE
PCLATHPCLATH
INTCONINTCON
INDFINDF
TMR0TMR0
PCLPCL
STATUSSTATUS
FSRFSR
PORTBPORTB
PCLATHPCLATH
INTCONINTCON
INDFINDF
OPTION_REGOPTION_REG
PCLPCL
STATUSSTATUS
FSRFSR
TRISBTRISB
PCLATHPCLATH
INTCONINTCON
PIR1PIR1 PIE1PIE1 EEDATAEEDATA EECON1EECON1
PIR2PIR2 PIE2PIE2 EEADREEADR EECON2EECON2
Bank 0 Bank 1 Bank 2 Bank 3
000
001
002
003
004
005
006
007
008
009
00A
00B
00C
00D
080
081
082
083
084
085
086
087
088
089
08A
08B
08C
08D
100
101
102
103
104
105
106
107
108
109
10A
10B
10C
10D
180
181
182
183
184
185
186
187
188
189
18A
18B
18C
18D
Device Specific Registers
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 24
STATUS Register
IRPIRP RP1RP1 RP0RP0 TOTO PDPD ZZ DCDC CC
bit 7 bit 0
IRP: Register Bank Select (used for Indirect addressing)0 = Bank 0, 1 1 = Bank 2, 3
RP1:RP0: Register Bank Select Bits (used for direct addressing)00 = Bank 0, 01 = Bank 1, 10 = Bank 2, 11 = Bank 3
TO: Time-out bit0 = A WDT time-out occurred
PD: Power-down bit0 = SLEEP instruction executed
Z: Zero bit1 = Result of arithmetic operation is zero
DC: Digit cary / borrow bit1 = Carry out of 4th low order bit occurred / No borrow occurred
C: Carry / borrow bit1 = Carry out of MSb occurred / No borrow occurred
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 25
PIC16 Addressing Modes
O Data Memory Access:
− Direct addwf <dat a_addr ess>, <d>
− Indirect addwf I NDF, <d>
− Immediate (Literal) movl w <const ant >
O Program Memory Access:
− Absolute got o <pr ogr am_addr ess>
− Relative addwf PCL, f
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 26
Register Direct Addressing
FFFF
FFFF
FFFF1818
FFFF
FFFF
FFFF
FFFF
FFFF1C1C
FFFF
FFFF
00h
01h
02h03h
04h
05h
7Ah7Bh
7Ch
7Dh
7Eh
7Fh
RP1
Bank 1 Bank 2 Bank 3
00 00 0x1830x18300
2-bits from
STATUS Register 7-bits Encoded in Instruction
9-bit Effective Address
(Use this when coding)
Bank 0
RP0 ‘f’ Operand
FFFFFFFF
FFFF
FFFFFFFF
FFFF
FFFF
FFFF
FFFF
FFFFFFFF
FFFF
FFFF
FFFF
FFFF
FFFFFFFF
FFFF
FFFF
FFFF
FFFF
00 00 00 00 00 00
Register File Address Bus A
d d r e s s
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 27
FFFFFF
FFFFFF
FFFFFF
383838
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
Register Direct Addressing
80h : INDF
81h : OPTION
82h : PCL
83h : STATUS
Bank 1
FFFFFF
FFFFFF
FFFFFF
383838
Address
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
84h : FSR
85h : TRISA
86h : TRISB
87h : TRISC
Bank 0
INDF: 00h
TMR0: 01h
PCL : 02h
STATUS: 03h
Address
FSR: 04h
PORTA: 05h
PORTB: 06h
PORTC: 07h
20h
22h
21h
23h
A0h
A2h
A1h
A3h
Register File
bsf STATUS,RP0
movlw b’11110000’
movwf TRISB bcf STATUS,RP0
clrf PORTB
000 000 000 000 000 000 000 000 000
9-Bit Effective Address:
7-bits from InstructionRP0RP1
Bin Dec Hex
Example: Init ialize bits 0-3 of
PORTB as outputs
F0F0F0
W Register:
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 28
000
Register Indirect Addressing
FFFF
FFFF
FFFF
FFFF
1C1C
FFFF
FFFF
000h
001h
002h
003h
004h
005h
0FAh0FBh
0FCh
0FDh
0FEh
0FFh
IRP
Bank 2,3
000 000 0x1FC0x1FC0x1FC
1-bit from
STATUS Register 8-bits from FSR Register
9-bit Effective Address
(Use this when coding)
Bank 0,1
FSR
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
000 000 000 000 000 000
Register File
Address Bus
100h
101h
102h
103h
104h
105h
1FAh1FBh
1FCh
1FDh
1FEh
1FFh
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 29
0000
FFFF
Register Indirect Addressing
00h : INDF
02h : PCL
03h : STATUS
04h : FSR
20h
21h
22h
23h
80h
7Fh
7Eh7Dh
Register File
LOOP
movlw 0x20
movwf FSR
clrf INDF
incf FSR,f btfss FSR,7
goto LOOP
<next instruction>
FFFF
1818
8080
Address
0000
0000
0000
0000
00000000
0000
FFFF
01h : TMR0
Example: Clear all RAM locations from 20h to 7Fh
bcf STATUS,IRP
00 00 00 00 00 00 00 00 00
9-Bit Effective Address:
FSRIRP
2020
W Register:
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 30
Program Memory Organization
O Program memory is
divided into four 2k×14
pages
O Required to maintain
single word/single
cycle execution
O Paging is only a
concern when using
the call or gotoinstructions, or when
directly modifying the
program counter
Reset Vector Reset Vector
Interrupt Vector Interrupt Vector
Page 0PCH = 00hPage 0PCH = 00h
Page 1PCH = 08h
Page 1PCH = 08h
Page 2PCH = 10h
Page 2PCH = 10h
Page 3PCH = 18h
Page 3PCH = 18h
0000h
0004h
0800h
1000h
1800h
1FFFh
2k
2k
2k
2k
14-bits
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 31
Program Counter
00 00 00 00 00
0123456789101112
PCLPCH
00 00 00 00 00 00 00 00Program Counter
O 13-bit PC can access up to 213 = 8192 words
O Contains address of NEXT instruction (pipelining)
O Lower byte accessible in data memory as PCL
O Upper byte indirectly accessible via PCLATH
O Runs freely across page boundaries
O Events that modify PC out of sequence:
− Interrupts
− Instructions: CALL, GOTO, RETURN, RETLW, RETFIE
− Any instruction that uses the PCL register as an operand
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 32
PC Absolute Addressing
0123456789101112
OpcodeOpcode 00 00 00 00 00
CALL and GOTO Instructions:
13
00 00 00 00 00 00
O PC Absolute Addressing (Program Memory)
− J ump to another program memory location out of PC sequence
− Call a subroutine
O Used by the CALL and GOTO instructions
− 11-bits of the required 13 address bits are encoded in theinstruction
− 2 additional bits will come from the PCLATH registerO Used when performing Computed Goto operation
− Address to jump to is calculated by the program
− Computed address is written directly into the Program Counter
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00 00
1112
PC Absolute Addressing
0123456789101112
OpcodeOpcode 00 00 00 00 00
13
00 00 00 00 00 00
-- -- -- 00 00 00 00 00
01234567
PCLATH Register in Data Memory
14-Bit CALL or GOTO Instruct ion in Program Memory
012345678910
00 00 00 00 00 00 00 00 00 00 00
13-Bit Program Counter
2-Bits From PCLATH11-Bits From
Instruction
PCHPCHPCH PCLPCLPCL
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-- 00 00
PC Absolute Addressing
MySubroutine
movlw HIGH MySubroutine
movwf PCLATH
call MySubroutine
…
org 0x1250<do something useful>
…
return
Example: Jumping to code located in a different program memory page.
-- -- -- 00 00 00 00 00
01234567
PCLATH Register
0123456789101112
OpcodeOpcode 00 00 00 00 00
13
00 00 00 00 00 00
CALL Instruction in Program Memory
FFFF
W Register Program Counter - PCH:PCL
00 00 00 00 00 00 00 00 00 00 00
org 0x0020
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 35
00200020
CALL / RETURN Stack13-bit Program Counter
13-bit x 8-Level
Return Address Stack
movlw HIGH MySub1
movwf PCLATH
call MySub1
call MySub4
…
bsf PORTB,0
call MySub2
return bsf PORTB,1
call MySub3
return
bsf PORTB,2
return bsf PORTB,3
call MySub2
return
bsf PORTB,7
MySub1
1002
1001
1000
…
00240023
0022
0021
0020
1009
10081007
1006
1005
1004
1003
100A
MySub2
MySub3
MySub4
0
1
2
3
4
5
6
7
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 36
8-bit Data Bus
PC Relative Addressing
FFFFFF
FFFFFF FFFFFF
To write to PC:
nWrite high byte toPCLATH
oWrite low byte to PCL
(PCH will be loaded with
value from PCLATH)
PCLATH
PCH PCL
movlw HIGH 0x1250
movwf PCLATH
movlw LOW 0x1250
movwf PCL
FFFFFFW Register
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 37
PC Relative Addressing: Lookup
Table
P I C ®
M C U
Example: Use a lookup
table with relative
addressing to retrieve the
bit pattern to display a digit
on a 7-segment LED
ORG 0x0020 ;Page 0
movlw HIGH SevenSegDecode
movwf PCLATH
movlw .5
call SevenSegDecode
movwf PORTB
…
ORG 0x1800 ;Page 3
SevenSegDecode:
addwf PCL,fretlw b’00111111’ ;0
retlw b’00000110’ ;1
retlw b’01011011’ ;2
retlw b’01001111’ ;3
retlw b’01100110’ ;4retlw b’01101101’ ;5
retlw b’01111101’ ;6
retlw b’00000111’ ;7
retlw b’01111111’ ;8
retlw b’01101111’ ;9
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©2005 Microchip Technology Incorporated. All Rights Reserved.©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 38
Special FeaturesOverview
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Configuration WordCPCP -- DEBUGDEBUG WRT1WRT1 WRT0WRT0 CPDCPD LVPLVP BORENBOREN -- -- PWRTENPWRTEN WDTENWDTEN FOSC1FOSC1 FOSC0FOSC0
bit 0bit 1
O Located in program memory space, outside the reach
of the program counter
O Used to setup device options:
− Code Protection
− Oscillator Mode− Watchdog Timer
− Power Up Timer
− Brown Out Reset
− Low Voltage Programming
− Flash Program Memory Write
O Only readable at program time on most PIC16 devices
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 40
PIC16 Oscillator Options
XTXTXT
HSHSHS
LPLPLP
RCRCRC
INTRCINTRCINTRC
Standard frequency crystal oscillator Standard frequency crystal oscillator Standard frequency crystal oscillator
High frequency crystal oscillator High frequency crystal oscil lator High frequency crystal oscil lator
Low frequency crystal oscillator Low frequency crystal oscillator Low frequency crystal oscillator
External RC oscil lator External RC oscillator External RC oscil lator
Internal RC oscillator Internal RC oscil lator Internal RC oscillator
100kHz - 4MHz100kHz100kHz -- 4MHz4MHz
4MHz - 20MHz4MHz4MHz -- 20MHz20MHz
5kHz - 200kHz5kHz5kHz -- 200kHz200kHz
DC - 4MHzDCDC -- 4MHz4MHz
4 or 8 MHz ± 2%4 or 8 MHz4 or 8 MHz ± 2%2%
O Selectable clock options provide greater flexibility for
the designer:− LP Oscillator designed to draw least amount of current
− RC or INTRC provide ultra low cost oscillator solution
− XT optimized for most commonly used oscillator frequencies− HS optimized to drive high frequency crystals or resonators
O Speed ranges are guidelines only
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 41
POR, OST, PWRT
O POR: Power On Reset
− With MCLR tied to VDD, areset pulse is generated when
VDD rise is detectedO PWRT: Power Up Timer
− Device is held in reset for72ms (nominal) to allow VDD
to rise to an acceptable level(after POR only)
O OST: Oscillator Start-up Timer
− Holds device in reset for 1024cycles to allow crystal or
resonator to stabilize infrequency and amplitude; notactive in RC modes; usedonly after POR or Wake Upfrom SLEEP
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Events that wake processor from sleepEvents that wake processor from sleepMCLRMCLR
WDTWDT
INTINT
TMR1TMR1
ADC ADC
CMPCMP
CCPCCP
PORTBPORTB
SSPSSP
PSPPSP
Sleep ModeO The processor can be put into a power-down
mode by executing the SLEEP instruction− System oscillator is stopped
− Processor status is maintained (static design)− Watchdog timer continues to run, if enabled
− Minimal supply current is drawn - mostly due to leakage (0.1 -2.0μA typical)
Master Clear Pin Asserted (pulled low)Master Clear Pin Asserted (pulled low)
Watchdog Timer TimeoutWatchdog Timer Timeout
INT Pin InterruptINT Pin Interrupt
Timer 1 Interrupt (or also TMR3 on PIC18)Timer 1 Interrupt (or also TMR3 on PIC18)
A/D Conversion Complete Interrupt A/D Conversion Complete Interrupt
Comparator Output Change InterruptComparator Output Change Interrupt
Input Capture EventInput Capture Event
PORTB Interrupt on ChangePORTB Interrupt on Change
Synchronous Serial Port (I2C™ Mode) Start / Stop Bit Detect InterruptSynchronous Serial Port (I2C™ Mode) Start / Stop Bit Detect Interrupt
Parallel Slave Port Read or WriteParallel Slave Port Read or Write
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Watchdog Timer
O Helps recover from software malfunction
O Uses its own free-running on-chip RC oscillator
O WDT is cleared by CLRWDT instructionO Enabled WDT cannot be disabled by software
O WDT overflow resets the chip
O
Programmable timeout period: 18ms to 3.0s typicalO Operates in SLEEP; on time out, wakes up CPU
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BOR –Brown Out Reset
O When voltage drops below a
particular threshold, the device isheld in reset
O Prevents erratic or unexpectedoperation
O Eliminates need for external BORcircuitry
PBOR Programmable
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PBOR – Programmable
Brown Out ResetO Configuration Option (set at program time)
− Cannot be enabled / disabled in software
O Four selectable BVDD trip points:
− 2.5V – Minimum VDD for OTP PIC®MCUs
− 2.7V− 4.2V
− 4.5V
O For other thresholds, use an external
supervisor (MCP1xx, MCP8xx/TCM8xx, or
TC12xx)
( ) O O
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(P)BOR – Brown Out ResetO Holds PIC® MCU in reset until ~72ms after VDD rises back above threshold
PLVD – Programmable Low
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PLVD – Programmable Low
Voltage DetectO Early warning
before brown out
O 16 selectable trippoints:
− 1.8V up to 4.5V
in 0.1 to 0.2Vsteps
− External analoginput
O Internal VREF
VDD LVDIN
LVDIN
LVDCON
VREF
LVDIF
1 6 - b i t M ul t i p
l ex er
In-Circuit Serial
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In Circuit Serial
Programming™O Only two pins required for
programming
O Convenient for In-System
Programming of − Calibration Data
− Serialization Data
O Supported by MPLAB® PM3 & ICD2
PinPinPin
VPPVPP
VDDVDD
VSSVSS
RB6RB6
RB7RB7
FunctionFunctionFunction
Programming Voltage = 13VProgramming Voltage = 13V
Supply VoltageSupply Voltage
GroundGround
Clock InputClock Input
Data I/O & Command InputData I/O & Command Input
MCLR/VPP
VDD
VSS
RB6
RB7
To application circuit
VDD VDD App lication PCB
ICSP Connector
Isolation
circuits
ICSP™ Connector
I/O P t
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I/O Ports
O High Drive Capability
O Can directly drive LEDs
O Direct, single cycle
bit manipulation
O Each pin has individual
direction control under softwareO All pins have ESD protection diodes
O Pin RA4 is usually open drain
O All I/O pins default to inputs (high impedance) onstartup
O All pins multiplexed with analog functions default to
analog inputs on startup
I/O Pi C t l Di
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I/O Pin Conceptual Diagram
Bit 1 of TRISB
Register
PORTB
Bit 1
Latch
RB1Bit 1 of
Data Bus
ReadOperation
Write
Operation
movwf PORTB
movf PORTB,w
1 = RB1 is input0 = RB1 is output
I/O P t
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I/O Ports
O Bit n in TRISx controls the datadirection of Bit n in PORTx
O 1 = Input, 0 = Output
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©2005 Microchip Technology Incorporated. All Rights Reserved.©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 52
Hands-onExercises
MPLAB® ICD2
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 53
MPLAB® ICD2
PICDEM™ 2 Plus Board
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 54
PICDEM™ 2 Plus Board
MPASM™ Assembler
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 55
Template
O
If not using interrupts, lines 8 and 9 could be omittedO The labels in the left column may be anything you
want; these are just examples
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5
6
7
8
9
10
11
12
13
LIST p=16f877a ;Explicitly declare processor
#include <p16f877a.inc> ;Include register label definitions
org 0x0000 ;Put next line of code at address 0x0000
RESET_V goto START ;Reset Vector
org 0x0004 ;Put next line of code at address 0x0004
INT_V retfie ;Interrupt Vector
START {Begin your code here} ;Your code goes here
END ;Tell MPASM that this is the end
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2
34
5
6
7
8
9
10
11
12
13
LIST p=16f877a ;Explicitly declare processor
#include <p16f877a.inc> ;Include register label definitions
org 0x0000 ;Put next line of code at address 0x0000
RESET_V goto START ;Reset Vector
org 0x0004 ;Put next line of code at address 0x0004
INT_V retfie ;Interrupt Vector
START {Begin your code here} ;Your code goes here
END ;Tell MPASM that this is the end
Specifying the Radix
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RadixRadix MPASM SyntaxMPASM Syntax
Specifying the Radix
O By default, MPASM™ assembler expects numbers in hexadecimal
O Default can be changed through IDE or by adding r=hex or r=decas a parameter to the LIST directive:
O Good programming practice suggests that a number’s radix bespecified explicit ly:
LIST p=16f877a, r=decLIST p=16f877a, r=dec
BinaryBinary b’10101010’b’10101010’
DecimalDecimal d’25’ or .25d’25’ or .25
HexadecimalHexadecimal h’2A’ or 0x2Ah’2A’ or 0x2A
Lab 1: The Task
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Lab 1: The Task
O Turn on LED connected to bit 0
of PORTB (RB0)
Lab 1: Program Structure
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Lab 1: Program Structure
1 Instruction
4 Instructions
1 Instruction
1 Instruction: goto $(Go to self)
Switch to Bank 1
Load number into W
Move value toTRISB
Switch to Bank 0
Lab 1: Template
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Lab 1: Template
Lab 1: Solution
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Lab 1: Solution
Lab 1: Results
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Lab 1: Results
O You have learned:
− How to program a device and run thecode using the MPLAB® ICD2
− How to configure an I/O port
− How to manipulate I/O pins
− How to code an infinite loop (the
equivalent of while(1) in C)
Lab 2: The Task
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Lab 2: The Task
O Make the LED connected to bit 0
of PORTB (RB0) blink
Lab 2: The Task
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Lab 2: The Task
O A delay is required to make the
blinking slow enough for thehuman eye
O At 4MHz, one instructionexecutes in 1μs
O A 16-bit software counter is
sufficient to implement the delay
Naming
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Registers/ConstantsO Equate Method: MyReg0 equ 0x20 ;MyReg0 = 0x20
MyReg1 equ 0x21 ;MyReg1 = 0x21 MyReg2 equ 0x23 ;MyReg2 = 0x23
O Constant Block Method:CBLOCK 0x20 MyReg0 ;MyReg0 = 0x20
MyReg1: 2 ;MyReg1 = 0x21 MyReg2 ;MyReg2 = 0x23ENDC
Lab 2: Program Structure
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Lab 2: Program Structure
Taken from Lab 1
1 Instruction
1 Instruction
Subroutine Call
1 Instruction
1 InstructionSubroutine Call
Lab 2: Program Structure
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Lab 2: Program Structure
1 Instruction
1 Instruction
1 Instruction
1 Instruction
1 Instruction
Delay Subroutine
Hint: Use decfsz
Lab 2: Template – Part 1
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p
Lab 2: Template – Part 2
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p
Lab 2: Solution – Part 1
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Lab 2: Solution – Part 2
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Lab 2: Results
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O You have learned:
− How to define register labels− How to implement a loop
− How to implement software delays− How to use a “skip”instruction
− How to call a subroutine
Lab 3: The Task
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O Using one of the rotate
instructions, “ move” theilluminated LED across the lower 4 bits of PORTB. When it
reaches one side, send it back tothe start.
RB0RB1RB2RB3
Lab 3: Program Structure
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1 Instruction
1 Instruction
Same setup code from Lab 1
1 Instruction
1 Instruction
1 Instruction
Call same subroutine from Lab 2
Rember: The rotate
instructions operate
on 9-bits, with the
Carry bit in theSTATUS register as
the 9th bit
Lab 3: Template – Part 1
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Lab 3: Template – Part 2
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Lab 3: Solution – Part 1
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Lab 3: Solution – Part 2
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Lab 3: Results
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O You have learned:
− How to use the rotate instructions− How to use the bit test & skip
instructions
Lab 4: The Task
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O Same as Lab 3, but this timemake the direction of rotationchange when the LED is rotatedto either end
Lab 4: Program StructureSTART
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Set Carry Bit
Delay
Rotate Left
PORTB
RB3 = 1?
Yes
No
Setup PORTB
Rotate Right
PORTB
Delay
RB0 = 1?
No
Yes
bsf STATUS,C
Same setup code from Lab 1
1 Instruction
1 Instruction
Subroutine Call
2 Instructions
1 Instruction
1 InstructionSubroutine Call
2 Instructions
Lab 4: Template
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O Setup is identical to Lab 3 up to the LOOPLab 3: Rotating LED - Continued
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bsf STATUS,C ;Set carry bit for initial rotate
LEFT {1st Instruction} ;Rotate PORTB to left
{2nd Instruction} ;Call delay routine
{3rd Instruction} ;Is the LED on RB3 (PORTB,3) on?
{4th Instruction} ;if no, rotate left again
RIGHT {5th
Instruction} ;Rotate PORTB to right{6th Instruction} ;Call delay routine
{7th Instruction} ;Is the LED on RB0 (PORTB,0) on?
{8th Instruction} ;if no, rotate right again
{9th Instruction} ;if yes, rotate left
DELAY decfsz COUNTERL ;Decrement COUNTERL
goto DELAY ;If not zero, keep decrementing COUNTERL
decfsz COUNTERH ;Decrement COUNTERH
goto DELAY ;If not zero, decrement COUNTERL again
return ;Return to main subroutine
END
Lab 3: Rotating LED - Continued
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bsf STATUS,C ;Set carry bit for initial rotate
LEFT {1st Instruction} ;Rotate PORTB to left
{2nd Instruction} ;Call delay routine
{3rd Instruction} ;Is the LED on RB3 (PORTB,3) on?
{4th Instruction} ;if no, rotate left again
RIGHT {5
th
Instruction} ;Rotate PORTB to right{6th Instruction} ;Call delay routine
{7th Instruction} ;Is the LED on RB0 (PORTB,0) on?
{8th Instruction} ;if no, rotate right again
{9th Instruction} ;if yes, rotate left
DELAY decfsz COUNTERL ;Decrement COUNTERL
goto DELAY ;If not zero, keep decrementing COUNTERLdecfsz COUNTERH ;Decrement COUNTERH
goto DELAY ;If not zero, decrement COUNTERL again
return ;Return to main subroutine
END
Lab 4: Solution
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Lab 4: Results
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O You have learned:
− How to make decisions in softwareand take different courses of action
Lab 5: The Task
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O Use a lookup table to obtain thebit pattern to be displayed onPORTB
Lab 5: Program Structure
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Lab 1 Setup Code
1 Instruction
2 Instructions
1 Instruction
1 Instruction
1 Instruction
1 Instruction
Subrout ine Call
1 Instruction
3 Instructions
1 Instruction
Lab 5: Template – Part 1
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Lab 5: Lookup Table
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LIST p=16f877a
#include <p16f877a.inc>
cblock 0x020COUNTERL
COUNTERH
endc
org 0x0000
RESET_V goto START ;Reset Vector
START clrf PORTB ;Clear PORTB output latches
bsf STATUS,RP0 ;Switch to bank 1
movlw b’11110000' ;Load value to make lower 4 bits outputs
movwf TRISB ;Move value to TRISB
bcf STATUS,RP0 ;Switch to bank 0
{1st Instruction} ;Clear index into table{2nd Instruction} ;Load W with high byte of TABLE address
{3rd Instruction} ;Move W to PCLATH
;CONTINUED ON NEXT SLIDE
Lab 5: Lookup Table
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LIST p=16f877a
#include <p16f877a.inc>
cblock 0x020COUNTERL
COUNTERH
endc
org 0x0000
RESET_V goto START ;Reset Vector
START clrf PORTB ;Clear PORTB output latches
bsf STATUS,RP0 ;Switch to bank 1
movlw b’11110000' ;Load value to make lower 4 bits outputs
movwf TRISB ;Move value to TRISB
bcf STATUS,RP0 ;Switch to bank 0
{1st Instruction} ;Clear index into table{2nd Instruction} ;Load W with high byte of TABLE address
{3rd Instruction} ;Move W to PCLATH
;CONTINUED ON NEXT SLIDE
Lab 5: Template – Part 2
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Lab 5: Template – Part 3
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 88
Lab 5: Solution – Part 1
L b 5 L k T bl
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Lab 5: Lookup Table
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LIST p=16f877a
#include <p16f877a.inc>
cblock 0x020COUNTERL
COUNTERH
endc
org 0x0000
RESET_V goto START ;Reset Vector
START clrf PORTB ;Clear PORTB output latches
bsf STATUS,RP0 ;Switch to bank 1
movlw b’11110000' ;Load value to make lower 4 bits outputs
movwf TRISB ;Move value to TRISB
bcf STATUS,RP0 ;Switch to bank 0
clrf INDEX ;Clear index into table movlw HIGH TABLE ;Load W with high byte of TABLE address
movwf PCLATH ;Move W to PCLATH
;CONTINUED ON NEXT SLIDE
Lab 5: Lookup Table
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LIST p=16f877a
#include <p16f877a.inc>
cblock 0x020COUNTERL
COUNTERH
endc
org 0x0000
RESET_V goto START ;Reset Vector
START clrf PORTB ;Clear PORTB output latches
bsf STATUS,RP0 ;Switch to bank 1
movlw b’11110000' ;Load value to make lower 4 bits outputs
movwf TRISB ;Move value to TRISB
bcf STATUS,RP0 ;Switch to bank 0
clrf INDEX ;Clear index into table movlw HIGH TABLE ;Load W with high byte of TABLE address
movwf PCLATH ;Move W to PCLATH
;CONTINUED ON NEXT SLIDE
Lab 5: Solution – Part 2
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 90
Lab 5: Solution – Part 3
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 91
Lab 5: Results
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 92
O You have learned:
− How to implement a lookup table− How to retrieve data from a lookup
table
− How to call a subroutine on anotherpage
− How to perform a computed goto
Summary
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O PIC16 Architecture
O PIC16 Instruction SetO PIC16 Memory Organization
O Simple Programming Techniques
References
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 94
O PIC® MCU Mid-Range FamilyReference Manual (DS33023A)
Microchip TechnologyO Programming and Customizing
PICmicro Microcontrollersby Myke Predko
O Design with PIC®
Microcontrollersby John B. Peatman
References
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©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 95
O 123 PIC® Microcontroller Experiments for the Evil Genius
by Myke Predko
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©2005 Microchip Technology Incorporated. All Rights Reserved.
©2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 96
Thank You
Trademarks
Th Mi hi d l th Mi hi l A d PIC
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The Microchip name and logo, the Microchip logo, Accuron, dsPIC,KeeLoq, KeeLoq logo, microID, MPLAB, PIC, PICmicro, PICSTART,PRO MATE, rfPIC and SmartShunt are registered trademarks of MicrochipTechnology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV,
MXLAB, SEEVAL, SmartSensor and The Embedded Control SolutionsCompany are registered trademarks of Microchip Technology Incorporatedin the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM,dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM,fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,MPASM, MPLAB Cert if ied logo, MPLIB, MPLINK, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail , PowerCal, PowerInfo, PowerMate, PowerTool,REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance,UNI/O, WiperLock and ZENA are trademarks of Microchip TechnologyIncorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their respective
companies.