Unit_2

9/07/2008 Institute of Technology and Management, Gurgaon 1

MOS IC and Technology

Semester: VI Branch: ECE

VATSALA KHANNA , Sr. Lecturer , ECE & EI


Unit 2

MOS TRANSISTOR THEORY

Topics• MOS transistor • MOS device design equations,• Evaluation aspects of MOS transistor• Threshold voltage• MOS transistor transconductance & output conductance• Figure of merit• Determination of pull-up to pull-down ratio for an n-mos inverter driven by another n-mos

inverter & by one or more pass transistor• Alternative forms of pullup• CMOS and Bicmos-inverters• Latch up in CMOS circuitry and bicmos latch up susceptibility


Basic MOS Structure (1)

MOS Stands for Metal-Oxide-Semiconductor. It has two Terminals


When the Three components are brought in physical contact

Basic MOS Structure (2)


MOS Structure under External Bias

(1)• Vb is set at zero and Vg is varied.• If a voltage equal and opposite to ΦM – ΦS is applied externally

between gate and bulk, then bending near surface can be compensated and bands become flat.

• This is known as the Flat Band Condition, defined by

SMFBV


• Now if External Bias other than VFB is applied, MOS system will have

three regions of operation:

• Accumulation (VG < 0).

• Depletion (VG > 0, but small voltage).

• Inversion (VG >> 0, high).


(2)


ACCUMULATION REGION – Vg<0

DEPLETION REGION – Vg > 0 (Small)


(3)


• As the Positive Voltage is further increased, the depletion region increases.• With increasing Vg, downward bending also increases. Minority carriers

are attracted from bulk to surface. • The p and n concentration becomes equal. The difference between Ei and

Efp at surface becomes ‘0’.

• As Vg increases again, Ei becomes smaller than Efp on the surface. The electrons concentration becomes lager than holes concentration on surface. The n-type region created near the surface is called inversion layer.

• When density of electrons on surface becomes equal to holes concentration in bulk, surface is said to be inverted and Φs = -ΦF.

• At this point the width of the depletion region is maximum.


(4)


• Thus we define the conditions for Inversion as:• Φ = 2ΦF

• VGB = VTO.

• Threshold Voltage (VTO ) - Is defined as the voltage required to create inversion layer.

• There are three main components of threshold voltage:

1. The work function difference between gate and channel.2. The gate voltage component to change the surface potential.3. The gate voltage component to off-set the depletion charge.4. Oxide charges are present within the oxide layer. The gate voltage

component to off-set the oxide layer charges.


(5)


Expression for Threshold Voltage

• Combining the four factors together the expression for threshold voltage is given as:

• Threshold Voltage is Positive value for NMOS and has a Negative Value in case of PMOS.


N-Channel MOSFET Operation

• Simple operation of device is : current conduction control between Source and Drain using electric field generated by gate voltage .

• When voltage at drain, source and bulk is zero then the device is simple MOS capacitor.

• When small positive voltage is applied Vgs <Vto, only depletion region is formed and no channel from source to drain.


• When Vgs > Vto is applied on gate inversion layer is formed and source to drain are connected through a n-type channel.

• Gate Voltage is applied with respect to source then Vto is same as in case of MOS Capacitor.

N-Channel MOSFET Operation


Influence of changing value of

VDS • Now the N-type conducting channel is capable of carrying the

Drain Current.• Depending on the value of VDS, there are two modes of drain

current flow:

– Linear Mode : for small values of VDS

– Saturation Mode : for VDS> VDSAT.


NMOS in Linear Region

•If small drain voltage is applied, drain current flows through the conducting channel.•As drain voltage increases, drain current also increases linearly with voltage. The channel region acts as voltage controlled resistor.

This operation mode is called linear mode.


NMOS in Saturation Region (1)

• As the Drain Voltage is increased, the inversion layer charge and the channel depth at Drain end starts to decrease.

• For drain voltage equal to VDS = VDSAT , inversion charge at drain is reduced to zero, This is called the Pinch – off Point.


• Beyond the pinch-off point, i.e. for VDS > VDSAT, a depleted surface forms adjacent to the Drain.

• The depletion region grows towards the source with increasing VDS.

• This mode of operation is called Saturation Mode.• Near pinch-off section high field region forms between

channel-end and drain. Electrons arriving at this end injected to drain region and accelerated to drain.

• 3-D analysis of this system is very complex to establish the I-V relation of NMOS.

• Several approximations be made to simplify the problem. • The Gradual-Channel Approximation (GCA) is used which

converts 3D problem into 1-D for analytic derivation of I-V.

NMOS in Saturation Region (2)


Drain Current in Linear Region


Drain Current in Saturation region


IV Characteristics

Drain Current V/S Drain Source VoltageDrain Current V/S Gate Source Voltage


Transconductance

• Transconductance measures the change in the drain current produced by a given change in the gate-source voltage.

• Is given by the following equation:

Three Expressions for gm


Output Conductance

• Output conductance is defined as the change in drain current produced by a given change in drain-source voltage.

• Is calculated as follows:


Figure of merit of MOSFET

• AC drain source resistance: rds = ∂Vds (at constant Vgs)

∂Id

• Transconductance: gm = ∂Id (at constant Vds) = β(Vgs –Vt)

∂Vgs

• Amplification factor: µ = ∂Vds (at constant Id) = rds.gm

∂Vgs

• Input resistance: ri = ∂Vgs

∂Igs


MOS Transistor as Switch

nMOS transistor:•Closed (conducting) when Gate = 1 (Vdd, 5V)•Open (non-conducting) when Gate = 0 (ground, 0V

pMOS transistor:•Closed (conducting) whenGate = 0(ground, 0V)•Open (non-conducting) whenGate = 1 (Vdd, 5V)

For nMOS switch, source is typically tied to ground and is used to pull-down signals and for pMOS switch, source is typically tied to Vdd, used to pull signals up.


R

Vss

R

1 0

0 1

Vo

•Inverter : basic requirement for producing a complete range of Logic circuits

NMOS Inverter


Vdd

Vss

Vo

Vin

R Pull-Up

Pull Down

Basic Inverter: Transistor with sourceconnected to ground and a load resistorconnected from the drain to the positiveSupply railOutput is taken from the drain and controlinput connected between gate and groundResistors are not easily formed in silicon- they occupy too much area

Transistors can be used as the pull-up device

NMOS Inverter


Vdd

Vss

Vo

Vin

D

S

D

S

• Pull-Up is always on – Vgs = 0; depletion• Pull-Down turns on when Vin > Vt

VtV0 Vdd

Vi

• With no current drawn from outputs, Ids for both transistors is equal

Non-zero output

NMOS Depletion type Pull-up


Vgs=0.2VDD

Vgs=0.4 VDD

Vgs=0.6 VDD

Vgs=0.8VDD

Vgs=VDD

Ids

Vds

VDD

VoVDD

VDD

Vin

Ids

VDD –Vds

Ids

Vds

Vgs=-0.6VDD

Vgs=-0.4 VDD

Vgs=-0.2 VDD

Vgs=0

Vgs=0.2VDD


VoVDD

VDD

Vin

Vinv

• Point where Vo = Vin is called Vinv

DecreasingZpu/Zpd

IncreasingZpu/Zpd

• Transfer Characteristics and Vinv can be shifted by altering ratio of pull-up to Pull down impedances

NMOS Depletion type Pull-up


NMOS Depletion Mode Inverter Characteristics

• Dissipation is high since rail to rail current flows when Vin = Logical 1

• Switching of Output from 1 to 0 begins when Vin exceeds Vt of pull down device

• When switching the output from 1 to 0, the pull up device is non-saturated initially and this presents a lower resistance through which to charge capacitors (Vds < Vgs – Vt)


When cascading logic devices care must be taken to preserve integrity of logic levels

i.e. design circuit so that Vin = Vout = Vinv

Determine pull – up to pull-down ratio for driven inverter

Cascading NMOS Inverters


Assume equal margins around inverter; Vinv = 0.5 VddAssume both transistors in saturation, therefore: Ids = K (W/L) (Vgs – Vt)2/2

Depletion mode transistor has gate connected to source, i.e. Vgs = 0Ids = K (Wpu/Lpu) (-Vtd)2/2

Ids = K (Wpd/Lpd) (Vinv – Vt)2/2Enhancement mode device Vgs = Vinv, therefore

Assume currents are equal through both channels (no current drawn by load)(Wpd/Lpd) (Vinv – Vt)2 = (Wpu/Lpu) (-Vtd)2

Convention Z = L/WVinv = Vt – Vtd / (Zpu/Zpd)1/2

Substitute in typical values Vt = 0.2 Vdd ; Vtd = -0.6 Vdd ; Vinv = 0.5 Vdd

This gives Zpu / Zpd = 4:1 for an nmos inverter directly driven by another inverter

Determination of Pull-up to Pull-down ratio for nMOS Inverter driven by

another nMOS Inverter


Vdd Vdd

A B C

Inverter 1 Inverter 2

Vin1 Vout2

Pull-Up to Pull-Down Ratio for an nMOS inverter driven through 1 or more pass transistors

It is often the case that two inverters are connected via a series of switches (Pass Transistors)We are concerned that connection of transistors in series will degrade the logic levels into Inverter 2. The driven inverter can be designed to deal with this. (Zpu/Zpd >= 8/1)


Complimentary Transistor Pull – Up (CMOS)

Vdd

Vss

VoVin

Vout

Vin

VddVss

Vtn Vtp

Logic 0 Logic 1

P onN off

Both On

N onP off


Vout

Vin

VddVss

Vtn Vtp

P onN off

Both On

N onP off

1 2 3 4 5

1: Logic 0 : p on ; n off

5: Logic 1: p off ; n on

2: Vin > Vtn. Vdsn large – n in saturation Vdsp small – p in resistive Small current from Vdd to Vss

4: same as 2 except reversed p and n

3: Both transistors are in saturation Large instantaneous current flows


Current through n-channel pull-down transis 2

2 tninn

n VVI

Current through p-channel pull-up transistor

22 tpDDinp

p VVVI

At logic threshold, In = Ip

tpDDtnp

n

p

nin

tpDDintninp

n

tpDDinp

tninn

tpDDinp

tninn

VVVV

VVVVV

VVVVV

VVVVV

1

22

2222

p

n

p

ntntpDD

in

VVV

V

1

If n = p and Vtp = –Vtn

2DD

inVV

nnn

p

ppLW

LW

Mobilities are unequal : µn = 2.5 µp

Z = L/WZpu/Zpd = 2.5:1 for a symmetrical CMOS inverter

CMOS Inverter Characteristics


CMOS Inverter Characteristics

• No current flow for either logical 1 or logical 0 inputs• Full logical 1 and 0 levels are presented at the output• For devices of similar dimensions the p – channel is slower

than the n – channel device


Simplified BiCMOS Inverter

•Two bipolar transistors (T3 and T4), one nMOS and one pMOS transistor (both enhancement-type devices, OFF at Vin=0V).

•The MOS switches perform the logic function & bipolar transistors drive output loads.

Vout

Vdd

VinT2

T4

T1

T3 CL


Basic Operation

When Vin = 0 : • T1 is off. Therefore T3 is non-conducting• T2 ON - supplies current to base of T4• T4 base voltage set to Vdd.• T4 conducts & acts as current source to charge load CL towards Vdd.• Vout rises to Vdd - Vbe (of T4) Note : Vbe (of T4) is base-emitter voltage of T4. (pullup bipolar transistor turns off as the output approaches 5V - Vbe (of T4))

When Vin = Vdd :• T2 is off.Therefore T4 is non-conducting.• T1 is on and supplies current to the base of T3 • T3 conducts & acts as a current sink to discharge load CL towards 0V.• Vout falls to 0V+ VCEsat (of T3)Note : VCEsat (of T3) is saturation V from T3 collector to emitter


Conventional BiCMOS Inverter

•Two additional enhancement-type nMOS devices have been added (T5 and T6).•These transistors provide discharge paths for transistor base currents during turn-off.•Without T5, the output low voltage cannot fall below the base to emitter voltage VBE of T3.

Vout

Vdd

VinT2

T4

T1

T3 CL

T6

T5


Basic Operation

When Vin = 0 : T1 is off. Therefore T3 is non-conductingT2 ON - supplies current to base of T4T4 base voltage set to Vdd.T5 is turned on & clamps base of T3 to GND. T3 is turned off. T4 conducts & acts as current source to charge load CL towards Vdd.Vout rises to Vdd - Vbe (of T4)

When Vin = Vdd :T2 is off T1 is on and supplies current to the base of T3 T6 is turned on and clamps the base of T4 to GND. T4 is turned off. T3 conducts & acts as a current sink to discharge load CL towards 0VVout falls to 0V+ VCEsat (of T3)


Comparison of logic families


Further advantages of BiCMOS Technology

•Analogue amplifier design is facilitated and improved.•High impedance CMOS transistors may be used for the input circuitry while the remaining stages and output drivers are realised using bipolar transistors.•In general, BiCMOS devices offer many advantages where high load current sinking and sourcing is required. The high current gain of the NPN transistor greatly improves the output drive capability of a conventional CMOS device.•MOS speed depends on device parameters such as saturation current and capacitance. These in turn depend on oxide thickness, substrate doping and channel length.•Compared to CMOS, BiCMOS’s reduced dependence on capacitive load and the multiple circuit and I/Os configurations possible greatly enhance design flexibility and can lead to reduced cycle time (i.e., faster circuits).[Peak bipolar speed is less dependent on circuit capacitance. Device parameters f t , Jk and Rb determine Bipolar circuit speed performance (not covered here) and depend on process parameters such as base width, epitaxial layer profile, emitter width and extrinsic base formation]


Further advantages of BiCMOS Technology

•BiCMOS is inherently robust with respect to temperature and process variations, resulting in less variability in final electrical parameters, resulting in higher yield, an important economic consideration.•Large circuits can impose severe performance penalties due to simultaneously switching noise, internal clock skews and high nodal capacitances in critical paths - BiCMOS has demonstrated superiority over CMOS in all of these factors.•BiCMOS can take advantage of any advances in CMOS and/or bipolar technology, greatly accelerating the learning curve normally associated with new technologies.


Are there disadvantages with BiCMOS technology ?

•Main disadvantage : greater process complexity compared to CMOS •Results in a 1.25 -> 1.4 times increase in die costs over conventional CMOS. •Taking into account packaging costs, the total manufacturing costs of supplying a BiCMOS chip ranges from 1.1-> 1.3 times that of CMOS.•However, as CMOS complexity has increased, the percentage difference between CMOS and BiCMOS mask steps has decreased. •Therefore, just as power dissipation constraints motivated the switch from nMOS to CMOS in the late ‘70s, performance requirements motivated a switch from CMOS to BiCMOS in the late ‘80s for VLSI products requiring the highest speed levels.•Capital costs of investing in continually smaller (<1um) CMOS technology rises exponentially, while the requirement of low power supplies for sub-0.5um CMOS results in degradation of performance. •Since BiCMOS does not have to be scaled as aggressively as CMOS, existing fabs can be utilised resulting in lower capital costs. Extra costs incurred in developing a BiCMOS technology is more than offset by the fact that the enhanced chip performance obtained extends the usefulness of manufacturing equipment & clean rooms by at least one technology generation.


Thanks !!!

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