Unit III Design for Testability. Syllabus Design for Testability – Ad-hoc design – generic scan...
-
Upload
angel-russell -
Category
Documents
-
view
235 -
download
0
Transcript of Unit III Design for Testability. Syllabus Design for Testability – Ad-hoc design – generic scan...
Unit III Design for Testability
Syllabus
Design for Testability – Ad-hoc design –
generic scan based design – classical scan based
design – system level DFT approaches.
Validation and Test of Manufactured Circuits
Components of DFT strategy• Provide circuitry to enable test• Provide test patterns that guarantee reasonablecoverage
Goals of Design-for-Test (DFT)Make testing of manufactured part swift andcomprehensive
DFT MantraProvide controllability and observability
Design for Testability
M state regs
N inputs K outputs
K outputsN inputs
Combinational
Logic
Module
Combinational
Logic
Module
(a) Combinational function (b) Sequential engine
2N patterns 2N+M patterns
Exhaustive test is impossible or unpractical
Test Approaches
• Ad-hoc testing• Generic Scan-based Design• Classical scan DesignsProblem is getting harder – increasing complexity and heterogeneous combination of
modules in system-on-a-chip.– Advanced packaging and assembly techniques extend
problem to the board level
Ad Hoc Design for Testability Techniques
• Test points• Initialization• Monostable Multivibrator• Oscillators and clocks• Partitioning of counters and shift registers • Partitioning of large combinational circuits• Logical Redundancy• Global feedback paths
Test PointsMethod of Test Points:
Block 1 Block 2Block 1 is not observable,Block 2 is not controllable
Block 1 Block 2
1- controllability: CP = 0 - normal working mode CP = 1 - controlling Block 2 with signal 1
1
CP
Improving controllability and observability:
Block 1 Block 2
0- controllability: CP = 1 - normal working mode CP = 0 - controlling Block 2
with signal 0
&
CP
OP
OP
Test Points (contd.)Method of Test Points:
Block 1 Block 2Block 1 is not observable,Block 2 is not controllable
Block 1 Block 21
CP1
Improving controllability:
Block 1 Block 2
Normal working mode:CP1 = 0, CP2 = 1
Controlling Block 2 with 1:CP1 = 1, CP2 = 1Controlling Block 2 with 0:CP2 = 0
MUX
CP1
&
CP2
CP2
Normal working mode:CP2 = 0
Controlling Block 2 with 1:CP1 = 1, CP2 = 1Controlling Block 2 with 0:CP1 = 0, CP2 = 1
Monostable Multivibrator
Oscillators and Clocks
Partitioning of Registers
Partitioning of Large Combinational circuits
Partitioning of Large Combinational circuits (contd.)
Generic scan-based Design
• Full Serial Integrated Scan• Isolated Serial Scan• Nonserial Scan
Full Serial Integrated Scan
Isolated Serial Scan
Isolated Serial Scan (contd.)
Non-serial Scan
Level-Sensitive Scan Design (LSSD)
System-Level DFT Approaches
• System-level Busses• System-level Scan paths
System-level Busses
System-level Scan paths