ATPG - 3 Testability Design

– Method of test points
– Multiplexing and demultiplexing of test points
– Time sharing of I/O for normal woring and testing modes
– !artitioning of registers and large combinational circuits
• "can#!ath Design
– &ull and partial serial scan#paths
– 'on#serial scan design
Method of Test !oints(
)loc + is not controllable
Method of Test !oints(
)loc + is not controllable
Multiplexing monitor points(
monitor points,
replaced by a single
address a selected
obser%ation point
time Ad%antage( 2n 3 *4 55 +n
'umber of additional pins( 2n 3 *4
'umber of obser%able points( 6+n7
Technical University Tallinn, ESTONIA
Multiplexing monitor points(
monitor points,
to dri%e the address lines
of the multiplexer
time
$ounter
Demultiplexer for implementing control points(
.
*
input pins for controlling
used8
%alues
x
x*
x+
xn
Ad%antage( 2n 3 *4 55 ' 'umber of additional pins( 2n 3 *4
'umber of control points( +n#* ' ≤
+n
Demultiplexer for implementing control points(
.
*
pins for controlling testpoints,
demultiplexer and a latch
register can be used8
for addressing, a counter
to dri%e the address lines of
the demultiplexer $ounter
the proper control %alues
To reduce the number of
output pins for obser%ing
monitor points, time#
inputs, again counter or
if needed
.
*
'
input pins for controlling
test points, time#sharing
introduced8
address lines of
demultiplexer , counter or
if needed
$!*
$!+
$!:
$!;
- CP1 and CP2 are not controllable
- CP3 and CP4 are not observable
D&T tas( Improve the testability by sing a single control inpt! no
additional inpts"otpts allo#ed
*
+
:
;
*
+
:
;
$!*
$!+
$!:
$!;
*
+
:
;
*
+
:
;
→ Improving the observability
$!*
$!+
$!:
$!;
<i%en a circuit: CP1 and CP2 are not controllable → Improving the controllability
M01
M01 &&
x3 y1
z 3
z 2
z 1
F 1
F 2
F 3
Ad Hoc Design for Testability Techniques
9xamples of good candidates for control points( – control, address, and data bus lines on bus#structured designs
– enable/hold inputs of microprocessors
– enable and read/write inputs to memory de%ices
– cloc and preset/clear inputs to memory de%ices 2flip#flops, counters, 8884
– data select inputs to multiplexers and demultiplexers
– control lines on tristate de%ices
9xamples of good candidates for obser%ation points( – stem lines associated with signals ha%ing high fanout
– global feedbac paths
– redundant signal lines
– outputs of logic de%ices ha%ing many inputs 2multiplexers, parity generators4
– outputs from state de%ices 2flip#flops, counters, shift registers4
– address, control and data busses
&ault redundancy and testability
&aults at x2 not
=edundant gates are remo%ed(
&ault at x12 not testable
x12
x11
=edundancy should be a%oided(
• If a redundant fault occurs, it may in%alidate
some test for nonredundant faults
• =edundant faults cause difficulty in
calculating fault co%erage
trying to generate a test for a redundant fault
=edundancy intentionally added(
circuits
detecting circuits4
@ogical redundancy(
T - . # testing mode
&ault redundancy(
&ault ≡ * not testable
T - * # testing mode
!artitioning of registers 2counters4(
$@ $@
Instead of +* - CC:
clocs needed
+C clocs needed
!artitioning of large combinational circuits(
$*
$+
their length
cloc cycles are needed to initiali?e
and sensiti?e patterns
T - . # normal woring mode
T - * # scan mode
disconnected from the combinational
form a shift register
O0TM01
DM01I'
"$A'
O0T
"$A'
I'
controllability/obser%ability
"can#I' +
"can#O0T +
In parallel scan path fip-fops can be organized in more than one scan chain
Advantage: time ↓
Disadvantage: # pins ↑
=+
In partial scan instead o ull- scan, it may be advantageous to scan only some o the fip-
fops
IN R 2
$ontrol !art
M3
IN R 2
$ontrol !art
1#Address
F#Address
In random access scan each fip-fop in a logic network is selected individually by an address or control and observation o its state
Example:
O0TM01
DM01I'
"$A'
O0T
"$A'
I'
controllability/obser%ability
• Impro%ing testability for any set of pseudo#random patterns
2!seudorandom )I"T4
– $estability measres are sed to characteri%e the controllability and
observability o& the circit
• Impro%ing testability for a gi%en sequence of %ectors
2&unctional )I"T4
– 'alt simlation is sed &or measring the &alt coverage
Methods that are used(
– path tracing
HG
Test
sequence
• Identi&ication o& the &alts that are detected
• $he remaining &alts are classi&ied as – A( 'alts that #ere not excited
– )( 'alts at gate inpts that #ere e,cited bt not propagated to the gate output
– $( 'alts that #ere e,cited bt not propagated to circuit output
• $he &alts and . require control points &or their detection
• $he &alts C may be detected by either by obser%ation points or by
control points
• Control points selection shold be carried ot be&ore observation
points selection
1 1
acti%ated
propagated
propagated to the output
* . . * . * . . . * * # * # * * *
+ . * . * * * . * # # # . . # # .
: . * . * . * . . # # * # * # * *
A b /.( b 0 1 is missing
) x : /.( x 3 a 0 11 is missing
) a /.( x 3 a 0 11 is missing
$ x + /.( x 1 x 20 1 x * /. x + /. x : /. a /. b /.
$lass &aults Missing signals
"election of Test !oints
$lassification of faults 1
* . . * . * . . . * * # * # * * *
+ . * . * * * . * # # # . . # # .
: . * . * . * . . # # * # * # * *
) x : /.( x 3 a 0 11 is missing
$ x + /.( x 1 x 20 1 x * /. x + /. x : /. a /. b /.
'ot detected faults(
* . . * . * . . . * * # * # * * *
+ . * . * * * . * # # # . . # # .
: . * . * . * . . # # * # * # * *
) x : /.( x 3 a 0 11 is missing
$ x + /.( x 1 x 20 1 x * /. x + /. x : /. a /. b /.
* . . * . * . . . * * # * # * * *
+ . * . * * * . * # # # . . # # .
: . * . * . * . . # # * # * # * *
) x : /.( x 3 a 0 11 is missing
$ x + /.( x 1 x 20 1 x * /. x + /. x : /. a /. b /.
* . . * . * . . . * * # * # * * *
+ . * . * * * . * # # # . . # # .
: . * . * . * . . # # * # * # * *
) x : /.( x 3 a 0 11 is missing
$ x + /.( x 1 x 20 1 ! bt
path activation is missing x * /. x + /. x : /. a /. b /.
"election of Test !oints( !rocedure
*8 "election of control points(
– nce control point candidates are identi&ied &or the &alts and .! a minimum nmber o& control points CP5 can be identi&ied
– $his can be &ormlated as a minimum co%erage problem #here a minimm CPs are selected sch that at least one CP candidate is inclded &or each &alt in and .
&* &+ &: &; &C & & &B &J
CP3 1 1 1
$ontrol
point
candidates
&aults
"elected
control
points
+8 "election of obser%ation points
– nce the CPs are selected! the given test patterns are augmented to accommodate the additional inpts assotiated #ith the CPs and fault simulation is per&ormed
– $he &alt class $ is updated
– 'or each &alt! in C the circit lines to #hich the e&&ect o& the &alt propagates! are identi&ied as a potential obser%ation point candidates
– minimum co%ering problem is &ormlated and solved to &ind the observation points to be added
DM01$ontrol
CP3 1 1 1
Minimi?ation of control points
x :-* 3 3 3
a -* 3 3 3
$lass $( x + /. 2obser%able point4
'o
exor gates can be used(
O0T
signature analy?ers can be used(
O0T
# e
"AM!@9 mode(
!=9@OAD mode(
9xtest instruction(
I'T9"T instruction
)ypass instruction(
o D!
(rom DI
ID$OD9 instruction(
Connects the component device identification register serially between T! and T" in the #hift-$ T%P controller state
%llows board-level test controller or external tester to read out component !
=equired whenever a &''C identification register is included in the design
D! DI 0ersion 1art /umber 2anuacturer ID 3
4-bits 5ny ormat
36-bits 5ny ormat
'hort
!pen
3
9
9
9
9
3
'hort
!pen
39
99
99
93
33
Assume wired AND
Kaut? showed in *J; that a sufficient condition to detect any pair of short circuited nets was that the Lhori?ontal codes must be unique for all nets8 Therefore the test length is 7log+2'46
'hort
!pen
393
999
993
933
339
Assume wired AND
All .#s and all *#s are forbidden codes because of stuc#at faults Therefore the final test length is 7log+2'3+46
'uspected :ired 5/D
'hort
!pen
Assume wired AND
To impro%e the diagnostic resolution we ha%e to add one bit more
'uspected :ired 5/D
*

Test generation(
*

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&irst assignment
"ynthesis of Testable $ircuits
32172163151432322310 x x xc x xc x xc xc x xc xc xcc y ⊕⊕⊕⊕⊕⊕⊕=
$alculation of constants(
f i x* x+ x: y Σ
f . . . . * * $. - f . f * . . * . * $* - f .⊕ f * f +
. * . * . $+ - f .⊕ f + f : . * * . . $: - f .⊕ f *⊕ f +⊕ f : f ; * . . . * $; - f .⊕ f ; f C * . * . * $C - f .⊕ f *⊕ f ;⊕ f C f * * . * * $ - f .⊕ f +⊕ f ;⊕ f f * * * * . $: - f .⊕ f *⊕ f +⊕ f :⊕ f ;⊕ f C⊕ f ⊕ f
213113 1 x x x x x x y ⊕⊕⊕⊕=
<i%en(
x* x+ x:
%musing testability(
Theorem: Fou can test an arbitrary digital system by only : test patterns
if you design it approprietly
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Proof:

ATPG - 3 Testability Design

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