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UC Davis ECE MSEE Thesis Measurement Board Block...
43
Date: Sheet of Date: Created by: Size: REV: PCB NO: Modified by: File: Title: 5 4 1 2 3 B A C D E 5 4 1 2 3 A B C D E E +5.2V 71nH 76nH 71nH TXCVR UARTLite DISPLAY Control Data Path FPGA SPI TI Micron SPI Configuration AsAPv2 SPI 1A 16 2 sub-phase 0 sub-phase 1 ODDR CLK CLK 250MHz DDR 250MHz DDR 333MHz DDR 64-bit Data, 16-bit Address CLK + - NL NL 15pF 499 270 62 - + 500MS/s A = -2.4 dB Analog 39.6pF 500MS/s 59.9pF 59.9pF 39.6pF A = -2.4 dB 12-bit 500MS/s OVR DRDY Sampling Clock Input 500 MHz + - THS4509 100 100 5.2pF AD9516 Devices DAC5682 16-bit Sampling Clock Input 500 MHz 500MS/s 16-bit LVDS 250MHz DDR 250MHz DDR DCLK fc = 140 MHz, BW = 120 MHz, Ripple = 0.5 dB 7th Order Chebyshev Lowpass Filter 62 270 226 OPA695 226 15pF 49.9 110 NL THS4302 - + 49.9 A = 8 dB Zi = 50 Ohm Zo = 100 Ohm A = 14 dB Zi = Zo = 50 Ohm Zi = 200 Ohm ADS5463 12-bit LVDS CLK DI[15:0] DA[15:0] DB[15:0] sub-phase 1 2x Polyphase Decimation Filter 2x Polyphase Decimation Filter sub-phase 0 DB[15:0] DA[15:0] DO[15:0] CLK XC5VSX50T-3FF1136C Xilinx Virtex 5 SX50T AsAP v2 AsAP v2 ODDR Write Data Read Data FFT Co-processor RF Input Spectrum Analyzer DC to 120 MHz Zi = 50 Ohm Zo = 50 Ohm IDDR BW: 120 MHz 2 DO[15:0] DB[15:0] DA[15:0] BW: 120 MHz 2x Polyphase Interpolation Filter 2x Polyphase Interpolation Filter DI[15:0] DO[15:0] CLK IFF 0 1 IN X2 Generator Waveform Arbitrary SDRAM Controller 499 Samsung QDR-II SRAM K7R323684C-EC250 Micron DDR2 SDRAM SODIMM MT16HTF25664H – 2GB 16 -5.2V +5.2V 0dB -20dB -40dB -60dB -80dB -80dB -60dB -40dB -20dB 0dB -80dB -60dB -40dB -20dB 0dB -125 MHz amplitude frequency 625 MHz 125 MHz 250 MHz 500 MHz 375 MHz -125 MHz amplitude frequency 625 MHz 125 MHz 250 MHz 500 MHz 375 MHz 375 MHz 500 MHz 250 MHz 125 MHz 625 MHz amplitude amplitude frequency 625 MHz 125 MHz 250 MHz 500 MHz 375 MHz UC Davis ECE MSEE Thesis Measurement Board Block Diagram -125 MHz -125 MHz Digital Filter Response -80dB -60dB -40dB -20dB 0dB AAF Response Large Transition BW Input Sample Rate Folded Transition BW Output Sample Rate 1D Spectrum at Output of Digital Anti-Alias Filter 1C Spectrum at Output of ADC 1B 1A Spectrum at Output of Analog Anti-Alias Filter Spectrum at Output of 2-to-1 Down Sampler 1B 1C 1D fs fs/2 fs fs/2 fs fs/2 UC Davis Confidential Copyright © 2008 VLSI Computation Lab frequency 32-bit Processor MicroBlaze DAC5682Z AD9516-3 SODIMM I2C FT245BL 15-bits MPMC DDR SDRAM microSD (2GB) UARTLite SPI AsAPv2 Configuration CP2102 SPI SPI GPIO Flash PROM (64Mb) I2C Fan #1 Control Fan #2Control PLB PLB User Interface Board Control SPI SPI Xilinx Xilinx Spartan-3A XC3S1400A-4FG484 DDR SDRAM 16-bit Data, 12-bit Address 100MHz DDR MT46V32M16BN-6:F I2C M25P64 AMC6821 AMC6821 ST Micro TI SanDisk 2GB 14-pin, 2mm Header CP2102 Silicon Labs To SS To DAC5682 AD9516 SPI Data Path FPGA Control Spectrum Analyzer Spectra Analysis fs 2fs fs/2 3fs/2 A = 14 dB RF Output Signal Source DC to 120 MHz 49.9 A = -1 dB A = -3 dB A = -3 dB Zo = 50 Ohm A = -9 dBm A = 11 dBm 71nH 76nH 71nH 71nH 76nH 71nH 19.8pF 30pF 30pF 19.8pF SPI TMP125 TMP125 SPI To Temp Sense Sense To Temp -2.5V +2.5V A = -1 dB 7th Order Chebyshev Lowpass Filter fc = 140 MHz, BW = 120 MHz, Ripple = 0.5 dB +5.2V 43 3-27-2009_12:24 1 001 BLOCK DIAGRAM MEAS_MAIN_BOARD JEREMY W. WEBB 342
Transcript of UC Davis ECE MSEE Thesis Measurement Board Block...
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
+5.2V
71nH 76nH 71nH
TXCVR
UARTLiteDISPLAY
ControlData Path FPGA
SPI
TI
Micron
SPI
ConfigurationAsAPv2
SPI
1A
16
2
sub-phase 0
sub-phase 1
ODDR
CLK CLK
250MH
z DD
R
250MH
z DD
R
333MH
z DD
R
64-bit D
ata, 16-bit A
dd
ress
CLK
+
-
NL
NL
15p
F
499
270 62
-
+
500MS/s
A = -2.4 dB
Analog
39.6pF500MS/s
59.9pF 59.9pF39.6pF
A = -2.4 dB
12-bit
500MS/s
OVRDRDY
SamplingClock Input
500 MHz
+
-
THS4509
100
100
5.2pF
AD9516Devices
DAC5682
16-bit
SamplingClock Input
500 MHz
500MS/s16-bit LVDS
250MHz DDR
250MHz DDR
DCLK
fc = 140 MHz, BW = 120 MHz, Ripple = 0.5 dB7th Order Chebyshev Lowpass Filter
62270
226
OPA695226
15pF
49.9110
NL
THS4302
-
+
49.9 A = 8 dBZi = 50 Ohm
Zo = 100 Ohm
A = 14 dBZi = Zo = 50 Ohm
Zi = 200 Ohm
ADS5463 12-bit LVDS
CLK
DI[15:0]
DA[15:0]
DB[15:0]
sub-phase 1
2x Polyphase Decimation Filter
2x Polyphase Decimation Filter
sub-phase 0
DB[15:0]
DA[15:0]
DO[15:0]
CLK
XC5VSX50T-3FF1136C
Xilinx Virtex 5 SX50TAsAP v2
AsAP v2
ODDR
Write D
ata
Read
Data
FFT
Co-processor
RF Input
Spectrum Analyzer
DC to 120 MHzZi = 50 Ohm
Zo = 50 Ohm
IDDR
BW: 120 MHz
2
DO[15:0]
DB[15:0]
DA[15:0]
BW: 120 MHz
2x Polyphase Interpolation Filter
2x Polyphase Interpolation Filter
DI[15:0]DO[15:0]
CLK
IFF0
1
IN
X2
Generator
Waveform
Arbitrary
SDRAM Controller
499
SamsungQDR-II SRAM
K7R323684C-EC250
MicronDDR2 SDRAM
SODIMM
MT16HTF25664H – 2GB
16
-5.2V
+5.2V
0dB
-20dB
-40dB
-60dB
-80dB
-80dB
-60dB
-40dB
-20dB
0dB
-80dB
-60dB
-40dB
-20dB
0dB
-125 MHz
amplitude
frequency625 MHz125 MHz 250 MHz 500 MHz375 MHz
-125 MHz
amplitude
frequency625 MHz125 MHz 250 MHz 500 MHz375 MHz
375 MHz 500 MHz250 MHz125 MHz 625 MHz
amplitude
amplitude
frequency625 MHz125 MHz 250 MHz 500 MHz375 MHz
UC Davis ECE MSEE ThesisMeasurement Board Block Diagram
-125 MHz
-125 MHz
Digital Filter Response
-80dB
-60dB
-40dB
-20dB
0dB
AAF Response
Large Transition BW
Input Sample Rate
Folded Transition BW
Output Sample Rate
1D
Spectrum at Output of Digital Anti-Alias Filter1C
Spectrum at Output of ADC1B
1A Spectrum at Output of Analog Anti-Alias Filter
Spectrum at Output of 2-to-1 Down Sampler
1B
1C 1D
fsfs/2
fsfs/2
fsfs/2
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
frequency
32-bit Processor
MicroBlaze
DAC5682Z AD9516-3
SODIMM
I2C
FT245BL15-bits
MPMC
DDR SDRAM
microSD (2GB)
UARTLite
SPIAsAPv2
Configuration
CP2102
SPI
SPI
GPIO
Flash PROM (64Mb)
I2CFan #1 Control
Fan #2Control
PLB
PL
B
User InterfaceBoard Control
SPISPI
Xilinx
XilinxSpartan-3A
XC3S1400A-4FG484
DDR SDRAM
16-bit D
ata, 12-bit A
dd
ress
100MH
z DD
R
MT46V32M16BN-6:F
I2C
M25P64
AMC6821
AMC6821
ST Micro
TI
SanDisk2GB
14-pin, 2mm
Header
CP2102
Silicon Labs
To SS To
DAC5682 AD9516
SPIData Path FPGA
Control
Spectrum Analyzer Spectra Analysis
fs 2fsfs/2 3fs/2
A = 14 dB
RF Output
Signal Source
DC to 120 MHz49.9
A = -1 dB
A = -3 dB
A = -3 dB
Zo = 50 Ohm
A = -9 dBm
A = 11 dBm
71nH 76nH 71nH
71nH76nH71nH
19.8pF30pF30pF19.8pF
SPI
TMP125 TMP125
SPI
To Temp
Sense Sense
To Temp
-2.5V
+2.5VA = -1 dB
7th Order Chebyshev Lowpass Filterfc = 140 MHz, BW = 120 MHz, Ripple = 0.5 dB
+5.2V
43
3-27-2009_12:24
1 001
BLOCK DIAGRAM
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
6I MOUNTING HOLES
DESCRIPTIONSHEET/BLOCK
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
DESCRIPTION
1 TITLE PAGE/BLOCK DIAGRAM
3 SCHEMATIC DESIGN SHEET/BLOCK INDEX
5 POWER GENERATION BLOCK DIAGRAM
6A +12V SUPPLY INPUT6B +12V FILTERING6C +12V ANALOG AND DIGITAL FILTERING6D GROUND TEST POINTS
6 MAIN POWER INPUT AND FAN CONTROL
A INDEXSHEET/BLOCK
2 SCHEMATIC DESIGN SHEET/BLOCK INDEX
10 ANALOG POWER REGULATION - PART 2 OF 210A +12V ANALOG10B +2.5V ANALOG SUPPLY REGULATION10C +1.8V ANALOG SUPPLY REGULATION10D -6V ANALOG SUPPLY REGULATION10E -5.2V ANALOG SUPPLY REGULATION10F +8V ANALOG SUPPLY REGULATION10G POWER LEDS
11 10MHZ REFERENCE CLOCK GENERATION11A 10MHZ REFERENCE CLOCK GENERATION11B CML-LVDS TRANSLATOR11C LVDS 1:2 FAN OUT11D 10MHZ OUTPUT BUFFER
12 HIGH-SPEED CLOCK GENERATION12A AD9516 LVPECL POWER SUPPLY AND DECOUPLING12B 10MHZ REFERENCE CLOCK BUFFER12C AD9516 HIGH-SPEED CLOCK GENERATION PLL12D AD9516 LVPECL CLOCK TERMINATIONS12E AD9516 MAIN POWER SUPPLY DECOUPLING
13 CONTROL FPGA DIGITAL DESIGN
14 XILINX SPARTAN-3A CONTROL FPGA CONFIGURATION14A CONFIGURATION SPI FLASH PROM/JTAG INTERFACE14B SPARTAN-3A FPGA CONFIG MODE14C SPARTAN-3A FPGA SPI MODE
15 XILINX SPARTAN-3A CONTROL FPGA I/O15B 100MHZ DIGITAL CLOCK15C VREF DECOUPLING CAPACITORS
16 XILINX SPARTAN-3A CONTROL FPGA POWER SUPPLIES
17 XILINX SPARTAN-3A CONTROL FPGA PERIPHERALS17A HW and Slot ID
18 DDR SDRAM ADDRESS AND CONTROL TERMINATIONS18A DDR SDRAM CONTROL TERMINATIONS18B DDR SDRAM ADDRESS TERMINATIONS18C VTT TERMINATION DECOUPLING CAPACITORS
19 DDR SDRAM DATA TERMINATIONS
20 DIGITAL TEMPERATURE SENSORS20A TEMP SENSOR 1A20B TEMP SENSOR 1B20C TEMP SENSOR 1C20D TEMP SENSOR 2A20E TEMP SENSOR 2B20F TEMP SENSOR 2C
4 NOTES AND REFERENCES
17B DDR SDRAM17C REACH DISPLAY INTERFACE17D PUSH-BUTTONS17E DEBUG LEDS17F MICROSD CARD (2GB)17G RESET CIRCUIT
17I USER INTERFACE BOARD17J USB-TO-RS-232 DEBUG INTERFACE17K LOGIC ANALYZER HEADER
17H USB TYPE-B PERIPHERAL
6F INSTRUMENT FAN #1 CONTROL6E FPGA FAN
6G REACH DISPLAY POWER
21 DATA PATH FPGA DIGITAL DESIGN
9 ANALOG POWER REGULATION - PART 1 OF 29A +5.5V ANALOG SUPPLY REGULATION9B POWER LEDS9C +5.5V FILTER9D +3.3V AIF ANALOG SUPPLY REGULATION9E +5.5V FILTER9F +3.3V AIF ANALOG SUPPLY REGULATION9G +5.5V FILTER9H +3.3V SIGNAL SOURCE ANALOG SUPPLY REGULATION9I +5.5V FILTER9J +3.3V CLOCK DIVIDER ANALOG SUPPLY REGULATION9K +5.5V FILTER9L +3.3V CLOCK ANALOG SUPPLY REGULATION9M +5.5V FILTER9N +5.2V ANALOG SUPPLY REGULATION
7 XILINX FPGA DIGITAL SUPPLY REGULATION AND SEQUENCING7A DIGITAL SUPPLY SEQUENCERS7B POWER LEDS7C GROUND TEST POINTS7D PTH08T220WAZ DISABLE7E +5V DIGITAL SUPPLY REGULATION7F +3.3V DIGITAL POWER SUPPLY7G +1.2V DIGITAL POWER SUPPLY7H +2.5V DIGITAL POWER SUPPLY7I +1.8V DIGITAL POWER SUPPLY7J DDR2/QDR-II VTT/VREF GENERATION7K +1.0V DIGITAL POWER SUPPLY7L SYNC GENERATION CPLD7M CPLD JTAG CONFIGURATION7N 10MHZ REFERENCE LVDS TO LVTTL
8 ASAP DIGITAL POWER REGULATION AND SEQUENCING8A DIGITAL SUPPLY SEQUENCER #18B +1.3V DIGITAL POWER SUPPLY8C DIGITAL SUPPLY SEQUENCER #28D +1.0V DIGITAL POWER SUPPLY8E POWER LEDS8F GROUND TEST POINTS
6H INSTRUMENT FAN #2 CONTROL
43
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SCHEMATIC INDEX
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
DESCRIPTIONDESCRIPTION
A INDEXSHEET/BLOCK
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
SHEET/BLOCK
22 XILINX VIRTEX-5 SX50T CONFIGURATION22B VIRTEX-5 SX50T CCLK22C SYSTEM MONITOR PRECISION REFERENCE22D VIRTEX-5 SX50T FPGA CONFIGURATION MODE22E VIRTEX-5 SX50T FPGA SPI MODE
23 XILINX VIRTEX-5 SX50T I/O23B DDR2/QDR-II REFERENCE
24 XILINX VIRTEX-5 SX50T I/O
25 XILINX VIRTEX-5 SX50T MGT I/O AND POWER INPUTS
26 XILINX VIRTEX-5 SX50T CORE, I/O, & AUXILIARY POWER INPUTS
27 DDR2 SDRAM SODIMM - MT16HTF25664H (2GB)27B DDR2 TERMINATION/POWER INPUTS27C DDR2 TERMINATION DECOUPLING27D DDR2 TERMINATIONS
28 QDR-II SRAM - ADDRESS, DATA, CONTROL28A QDR-II SRAM READ/WRITE DATA28B QDR-II SRAM ADDRESS
29 QDR-II SRAM - POWER AND TERMINATIONS29A QDR-II SRAM DECOUPLING29B QDR-II SRAM TERMINATION DECOUPLING29C QDR-II SRAM WRITE DATA, ADDRESS TERMINATIONS29D QDR-II TERMINATION/POWER INPUTS
30 XILINX VIRTEX-5 SX50T FPGA PERIPHERALS30A PUSH-BUTTONS30B DEBUG LEDS30C USB TYPE-B PERIPHERAL (BACK-UP)30D USB-TO-RS-232 DEBUG INTERFACE30E 100MHZ DIGITAL CLOCK30F MICROSD CARD (2GB)30G LOGIC ANALYZER HEADER
31 SPECTRUM ANALYZER IF AND SIGNAL SOURCE BLOCK DIAGRAMS
32 SPECTRUM ANALYZER IF ESTIMATED PERFORMANCE
33 SPECTRUM ANALYZER IF
33B LNA (+14DBM)33C 1DB PAD33D ANTI-ALIAS FILTER33E 1DB PAD33F PRE-AMPLIFIER (+6DBM)
34 SIGNAL SOURCE34A HIGH-SPEED DAC (16-BITS, 1GS/S)34B OUTPUT STAGE34C ANTI-IMAGE FILTER34D AMPLIFIER
35A TRIGGER INPUT BUFFER35B TRIGGER OUTPUT BUFFER35C +5.5V FILTER35D +2.5V TRIGGER ANALOG SUPPLY REGULATION35E AUXILIARY INPUT
36 ASAPV2 #1 DATA IN/OUT, CONFIG, ANALOG, TEST36A ASAP CONFIG LEVEL TRANSLATE36B ASAP MAIN DATA INPUT AND OUTPUT36C ASAP CONFIGURATION AND TEST PORT36D ASAP ANALOG AND MISCELLANEOUS I/O
37 AGILENT 16902A LOGIC ANALYZER SOFT-TOUCH CONNECTOR37A SOFT-TOUCH SINGLE-ENDED PROBE (E5390A)
38 ASAPV2 #1 POWER SUPPLY INPUTS
39 ASAPV2 #1 POWER SUPPLY DECOUPLING
40 ASAPV2 #2 DATA IN/OUT, CONFIG, ANALOG, TEST40A ASAP CONFIG LEVEL TRANSLATE40B ASAP MAIN DATA INPUT AND OUTPUT40C ASAP CONFIGURATION AND TEST PORT40D ASAP ANALOG AND MISCELLANEOUS I/O
41 AGILENT 16902A LOGIC ANALYZER SOFT-TOUCH CONNECTOR41A SOFT-TOUCH SINGLE-ENDED PROBE (E5390A)
42 ASAPV2 #2 POWER SUPPLY INPUTS
43 ASAPV2 #2 POWER SUPPLY DECOUPLING
33A 3DB PAD
33G HIGH-SPEED ADC (12-BIT, 500MS/S)33H HIGH-SPEED ADC DECOUPLING
34H OPA695 DECOUPLING
34F SIGNAL SOURCE OUTPUT
35 TRIGGER INPUT/OUTPUT AND AUXILIARY INPUT
34E 3DB PAD
34G DAC5682 DECOUPLING
43
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3 001
SCHEMATIC INDEX
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
Data Sheets and User Guides:
TI DAC5682Z 16-bit, 1GS/s:
TI ADS5463 12-bit, 500MS/s:
Xilinx Virtex-5 SX50T:
2. PTH08T260WAZ Data Sheet: http://focus.ti.com/lit/ds/symlink/pth08t260w.pdf
4. TPS79601 Data Sheet: http://focus.ti.com/lit/ds/symlink/tps79601.pdf3. PTH12050YAZ Data Sheet: http://focus.ti.com/lit/ds/symlink/pth12050y.pdf
7. LP2951D Data Sheet: http://focus.ti.com/lit/ds/symlink/lp2951.pdf6. TPS73701 Data Sheet: http://focus.ti.com/lit/ds/symlink/tps73701.pdf5. TPS74201 Data Sheet: http://focus.ti.com/lit/ds/symlink/tps74201.pdf
8. TPS72301 Data Sheet: http://focus.ti.com/lit/ds/symlink/tps72301.pdf
10. TPS3808G25 Data Sheet: http://focus.ti.com/lit/ds/symlink/tps3808g25.pdf
TI Power Supply Regulators:
9. TL7733BCD Data Sheet: http://focus.ti.com/lit/ds/symlink/tl7733b.pdf
1. PTH08T220WAZ Data Sheet: http://focus.ti.com/lit/ds/symlink/pth08t220w.pdf
1. AMC6821 Data Sheet: http://focus.ti.com/lit/ds/symlink/amc6821.pdf
TI High-Speed Op-Amps: THS4302, THS4509, OPA695
1. ADS5463 Data Sheet: http://focus.ti.com/lit/ds/symlink/ads5463.pdf
1. DAC5682Z Data Sheet: http://focus.ti.com/lit/ds/symlink/dac5682z.pdf
Xilinx Spartan-3A XC3S1400A:
1. Data Sheet: http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf2. User Guide: http://www.xilinx.com/support/documentation/user_guides/ug331.pdf3. Configuration Guide: http://www.xilinx.com/support/documentation/user_guides/ug332.pdf
8. System Monitor Guide: http://www.xilinx.com/support/documentation/user_guides/ug192.pdf7. PCB Designer's Guide: http://www.xilinx.com/support/documentation/user_guides/ug203.pdf6. Rocket I/O GTP Guide: http://www.xilinx.com/support/documentation/user_guides/ug196.pdf5. Configuration Guide: http://www.xilinx.com/support/documentation/user_guides/ug191.pdf4. Packaging and Pinout: http://www.xilinx.com/support/documentation/user_guides/ug195.pdf3. User Guide: http://www.xilinx.com/support/documentation/user_guides/ug190.pdf2. DC and Switching: http://www.xilinx.com/support/documentation/data_sheets/ds202.pdf1. Data Sheet: http://www.xilinx.com/support/documentation/data_sheets/ds100.pdf
1. THS4302 Data Sheet: http://focus.ti.com/lit/ds/symlink/ths4302.pdf2. THS4509 Data Sheet: http://focus.ti.com/lit/ds/symlink/ths4509.pdf3. OPA695 Data Sheet: http://focus.ti.com/lit/ds/symlink/opa695.pdf
TI Fan Controllers
Samsung QDR-II SRAM:
1. K7R323684C-EC250 Data Sheet: http://www.samsung.com/global/system/business/semiconductor/product/2007/7/30/948789ds_k7r32xx84c_rev11.pdf
1. AD9516-3 Data Sheet: http://www.analog.com/UploadedFiles/Data_Sheets/AD9516_3.pdf
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
Notes and References
Analog Devices Clock PLL IC:
Micron DDR2 SDRAM SODIMM:
1. MT16HTF25664HY-667E1 Data Sheet: http://download.micron.com/pdf/datasheets/modules/ddr2/HTF16C128 256x64H.pdf
43
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4 001
NOTES AND REFERENCES
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
+
Low Drop-Out
I max = 80mATPS73701
Texas Instruments
Texas Instruments I max = 150mATPS72301
Low Drop-Out
+
N2V5A_AIF
Texas Instruments
TPS73701
Low Drop-Out
+
+
+
Low Drop-Out
1
+
+
+
Texas InstrumentsDC/DC Converter
+
Texas Instruments+
Texas InstrumentsSupply Supervisor
+
+
+
Low Drop-Out
Low Drop-Out
+
+
Texas InstrumentsLow Drop-Out
+
Low Drop-Out
Low Drop-OutTexas Instruments
+
+
Low Drop-Out
Low Drop-Out
+PTH08T220WAZ
+
DC/DC Converter
+
+
+
+
+
+
+
+
+
+
++
PTH08T220WAZTexas InstrumentsDC/DC Converter
PTH08T220WAZ
DC/DC ConverterTexas Instruments
+
Texas Instruments
DC/DC ConverterTexas Instruments
PTH08T220WAZ
PTH08T220WAZTexas InstrumentsDC/DC Converter
Supply SupervisorTexas Instruments
PTH08T220WAZ
DC/DC ConverterTexas Instruments
Texas InstrumentsDC/DC Converter
PTH08T220WAZ
Power Supply125W
12VDC
P12VFP12V_IN
P3V3D
P3V3D_TRACK
DDR/QDR Termination
+
P1V3D_AsAP
P1V0D_AsAP
P1V3DF_AsAP
P1V0DF_AsAP
Low Drop-Out
P1V2D P1V2DF
Bias
TL7733BDC
I max = 5A
I max = 9A
I max = 4A
I max = 250mA
P3V3AF_AIF
I max = 500mA
P1V8AF_SS
PTH12050YAZ
P3V3A_CLK
P1V8A_SS
P3V3A_SS
P3V3A_AIF
Vout
TPS74201
Temp Trim
Vin
Texas Instruments
ReferencePrecisionADR03P12VFD
Texas Instruments
XC9572XL-10VQG44C
Div 32
Reference10MHz
P8VA_VCO
*** PTH08Txxx Sync Gen ***
I max = 200uAP2V5_REF
P3V3D
*** Input Supply Conditioning ***
P2V5D_AsAP_TRACK
1.8V
0V
1.0V
2.5V
1.2V1.3V
Voltage
Time
12V
TPS3808G255.1V
P2V5D
1k
1k
P1V8D
P1V0D
Zener DiodeMMSZ5231BT1G
Digital Power Supply Sequencing
TPS72301
I max = 1A
P5V2AF
I max = 600mA
I max = 500mA
I max = 600mATexas Instruments
P5V5A
PTN78060AAH
P2V5A
N6VA
P2V5AF
N6VAF
P5V5AF P5V2A
I max = 1A
I max = 150mA
P3V3AF_CLK
P3V3AF_SS
P8VA
Low Drop-Out
I max = 50mA
P12VFA
0.9V
234
567
Sync312.5kHzPTH08Txxx
+5V Tolerant I/O
CPLDXilinx, Inc.
TPS73701
TPS73701
TPS73701
N5V2A_SS N5V2AF_SS
P3V3DF
TPS73701
P3V3AF_CLKDIVP3V3A_CLKDIV
P2V5DF_AsAP
I max = 2A
P2V5D
*** AsAP Digital Power Supplies ***UC Davis Confidential Copyright © 2008 VLSI Computation Lab
I max = 2.4A
I max = 720mA
I max = 130mA
I max = 50mA
P5V5AF_CLK
P5V5AF_SS
P5V5AF_CLKDIV
P5V5AF_TRIG P2V5A_TRIG P2V5AF_TRIG
I max = 80mA
Texas Instruments
Texas Instruments
Texas Instruments
LP2951D
TPS73701
TPS73701
Texas Instruments
Texas Instruments
TPS79601
Texas Instruments
Texas Instruments
P5VD*** Measurement Board Digital Power Supplies ***
*** Measurement Board Analog Power Supplies ***
P3V3D_AIF P3V3DF_AIF
I max = 100mA
P5V5AF_AIF
P5V5DF_AIF
PTH08T260WAZ
PTH08T260WAZ
DC/DC Converter
DC/DC Converter
Power GenerationBlock Diagram
P5VDF
I max = 1.05A
I max = 1.24A
I max = 4.95A
I max = 1.3A
I max = 6.25A
Total Power Usage: 75W
89
I max = 4A
P1V0DF
P0V9D_VREF
P0V9D_VTT
P1V8DF
I max = 8A
P2V5DF
I max = 6A
5V
3.3V
N2V5AF_AIF
P2V5A_AIF P2V5AF_AIF
43
3-27-2009_12:24
5 001
POWER GENERATION BLOCK DIAGRAM
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
156MILS
156MILS
156MILS 156MILS 156MILS
156MILS156MILS156MILS156MILS
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
6.8U
2
6.8U
2
LN
J208R8A
RA
1
RE
D
6.8U
2
1
1
2.21
K
1
LN
J308G8L
RA
1
GR
EE
N
0.1U
2
56-OHM
1 2
56-OHM
1 2
0.1U
2
10UH
10UH
42-OHM
1 2
150
1
150
1
LN
J208R8A
RA
1
RE
D
LN
J208R8A
RA
1
RE
D
LN
J208R8A
RA
1
RE
D
2N7002-7-F
D
S2
3
1 G
2N7002-7-F
D
S2
3
1 G MMBT3904-TP
2
3
1
0.0
1
0.0
1
1000
P
2
FAN-FAULT8
THERM7
OVR3
IN+10
IN-9
SMBALERT 14
SDA 15
SCLK 16
A1 12
A0 13
VDD6
TACH 2
PWM-OUT 1
PWM-MODE 11
GND5
NC4
AMC6821SDBQ
Alarm
ADC(11-Bit)MUX
DetectorsSMBus
ICInterface
2
Logic
Tach Counter
Control
0.1U
2
0.1U
2
0.1U
2
6.8U
2
42-OHM
1 2
2.21
K
1
2.21
K
1
1
VERT
6.8U
2
1
LN
J208R8A
RA
1
RE
D
LN
J208R8A
RA
1
RE
D
0.1U
2
0.1U
2
0.1U
2
6.8U
2
42-OHM
1 2
1
VERT
156MILS
156MILS 156MILS
2.21
K
SN74LVC2G14DBV
26-61-4060
1
2
3
4
5
6
FrictionLock
Not Recommended for New Designs.Use 09-65-2068
1
1725656
1
3
4 2
NDT3055L
10K
1
6.8U
2
10UH
2.21
K
SN74LVC2G14DBV
0.0
1
NL
1
NL
1
NL
1
4.75
K1
10K
1
10K
1
NL
1
10K
1
NL
1
10K
1
2.21
K
1
2.21
K
1
2.21
K
1
FAN-FAULT8
THERM7
OVR3
IN+10
IN-9
SMBALERT 14
SDA 15
SCLK 16
A1 12
A0 13
VDD6
TACH 2
PWM-OUT 1
PWM-MODE 11
GND5
NC4
AMC6821SDBQ
Alarm
ADC(11-Bit)MUX
DetectorsSMBus
ICInterface
2
Logic
Tach Counter
Control
2.21
K
1
49.9
1
2.21
K
1
49.9
1
2.21
K
1
49.9
1
0.0
1
0.0
1
MMBT3904-TP
2
3
1
1000
P
2
SN74LVC2G14DBV
SN74LVC2G14DBV
0.1U
2
0.1U
2
2N7002-7-F
D
S2
3
1 G
2N7002-7-F
D
S2
3
1 G
2N7002-7-F
D
S2
3
1 G
150
1
150
1
150
1
10UH
6.8U
2
10K
1
1
3
4 2
NDT3055L
SN74LVC2G14DBV
SN74LVC2G14DBV
0.1U
2
SN74LVC2G14DBV
0.1U
2
2.21
K
1
NL
1
10K
1
10K
1
NL
1
NL
1
NL
1
10K
1
4.75
K1
10K
1
NL
1
0.0
1
2.21
K
1
49.9
1
2.21
K
1
49.9
1
2.21
K
1
49.9
1
SN74LVC2G14DBV
2N7002-7-F
D
S2
3
1 G
42-OHM
1 2
CM5441Z161B-10
1
2
4
3
150
1
Spread out over board - Top & Bottom
-
+
FPGA FanGROUND Tst PtsA +12V SUPPLY INPUT
Place on perimeter of FPGA.
Instrument Fan #1 Control
Instrument Fan #2 Control
D E
F
B +12V Filtering C +12V Analog and Digital Filtering
MAIN POWER INPUT AND FAN CONTROL
(Rated @ 6A)
FBMJ2125HS420-T
(Rated @ 6A)
FBMJ2125HS420-T
Reach Display PWR
MOUNTING HOLES
G
H I
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
Sense
R20
6
FI1
GND_MAIN
P12V_MAIN
L59
Q12
2
16
5
U5
R53
R32
6
R52R
324
R51
R32
5
R503
R542
R114
R21
4
R11
8
R541
R54
3
R54
0
R11
7
R11
6
R53
9
R32
8
C458
34
U5
C457
2
16
5U8
3 4
U8U10
R11
5
C34
0
L50
R21
1
R21
0
R20
9
Q17
Q15
Q16
C460
C459
2
16
5U7
2
16
5U6
C31
4
Q2R508
R507
R54
R33
0
R55
R33
2
R56
R33
1
U50
R33
4
R33
3
R33
5
R12
3
R54
8
R11
9
R54
4
R12
0
R122
R21
5
R54
6
R547 R545
R504
3 4
U7
R42
8
L52
C34
2
R12
1
U11
J70
AMC6821_FAN2_FAULTN
AMC6821_FAN2_OVRNFPGA_AMC6821_FAN2_SCKFPGA_AMC6821_FAN2_SDAFPGA_AMC6821_FAN2_SMBALERTN
FPGA_AMC6821_FAN1_SCKFPGA_AMC6821_FAN1_SDAFPGA_AMC6821_FAN1_SMBALERTN
J69
AMC6821_FAN2_A1AMC6821_FAN2_A0
AMC6821_FAN2_THERMN
FPGA_AMC6821_FAN2_OVRN
FPGA_AMC6821_FAN2_THERMN
FPGA_AMC6821_FAN2_FAULTN
FAN1_TACH
AMC6821_FAN1_A0AMC6821_FAN1_A1
AMC6821_FAN1_FAULTN
AMC6821_FAN1_THERMN
AMC6821_FAN1_OVRN
FPGA_AMC6821_FAN1_OVRN
FPGA_AMC6821_FAN1_THERMN
FPGA_AMC6821_FAN1_FAULTN
GND
GND
P12VF_INP12V_IN
34
U6
R42
7
M11M10
M1
J46
L53
C34
3
C45
6
C45
4
C45
5
D46
D44
J6
C11
6
J45
R32
9
R32
7
L51
C34
1
C45
3
C45
1
C45
2U49
C31
3
R505
R506
Q1Q14
Q13
D43
D42
D41
R20
8
R20
7
L58
L54
L57
C46
2
L109
L110
C46
1
D1
R33
6
J48
TP
31T
P48
P3V3D_FAN1
TP112
FAN2_TACH
15-C1,15-D3
15-C1,15-D3
15-C1,15-D3
P12VF_IN
P12VFD
P12V_IN
P12V_IN
P3V3D_FAN1
P3V3D_FAN1
15-C1,15-D3
P3V3D_FAN1
P3V3D_FAN1 P3V3D
P12VF_FAN1
P12VFD_FAN
TP
10
P12V_IN
GND
TP
30
TP
19
TP
18
TP
17
TP
16
TP
15
TP
14
TP
13
TP
12
TP
11
TP
9
TP
8
TP
7
TP
6
TP
5
TP
4
TP
3
TP
2
TP
1
J47C34
6
P12VFD
P3V3D_FAN1
P3V3D_FAN2
D45
P12VF_FAN2
P3V3DP3V3D_FAN2
P3V3D_FAN2
P3V3D_FAN2
TP
29
TP
28
TP
27
TP
26
TP
25
TP
24
TP
23
TP
22
TP
21
TP
20
15-B5,15-D315-B5,15-D3
14-D4,14-E514-D4,14-E5
15-C1,15-D3
P3V3D_FAN2
P3V3D_FAN2
P12VFA
C34
4C
345
14-D4,14-E1
15-C1,15-D3
15-C1,15-D3
43
4-20-2009_13:35
6 001
MAIN POWER INPUT AND FAN CONTROL
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
TP109TP110
TP111
P12VFDP12VFD_REACH
M2 M3 M4 M5
M9M8M7
M6
M12
1
100U
2
1
3011
LN
J308G8L
RA
1
GR
EE
N
10K
1
2.2U2
1
56.2K
330U
2
330U
2 22U
2
49.9
1
.01
1
1 89
PTH08T260WAZ
10 3 7
6
4
5
2
VO AdjINHIB
TRK SYNC TT
+SENSE
VOUT
-SENSE
VIN
GND
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
49.9
1
49.9
1
1U
2
VCC1
GND2
3 A 4B
R 5
SN65LVDT2DBVR
1
1.91
K
0.1U
2
87832-1420
1
10
11 12
13 14
2
3 4
5 6
7 8
9
VERT
20
1
20
1
20
1
20
1
1
1.91
K
1
1.91
K
0.1U
2
0.1U
2
0.1U
2
I0/GCK143
I1/GCK244
I2/GCK31
I3/GTS136
I4/GTS234
4
GND
17 25
15
VCCINT
35 26
VCCIO
IO02
IO13
IO25
IO36
IO47
IO58
IO612
IO713
IO814
IO916
IO1018
IO1119
IO1220
XC9572XL-10VQG44C
IO13 21
IO14 22
IO15 23
27IO16
28IO17IO18 29
IO19 30
IO20 31
IO21 32
37IO22
38IO23IO24 39
IO25 40
IO26 41
IO27 42
10TMS
24TDOTDI 9
11TCK
I5/GSR33
1K
1
100U
2
5UH
311 8
1 9
6
5
7
2
10
4
PTH08T220WAZ
VO AdjINHIB
TRK SYNC TT
+SENSE
VOUT
-SENSE
VIN
GND
1.1K
1
MMBT3904-TP
2
3
1
LN
J308G8L
RA
1
GR
EE
N
274
1
274
1
1.1K
1
LN
J308G8L
RA
1
GR
EE
N
LN
J308G8L
RA
1
GR
EE
N
MMBT3904-TP
2
3
1
1.1K
1
MMBT3904-TP
2
3
1
680P
2
0.1U
2
2.2U
2
1
56.2K
1
56.2K
1.21
K
1
2.32
K
1
34.8
1
20K
1
1
1
56.2K
TL7733BCDR8
VCC
4
GND
6RESET
7 SENSE
2 RESIN
1REF
3 CT
5RESET
330U
2
330U
2
330U
2
330U
2
330U
2
330U
2
330U
222U
2
100U
2
22U
2
22U
2
1K
1
49.9
1
0.1U
2
10K
1
.01
1
.01
1
.01
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
.01
1
165
1
49.9
1
49.9
1
1K-OHM
274
1
LN
J308G8L
RA
1
GR
EE
N
121
1
311 8
1 9
6
5
7
2
10
4
PTH08T220WAZ
VO AdjINHIB
TRK SYNC TT
+SENSE
VOUT
-SENSE
VIN
GND
.01
1
330U
2 22U
2
4.75
K1
1
56.2K
PTH12050YAZ
14 5
2
63
GNDINHIBIT N/C
VREF
VTTVIN15
0U
2
311 8
1 9
6
5
7
2
10
4
PTH08T220WAZ
VO AdjINHIB
TRK SYNC TT
+SENSE
VOUT
-SENSE
VIN
GND
330U
2
220U
2
4.7U
2
BIAS10
11 EN
16FB
12
GND
IN5678
NC
234
131417
OUT1
181920
PG 9
SS15
TPS74201RGWR
21
PMH
2.32
K
1
4.64
k
1
2.2U
2
4.7U
2
.01
1
5UH
311 8
1 9
6
5
7
2
10
4
PTH08T220WAZ
VO AdjINHIB
TRK SYNC TT
+SENSE
VOUT
-SENSE
VIN
GND
LN
J308G8L
RA
1
GR
EE
N
274
1
1
2.55K
All components close to DC/DC
Place the resistor as close to the regulator as possible.
using dedicated PCB traces.
Connect the resistor directly between pins 7 and 3
All components close to DC/DC
Place the resistor as close to the regulator as possible.
Connect the resistor directly between pins 8 and 4
using dedicated PCB traces.
Place the resistor as close to the regulator as possible.
Connect the resistor directly between pins 8 and 4
using dedicated PCB traces.
Place the resistor as close to the regulator as possible.
Connect the resistor directly between pins 8 and 4
using dedicated PCB traces.
Place the resistor as close to the regulator as possible.
Connect the resistor directly between pins 8 and 4
using dedicated PCB traces.
Spread out over board - Top & Bottom
1.2V, 500mA
0.8V
Equiv. ESR 9.1mOhms
Digital Power Supply Sequence Order:
1.0V Rset = 20.0kOhm, PTH08T220W, Vout = 1.011979 V
A +3.3V Digital Power Supply +1.2V Digital Power Supply
+2.5V Digital Power Supply
+1.8V Digital Power Supply
DDR/QDR VTT/VREF Generation
+1.0V Digital Power Supply
POWER LEDsB
Green LED (LNJ308G8LRA):
RLED = (VCC - VF)/IF
VF = 1.9V IF = 5mA
GROUND Tst Pts
PLACE LEDs NEAR EDGE OF BOARD
Load Jumper to Disable DC/DC Converters
C D
1. +12V Input
1.8V Rset = 4.75 kOhm, PTH08T220W, Vout = 1.806505 V
JTAG HeaderXilinx Platform USB
10MHz Reference LVDS to LVTTL
Digital Supply Sequencers2. +3.3V
3. +2.5V, +1.8V, +1.2V, +1V, DDR VTT/VREF
2.5V Rset = 2.32 kOhm, PTH08T220W, Vout = 2.53 V
3.3V Rset = 1.21 kOhm, PTH08T220W, Vout = 3.303636 V
All components close to DC/DC
All components close to DC/DC
All components close to DC/DC
All components close to DC/DC
Sync Generation CPLD
CPLD JTAG Configuration
PTH08T220WAZDISABLE
F G
H
I
J
K
L
M
N
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
Xilinx Virtex-5 SX50T Digital Supply Regulation and Sequencing
+5V Digital Supply RegulationE
5.0V Rset = 165 Ohm, PTH08T260W, Vout = 5.01 V
CLK10MHZ_CPLD
R303
DIG2_INHIBIT
R49
3
D4
U34
L119 R347
C95
TP
49
C2
R29
3R
642
U20
C94
TP
50
C1
C34
U35
TP
53
TP
54
C68
TP
52
U59
R661
R21
6
C72
C35
R344
U33
P3V3D_TRACK_CTRL_OUT
DIG2_INHIBIT
P2V5D
R16
5
D6
R49
4
L1
P3V3D_TRACK_CTRL
R68
TP126
PTH08T260_SOUT9PTH08T260_SYNC910-E2
PTH08T260_SYNC8R65PTH08T260_SOUT8
PTH08T260_SYNC9
P5VD
P12VD_TRACK_CTRL1
R48
2
R346
CPLD_BOARD_RSTN
CPLD_CLK10MHZ_LVDS_N
CPLD_CLK10MHZ_LVDS_P
TP117
PTH08T220_SYNC7
8-E5
8-C5
PTH08T220_SYNC5
PTH08T220_SYNC6R64
R63PTH08T220_SOUT5
PTH08T220_SOUT6
7-E2
7-D3
R627-A3
PTH08T220_SYNC4
R58
PTH08T220_SOUT3 R617-C3
PTH08T220_SYNC3
TP114
PTH08T220_SYNC2R60
P1V8D
P3V3D_CPLD
P3V3D_CPLDP3V3D
TP125
P3V3D_TPS74201
R345
R343
R342
R12
4
PTH08T220_SYNC4
PTH08T220_SYNC3
PTH08T220_SYNC2
PTH08T220_SYNC1
PTH08T220_SYNC1PTH08T220_SOUT1
DIG_INHIBIT
DIG_INHIBIT
TP
55
C46
4
P12VFD
R57CLK10MHZ_CPLDCLK10MHZ_CPLD_OUT
TP113
NC
CPLD_TMSCPLD_TDOCPLD_TDICPLD_TCK
CPLD_TDICPLD_TDOCPLD_TCKCPLD_TMS
NC
NC
R31
2
C74
C73
C13
C71
C36
C37
C38
C30
C31
C32
C33
U32
R664
J49
R16
3
P1V2D
P0V9D_VTT
R1
R64
3
R94
P3V3D
R663
R662
P2V5D
P1V0D
P3V3D
C14
7
C46
3
P0V9D_VREF
TP
51
C31
8
P1V8D
Q5
R14
4
Q4
P3V3DP3V3D
D5
D3
P3V3D
R14
3
P1V2D
R49
2
R49
1
D2
P3V3D
Q3
R14
2
P1V0D
TP
41
TP
40
TP
39
TP
38
TP
37
TP
36
TP
35
TP
34
TP
33
TP
32
NC
DIG_INHIBIT
DIG_INHIBIT
TP
56
U36
TP
57
L120
C14
R31
3
U57 C46
5
C46
6
C46
7
R70
6
R70
5
R265R264
R263R262
J35
C468
R70
4
P3V3D_CPLD
U51
C39
8
11-C5,11-E5
11-C5,11-E5
TP116
TP115
R59
TP118TP119TP120TP121
TP124TP123TP122
TP130TP129TP128TP127
17-B3,17-E5
PTH08T220_SOUT2
TP131
PTH08T220_SOUT4
TP132
PTH08T220_SOUT7 R669-E2
43
4-20-2009_13:35
7 001
XILINX VIRTEX-5 SX50T DIGITAL SUPPLY REGULATION AND SEQUENCING
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
7-C4
U3
R348
TP
59
R67
C75
C40
C39
R665
TP
58
DIG_INHIBIT
P12VFD
P3V3D_CPLD
C14
8
R12
5
D7
R97
S1CPLD_BUTTONCPLD_LED
7-B1TP133
C4
DIG2_INHIBIT
J7
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
D
1
1 2 3 4 5 6 7 8
2 3 4 5 6 7 8
A
B
C
E
D
A
B
C
E
D
121
1
2 SENSE
MR4
3 CT
GND5
PMH7
6RESET
VDD1
TPS3808G25DRV
2 SENSE
MR4
3 CT
GND5
PMH7
6RESET
VDD1
TPS3808G25DRV
4700
P
2
10K
1
0.1U
2
4700
P
2
5.1V
21
MM
SZ
5231
BT
1G
0.1U
2
0.1U
2
5.1V
21
MM
SZ
5231
BT
1G
4700
P
2
1.1K
1
MMBT3904-TP
2
3
1
LN
J308G8L
RA
1
GR
EE
N
1.1K
1
LN
J308G8L
RA
1
GR
EE
N
MMBT3904-TP
2
3
1
1
1
56.2K
20K
1
1
56.2K
9.76
k
1
311 8
1 9
6
5
7
2
10
4
PTH08T220WAZ
VO AdjINHIB
TRK SYNC TT
+SENSE
VOUT
-SENSE
VIN
GND
330U
2
330U
2
311 8
1 9
6
5
7
2
10
4
PTH08T220WAZ
VO AdjINHIB
TRK SYNC TT
+SENSE
VOUT
-SENSE
VIN
GND
330U
2
330U
2 22U
2
22U
2
.01
1
.01
1
0.1U
2
10K
1
34.8
1
34.8
1
0.0
1
NL
1
121
1
Digital Power Supply Sequence Order:
1. +12V Input
POWER LEDs GROUND Tst Pts
+1.0V Digital Power Supply
+1.3V Digital Power Supply
2. +3.3V
3. +2.5V
4. +1.3V, +1V
All components close to DC/DC
All components close to DC/DC
1.0V Rset = 20.0kOhm, PTH08T220W, Vout = 1.011979 V
A
Digital Supply Sequencer #2
Digital Supply Sequencer #1
CT should be >= 100pFCT can be adjusted to change program time between 1.25ms and 10s
Allow for second level of sequencing if necessary
CT(nF) = {td[s]-(0.5*10^-3[s])}*175
Load Jumper to Disable DC/DC Converters
VF = 1.9V
RLED = (VCC - VF)/IF
IF = 5mA
Green LED (LNJ308G8LRA):
PLACE LEDs NEAR EDGE OF BOARD
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
Spread out over board
B
C D
E F
AsAP Digital Power Regulation and Sequencing
1.0V Rset = 20.0kOhm, PTH08T220W, Vout = 1.011979 V
using dedicated PCB traces.
Connect the resistor directly between pins 8 and 4
Place the resistor as close to the regulator as possible.
using dedicated PCB traces.
Connect the resistor directly between pins 8 and 4
Place the resistor as close to the regulator as possible.
P12VFD
R16
9
TP
67
P2V5D
R552R
510
ASAP_TRACK_CTRL_OUT2R3
R2ASAP_TRACK_CTRL_OUT1
TP
68
R12
6
C47
5NC
R353
R352
PTH08T220_SYNC5
PTH08T220_SYNC6
P2V5DP2V5D
P12VFD
C77
C76
C41
C43
U38
C44
C42
U37
R65
3
R667
R16
4
P1V0D_ASAP
R666
P1V3D_ASAP
ASAP_INHIBIT
J50
Q10
D12
R14
9
P1V3D_ASAP
D11
Q9
R14
8
P1V0D_ASAPT
P47
TP
46
TP
45
TP
44
TP
43
TP
42
ASAP_INHIBIT
TP
66
ASAP_INHIBIT
TP
69
C62
6
P12VFD
D36
P2V5D
C47
6C
478
D37
C62
7
NC
C47
7
R12
7
ASAP_TRACK_CTRL1
C62
8
U14
U15
7-C5
7-C5
TP
70T
P71
R17
0
342
JEREMY W. WEBB
MEAS_MAIN_BOARD
ASAP DIGITAL POWER REGULATION AND SEQUENCING
43
4-20-2009_13:35
8 001
LN
J308G8L
RA
1
GR
EE
N
274
1
10UH
10U
2
2.2U
2
1
30.1
K
52.3k
1
.01
1
1U2
TPS73701DRB
5 EN
OUT 1
3FB
IN8
4
GND NC
29 6 7
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
1U2
2.2U
2
1
30.1
K
52.3k
1
TPS73701DRB
5 EN
OUT 1
3FB
IN8
4
GND NC
29 6 71U2
.01
1
52.3k
1
1
30.1
K
2.2U
2
2.2U
2
1
30.1
K
52.3k
1
.01
1
1U2
LN
J308G8L
RA
1
GR
EE
N
LN
J308G8L
RA
1
GR
EE
N
274
1
274
1
LN
J308G8L
RA
1
GR
EE
N
LN
J308G8L
RA
1
GR
EE
N
274
1
274
1
LN
J308G8L
RA
1
GR
EE
N
10UH
10U
2
10UH
10U
2
10UH
10U
2
10U
2
10UH
4.7U2
4.7U2
.01
1
1
56.2K
330U
2
330U
2
49.9
1
22U
2
1
5.1
681
1
TPS73701DRB
5 EN
OUT 1
3FB
IN8
4
GND NC
29 6 7
.01
1
52.3k
1
1
30.1
K
2.2U
2
TPS73701DRB
5 EN
OUT 1
3FB
IN8
4
GND NC
29 6 7
.01
1
1U2
4.7U2
681
1
110
1
243
1
TPS79601DRB
8 EN 5FB
IN1
2
NC7
OUT3
4
6
GND9
42-OHM
1 2
10UH
10U
2
TPS73701DRB
5 EN
OUT 1
3FB
IN8
4
GND NC
29 6 7
.01
1
1U2
311 8
1 9
6
5
7
2
10
4
PTH08T220WAZ
VO AdjINHIB
TRK SYNC TT
+SENSE
VOUT
-SENSE
VIN
GND
+5.5V Filter
ShieldedIsat: 9.36A
DCR: 21.8mOhm
3.3V, 500mA
+3.3V30.1k52.3k
R1 R2 Vout1.2V
3.3V, 500mA
+3.3V30.1k52.3k
R1 R2 Vout1.2V
1.2V
VoutR2R1
52.3k 30.1k +3.3V
3.3V, 500mA
+3.3V30.1k52.3k
R1 R2 Vout1.2V
1.2V
VoutR2R1
ShieldedIsat: 9.36A
DCR: 21.8mOhm
ShieldedIsat: 9.36A
DCR: 21.8mOhm
ShieldedIsat: 9.36A
DCR: 21.8mOhm
DCR: 21.8mOhmIsat: 9.36AShielded
ShieldedIsat: 9.36A
DCR: 21.8mOhm
+5.5V Filter
using dedicated PCB traces.
Connect the resistor directly between pins 8 and 4
Place the resistor as close to the regulator as possible.
All components close to DC/DC
B POWER LEDs
PLACE LEDs NEAR EDGE OF BOARD
Green LED (LNJ308G8LRA):
RLED = (VCC - VF)/IF
VF = 1.9V IF = 5mA
52.3k 30.1k +3.3V
3.3V, 600mA
3.3V, 600mA
Vout = 1.21 * (1 + (R1/243)) = 5.210849383 V
All components close to TPS79601 All components close to TPS79601
A +5.5V Analog Supply Regulation
+3.3V Signal Source Analog Supply Regulation+5.5V Filter
+3.3V Clock Divider Analog Supply Regulation+5.5V Filter
+3.3V Clock Analog Supply Regulation+5.5V Filter
+5.2V Analog Supply Regulation+5.5V FilterPower Dissipation = (5.5V - 5V)*1A = 500mW
D
All components close to DC/DC
+3.3V AIF Digital Supply RegulationE F
G H
I J
K L
M N
C +3.3V AIF Analog Supply Regulation5.5V Rset = 100 Ohm, PTH08T220W, Vout = 5.498027315 V
Analog Power Regulation - Part 1 of 2
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
U39
TP
89
TP
84
C40
3
R358
U94
C11
7
L67L16
U47
R31
8
R4R340
C99
C40
0
NC
R354
P12VA_TRACK_CTRL1
TP
81
TP
80
U92
P3V3A_CLK
C6
R30
7
R656
R355
TP
78
NC
U91
R33
9
P5V5A
TP
75
R18
P5V5AF_AIF
C78
R69
C46
C45
R668
TP
91
TP
90
P12VFA
R360
P3V3A_AIF
ANLG_INHIBIT
PTH08T220_SYNC7
C10
0
P5V2ATP
73
TP
72
C98
P3V3A_CLKDIV
P3V3A_SS
TP
74
L62
C11
8
P5V5AF_SS
P5V5AF_CLKDIV
C11
9
L63
P5V5AF_CLK
C12
0
L64
TP
76
P5V5AF
C12
1
L65
TP
77
7-C5
D13
R49
5
P3V3A_AIF P3V3A_SS
R49
6
D14
D15
R49
7
P3V3A_CLKDIV P3V3A_CLK
R49
8
D16
D17
P5V2A
TP
79
NC
NC
NC
NC
C40
1
R356
R657
R30
8 C7
C8
R30
9
R658
R357
C40
2
NC
NC
NC
U93TP
83
TP
82T
P85
NC
NC
NC
R659
R31
0 C9
NC
C40
4
43
4-20-2009_13:35
9 001
ANALOG POWER REGULATION - PART 1 OF 2
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
TP
87
TP
86
U95
NC
NC
NC
C40
5
R359
R660
R31
1 C10
P3V3D_AIFP5V5DF_AIF
C12
2
L66
TP
88
P3V3D_AIF
R49
9
D18
274
LN
J308G8L
RA
1
GR
EE
N
LN
J308G8L
RA
1
GR
EE
N
1U
2
1U
2
82
1
36.5
K
5.62K1
34K
1
10UH
10U
2
TPS73701DRB
5 EN
OUT 1
3FB
IN8
4
GND NC
29 6 7
.01
1
2.2U
2
1U2
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
2.2U
2
MMBT3904-TP
2
3
1
681
1
LN
J308G8L
RA
1
GR
EE
N
LN
J308G8L
RA
1
GR
EE
N
1U
2
1
1.21
K
1
17.4K
1
274
1 274
10UH
10U2
1U
2
1U
2
.01
1
TPS72301DBV
EN3
OUT 5IN2
GND1
FB 4
1U
2
1U
2
1U
2
16.5
K
1
TPS72301DBV
EN
OUTIN
GND
FB
18.2K
1U
2
1U
2
1U
2
16.5
K
10U
2
100P
2
549K
1
100K
1
1U210U
2
390-OHM
1
56.2K
10UH
10U2
.01
1U
2
1U
2
10UHTPS72301DBV
EN3
OUT 5IN2
GND1
FB 4
PTN78060AAH
1
2
3 4 5
6
7VOUT
NC
VIN
VO AdjNC
VOUT
GND.01
1
150U
2
4.7U2
4.7U2
4.7U2
4.7U
2
150U2
4.7U2
10U2
.01
1
1U
2
16.5
K
1
1
56.2K 1U
2
1U
2
1U
2
1U
2
1.1K
1
LN
J308G8L
RA
1
GR
EE
N
.01
1
330U
2 22U
2
.01
1
1 89
PTH08T260WAZ
10 3 7
6
4
5
2
VO AdjINHIB
TRK SYNC TT
+SENSE
VOUT
-SENSE
VIN
GND
49.9
1
1
56.2K
330U
2
100U
2
10UH
10U
2
1U2
1
56.2
K
28.7K
1
2.32
K
1
.01
1
TPS73701DRB
5 EN
OUT 1
3FB
IN8
4
GND NC
29 6 7
4
GND
3 SHD
7
FBVTAP6
OUT 1
2SENSE
IN8LP2951D
ERROR 5
ShieldedIsat: 9.36A
DCR: 21.8mOhm
Vout = -1.186 * (1 + (R1/R2)) = -5.22558788 V
Isat: 9.36AShielded
Vout = -1.186 * (1 + (R1/R2)) = -2.500088 V
R1 R2 Vout
36.5k39.62k +2.51V
1.2V
ShieldedIsat: 9.36A
DCR: 21.8mOhm
+5.5V Filter +2.5V AIF Analog Supply Regulation
2.5V, 200mA
R1 R2 Vout
1.2V
POWER LEDs
DCR: 21.8mOhmIsat: 9.36AShielded
+8V Analog Supply Regulation
ShieldedIsat: 9.36A
DCR: 21.8mOhm
Debug
All components close to DC/DC
Place the resistor as close to the regulator as possible.
using dedicated PCB traces.
Connect the resistor directly between pins 7 and 32.5V Rset = 2.32 kOhm, PTH08T260W, Vout = 2.53 V
-6V Rset = 17.3 kOhm, PTN78060A, Vout = -6V
-6V Analog Supply Regulation
Vout = -1.186 * (1 + (R1/R2)) = -5.22558788 V
All components close to DC/DC
All components close to DC/DC
All components close to DC/DC
-5.2V Analog Supply Regulation
+1.8V Analog Supply RegulationB +2.5V Analog Supply Regulation+12V AnalogA C
D E
F
IF = 5mA
RLED = (VCC - VF)/IF
VF = 1.9V
Green LED (LNJ308G8LRA):
PLACE LEDs NEAR EDGE OF BOARD
1.8V, 1A
28.7k 56.2k +1.818V
G
All components close to LP2951D
Power Dissipation = (12V -8V)*60mA = 240mW
Vout = 1.235 * (1 + (R1/100k)) = 8.01515 V
All components close to LP2951D
Analog Power Regulation - Part 2 of 2
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
H I
DCR: 21.8mOhm
KJ -5.2V AIF Analog Supply Regulation -2.5V AIF Analog Supply Regulation
U24
U96
R365
R64
4
TP
99
R595
R67
0
C41
2
C12
4
TP
95
L69
TP
102
L84
FERRITE BEAD1.2A, 390R
C5
C47
R671R70
U4
R361
C79
C48
TP
103
R363
D21
R15
0
C40
8
C40
6
C40
7
C40
9
R669
R67
6
C41
1
R364
TP
94
C12
3
C10
3
C70
C101
C10
5
C10
2
C10
4
C69
R362
U60
TP
93
U17
TP
97
L68
TP
92
C61
C60
TP
240
R375
TP
241
C55
L13
R389
TP
239
L83
1.2A, 390R
TP
244
TP
101
C12
5
C32
1
R74
3R
292 C
20
C12
6
TP
100
R39
1
C96
C93
C66
R3784
1
2 5
3
U26
R39
2
C97
C11
4
C13
7
TP
243
U27R376
C13
9
C14
5
TP
242
C56
L14
R38
5R50
0
N6VAF_SS_INN6VAF_SS
N6VAF_AIFN6VA
N6VA
NC
N6VA_OUT
R19
P12VA_TRACK_CTRL2
P1V8A_SS
P3V3A_SS
N5V2A_SS
N5V2A_SS
R96
7-C5
P2V5A
P12VFA
P8VA_CLKDIV
P1V8A_SS
NC
J51
ANLG_INHIBIT
ANLG_INHIBIT
NC
C41
0
TP
96
D20
D19
P8VA_CLKDIV
R34
1
Q11
NC
NC
NC
TP
98
C11
43
4-20-2009_13:35
10 001
ANALOG POWER REGULATION - PART 2 OF 2
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
C59
P2V5A_AIF
C53
R374
TP
238
U61P5V5AF_THS4302
C54
L12
TP
237
TP
236
P5V5A
R373 R394
R39
3
NC
NC
NC
N2V5A_AIFN5V2AF_AIF
R390
C67
N5V2AF_AIF_INN5V2A_AIF
C11
5
N6VAF_AIF_IN
N2V5A_AIF
D9
D8
P2V5A_AIF
R38
6
NC
NC
PTH08T260_SYNC8
1367-000-G91P-61
1367-000-G91P-61
1U
2
1U
2
1K-OHM
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
1U
2
1U
2
1U
2
49.9
1
49.9
1
75
1
75
1
49.9
1
1U
2
1U
2
75
1
75
1
75
1
0.1U
2
0.1U
2
75
1
1
100
100K
1
0.0
1
49.9
1
1U
2
1U
2
1U
2
0.1U2
1U
2
1U
2
1U
2
1U
2
1K
1
1K
1
1K
1
1K
1
1U
2
1U
2
1U
2
1U
2
1U
2
1U
2
1U
2
1U
2
1U
2
1U
2
1U
2
1U
2
1.62
K
1
1
56.2
K 100K
1
10K
1
1.62
K
1
33
1
BAV199DW-7-F
1
2
3 4
5
6
1
PGB10603
26.1
1
1000
0P
2
56P
2
1
10
11
12
13
14 15
16
17
2
3
4
5
6 7
8
9
SY58011UMGIN
Vt
/IN
Vref-AC
VCC
/Q1
/Q0
Q0
Q1
GND PMH
5P
RIM
42N
D3
2ND
_DO
T
2N
C
1P
RIM
_DO
T
MA
BA
-007
159-
0000
00
0.0
1
0.1U
2
1
2
3
4
5 6
7
8
9
10
VTC2-J02C-10M00
10.000MHz
OSC
TCXONCNCNCGND
VccENNCNC
OUT
NC
1U
2
1
10
11
12
13
14
15
16 17
2
3 4
5
6
7
8
9
ONET1191PRGTT
PMH
VAR
DISABLE
VCC
C0C+C0C-
DIN+DIN-
TH
GND
LOS
DOUT-
DOUT+
49.9
1
75
1
75
1
42-OHM
1 2
1U
2
1
10
11
12
13
14 15
16
17
2
3
4
5
6 7
8
9
SY58608UMGIN
Vt
/IN
Vref-AC
VCC
/Q1
/Q0
Q0
Q1
GND PMH
1
2 3
4
OSC
GND
Vdd
OUT
E/D
10MHz
HCMOS
0.0
1
NL
1
1234
65 7 8
9101112
13141516
3X3mmQFN
NB4N527SVTD1D1
VTD1
GN
DN
CN
CV
cc
Q1Q1Q0Q0
D0
D0
VT
D0
VT
D0
D1
SY58017UMG
1
10 11
12
13
14 15
16
17
2
3
4
5
6
7
8
9
Q
/Q
/IN0
Vt0
IN0
IN1
Vt1
/IN1
PMHSEL
GND
NC
VCC
SY58017UMG
1
10 11
12
13
14 15
16
17
2
3
4
5
6
7
8
9
Q
/Q
/IN0
Vt0
IN0
IN1
Vt1
/IN1
PMHSEL
GND
NC
VCC
SY58017UMG
1
10 11
12
13
14 15
16
17
2
3
4
5
6
7
8
9
Q
/Q
/IN0
Vt0
IN0
IN1
Vt1
/IN1
PMHSEL
GND
NC
VCC
MC10EP89DTG1
2
3
45
6
7
8 VCC
VEE
Q0
Q1D
D Q0
Q1
1
101112
13141516
234
5 6 7 8
9
3X3mmVTDDDNVTDN
Q0Q0N
Q1Q1N
VC
CV
EE
VE
EV
CC
VC
CV
RE
FA
CV
EE
VC
C
Diff/Buffer
QFN
R1
** INPUTS **
10MHz Reference Clock Input
LAYOUT
FBMJ2125HS420-T
(Rated @ 6A)
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
10 MHz Reference Clock GenerationA
D
B CML-LVDS Translator
C
EXT_CLK10MHZ_ENABLE
CLK10MHZ_SELECT
10MHz Control
10MHz Reference Clock Generation10MHz Outputs
** OUTPUTS **
10MHz Output Buffer
LVDS 1:2 Fan Out
R1
R2
R2
-OR-
Place Resistors close to eachother to minimize the stub.
INT_CLK10MHZ_ENABLE
10MHz Reference Clock Output
LAYOUT
EXT_CLK10MHZ_IN_DISABLE
CLK10MHZ_REF_INT_LVDS_NCLK10MHZ_REF_INT_LVDS_P
CLK10MHZ_INT_BUF_NCLK10MHZ_INT_BUF_P
FOX_10MHZ_REF
VECTRON_10MHZ_REF
CLK10MHZ_REF_OSC
U25
CPLD_CLK10MHZ_LVDS_NCPLD_CLK10MHZ_LVDS_P
CLK10MHZ_REF_INT_LVDS_P
CLK10MHZ_REF_INT_LVDS_N
FPGA_EXT_CLK10MHZ_REF_N
FPGA_EXT_CLK10MHZ_LOS
CLK10MHZ_EXT_BUF_NCLK10MHZ_EXT_BUF_P
FPGA_CLK10MHZ_REF_CTRL0
U76
CLK10MHZ_REF_P
CLK10MHZ_REF_N
CLK10MHZ_REF_PCLK10MHZ_REF_N
U29
U30
EXT_CLK10MHZ_REFCLK10MHZ_REF_OUT
FPGA_CLK10MHZ_REF_CTRL2
FPGA_CLK10MHZ_REF_CTRL3
U28
U23
P2V5D_10MHZREF
R467
R466
U21
P2V5D
U79
FPGA_EXT_CLK10MHZ_LOS11-B1,11-E5,15-B1,15-D1
FPGA_EXT_CLK10MHZ_REF_P
FPGA_INT_CLK10MHZ_REF_P
CPLD_CLK10MHZ_LVDS_P
CLK10MHZ_REF_AD9516_PCLK10MHZ_REF_AD9516_N
11-A2,11-E5,12-D1,12-E111-A2,11-E5,12-D1,12-E1
7-A4,11-C5,11-E57-A4,11-C5,11-E5
11-C5,11-E5,15-E111-C5,11-E5,15-E1
11-D5,11-E5,15-D1,15-E111-D5,11-E5,15-D1,15-E1
CLK10MHZ_REF_AD9516_P
CLK10MHZ_REF_AD9516_N
FPGA_EXT_CLK10MHZ_REF_P
11-B1,11-C1,11-E1,15-B115-D5
FPGA_CLK10MHZ_REF_CTRL[3:0]
FPGA_CLK10MHZ_REF_CTRL1
C43
1
FPGA_INT_CLK10MHZ_REF_NFPGA_INT_CLK10MHZ_REF_P
P3V3A_10MHZREF
L17
R68
3
R68
4
R221
CLK10MHZ_REFOUT_N
CLK10MHZ_REFOUT_P
CLK10MHZ_INT_BUF_PCLK10MHZ_INT_BUF_N
CLK10MHZ_EXT_BUF_NCLK10MHZ_EXT_BUF_P
P3V3A_10MHZREF
P3V3A_10MHZREF
U9
P3V3A_CLK
C43
8
U78
P3V3A_10MHZREF
P3V3A_10MHZREF
C159
R484
T1
U31
C25
C85
0
R715
D35
D48
R689
P3V3A_10MHZREF
P3V3A_10MHZREF
P3V3A_10MHZREF
P3V3A_10MHZREF
R64
8
R128
P3V3A_10MHZREF
R74
4
R67
2
R64
7
C43
0
C42
9
C42
8
C42
7
C42
6
C42
5
C42
4
C42
3 C42
2
C42
1
C42
0
C41
9
R317
R316
R315
R314
C41
8
C41
7
C41
6
C41
5
C15
8
P3V3A_10MHZREF
C41
4
C41
3
C43
2
P3V3A_10MHZREF
R72
R485
R74
5
R6
R68
0
C161
C160
R67
9R
678
R67
7
C43
4
C43
3
R71
R68
2
R68
1
R222
R223
C43
5
C43
6
C43
7
FPGA_EXT_CLK10MHZ_REF_N
FPGA_INT_CLK10MHZ_REF_N
CPLD_CLK10MHZ_LVDS_N
@SHEETTOTAL=43
4-20-2009_13:35
@SHEET=11 REVISION=001
10MHZ REFERENCE CLOCK GENERATION
MEAS_MAIN_BOARD
JEREMY W. WEBB
PCBNUMBER=342
L132
C85
2
C85
1
P3V3A_10MHZREF
EXT_CLK10MHZ_REFOUTJ57
J56
P3V3A_10MHZREF
GND
SMP
GND
SMP
0.0
0.0
0.0
0.0
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
130
1
130
1
27.4
1
27.4
1
56.2
1
56.2
1
56.2
1
0.1U 2
0.1UFA B
G1 G2
0.1U 2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1U 2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
1U2
1U
2
1U
2
1U
2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
1
100
0.1U 2
1U
2
1
10
11
12
13
14
2
3
4
5
6 7
8
9
GN
D
GN
D
GND
VCC
GND
RF
GND
GN
D
GN
D
GND
NC
GND UMX-244-B14CRO1GHz
VT
GND
0.1U
2
1K-OHM
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1U 2
42-OHM
1 2
100P
2
56.2
1
130
1
130
1
27.4
1
75
1
75
1
75
1
75
1
49.9
1
0.1U
2
0.1U
2
0.22
U
2
1
100
0.15
U
2
4.7U2
4.7U2
0.01
5U2
0.0
1
1
100
0.1U
2
0.1U
2
100P
2
1
200
1
200
1
200
5.11K
1
4.02K
1
100
1
NL
1
1K-OHM
1
100
1
100
1U
2
1U
2
42-OHM
1 2
MC10EP89DTG1
2
3
45
6
7
8 VCC
VEE
Q0
Q1D
D Q0
Q1
524-001-11Shield
27.4
1
AD9516-3BCPZ
65
1111230313238495051576061
64
63
16
17
21
22
13
14
37 44 59
56
55
53
52
43
42
40
39
25
26
28
29
48
47
46
45
33
34
35
36
9
5
58
62
4
6
2
3
274154
15
18
19
20
7
8
10
24
23
REFINREFINB
SCLK
SDO
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
STATUS
VCP
CPRSET
RSET
CS
SDIO
CLKCLK
GND PMH
OUT1
OUT0
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8OUT8
OUT9OUT9
CPLF
REFMONLD
VS VS_LVPECL
NCNCNCNC
REF_SEL
SYNC
BYPASS
PD
RESET
0.0
100P
2
100P
2
1
200
0.0
under-shoot on clocks.need to dampen over- orZero Ohm used in case we
under-shoot on clocks.need to dampen over- orZero Ohm used in case we
Place near FPGA
250MHz, LVPECL
250MHz, LVDS
500MHz, LVPECL
LVDS FPGA Inputs
AD9516 High-Speed Clock Generation PLL
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
(Rated @ 6A)
FBMJ2125HS420-T
HIGH-SPEED CLOCK GENERATION
10 MHz Reference Clock Buffer
10MHz Reference
High-Speed Clock Outputs (LVPECL)
High-Speed Clock Outputs (LVDS)
(Rated @ 6A)
FBMJ2125HS420-T
+8V Analog: I = 27mA
** INPUTS **
AD9516 Control
Large Swing ECL Driver
B C
Vidiff = 0.1V to 1.5V
Vicm = 0.6V to 2.2V
Vodiff = 790mV
Vocm = 1.12V
Vocm = 1.335V
Vodiff = 600mV
CLKVDD = 1.8V
Vidiff = 0.5V to 1V
Vicm = 0.9V
Vocm = 920mV
Vodiff = 960mV
+3.3V Clock: I = 455mA max
+2.5V Clock: I = 300mA max
Place near FPGA
** OUTPUTS **
AD9516 Control
AD9516 Status Signals
D AD9516 LVPECL Clock Terminations E AD9516 Main Power Supply Decoupling
Vicm = 0.6V to 2.2V
Vidiff = 0.1V to 1.5V
VCCO_3 = 2.5V
Vocm = 1.12V
Vodiff = 790mV
VS_LVPECL = 3.3VVS_LVPECL = 3.3V
VS_LVPECL = 3.3VVS_LVPECL = 3.3V
Place near AD9516
Place near AD9516 Place near DAC5682
Place near ADS5463
AVDD = 5.2V
Vidiff = 0.5V to 5V
Vicm = 2.4V
100 Ohm Termination
located on DAC Sheet
located on ADC Sheet
100 Ohm Termination
A AD9516 LVPECL Power Supply Decoupling
VCCO_3 = 2.5V
Place as close as
possible to FPGA Pins
possible to FPGA Pins
Place as close as
Terminated in FPGA Fabric
Virtex 5 Bank 4
AD9516 Test Clock Output
TEST_CLK_NTEST_CLK_P
FPGA_ASAP_CLK_N
R380
R71
8
C65
C64
R379
U53
R297
2 3 4 5 61SH1
U77
L18
C44
5
C44
4
R11
R7
L3
R553
R691R483
R319
R71
9R
717
R71
6
C62
C173
C177R10
R486
C32
8
C10
6
C10
7
C39
7
R9
CLK10MHZ_REF_AD9516_N
C31
0
C174
C175
R224
R68
7
R68
6R
685
R68
8
FPGA_ASAP_CLKIN_P
FPGA_DSP_CLKIN_N
P3V3A_AD9516
P3V3A_AD9516
FPGA_DSP_CLK_N
FPGA_DSP_CLK_P
P3V3D_V5
12-C3,12-E5,22-E1,22-E312-C3,12-E5,22-E1,22-E3
12-A3,12-E5,22-E1,22-E312-A3,12-E5,22-E1,22-E312-B2,12-E5,33-C312-B2,12-E5,33-C312-A2,12-E5,34-E112-A2,12-E5,34-E1
12-D5,15-C3,15-D112-E5,15-C3,15-D112-E5,15-C3,15-D1
12-E5,15-C3,15-D1
FPGA_ASAP_CLK_P
R296
P3V3D_V5
R20
2
R20
3
R72
2
C63
L19
P3V3A_AD9516
AD9516_10MHZ_REF_N
AD9516_10MHZ_REF_P
C167
C633C635
C632C631C629 C630
L2
P5V2A
P5V2A_VCO
NC
P8VA_CLKDIVP8VAF_VCO
P3V3A_CLKDIVREF
CLK10MHZ_REF_AD9516_NCLK10MHZ_REF_AD9516_P
12-C3,12-E5,22-E1,22-E312-C3,12-E5,22-E1,22-E3
11-A2,11-E5,12-D1,12-E111-A2,11-E5,12-D1,12-E1
12-E1,15-C3,15-C5
12-E1,15-C3,15-C512-E1,15-C3,15-C512-E1,15-C3,15-C5
FPGA_AD9516_LD
FPGA_AD9516_SDO
12-E1,15-C3,15-C5
12-E1,15-C3,15-C5
FPGA_SDRAM_CLK_NFPGA_SDRAM_CLK_PFPGA_SRAM_CLK_NFPGA_SRAM_CLK_P
12-B3,12-E5,22-E1,22-E3
FPGA_AD9516_STATUSFPGA_AD9516_REFMON
SS_DAC_CLKIN_NSS_DAC_CLKIN_P
AIF_ADC_CLKIN_PAIF_ADC_CLKIN_N
CLK10MHZ_REF_AD9516_P
AD9516_BYPASS
NC
SS_DAC_CLK_N
SS_DAC_CLK_P
AD9516_1GHZ_VCO_OUT
AD9516_1GHZ_VCO_OUTC176
U80
C44
3
C168
R8
AIF_ADC_CLK_P
AIF_ADC_CLK_N
C165
C166
C172
C171
C170
C169
P3V3A_AD9516P3V3A_CLKDIV
C44
2
C44
1
C44
0
P3V3A_CLKDIV
NC
12-B3,12-E5,22-E1,22-E3FPGA_ASAP_CLKIN_NFPGA_ASAP_CLKIN_P
FPGA_DSP_CLKIN_NFPGA_DSP_CLKIN_P
FPGA_AD9516_RESETFPGA_AD9516_PDFPGA_AD9516_SYNCFPGA_AD9516_REF_SEL
12-E1,15-C5,15-E3
FPGA_AD9516_SDIOFPGA_AD9516_CSBFPGA_AD9516_SCLK
P5V2A_VCO
C43
9
C636 C634 C637 C638
C639 C640
TP134TP135TP136TP137
TP138
TP139
TP140
TP141
TP142
TP143TP144
C164
C643C642
C163
C641
C162
R72
3R
725
R72
4
R298
R299
R20
5
R20
4
FPGA_ASAP_CLKIN_N
FPGA_DSP_CLKIN_P
43
4-20-2009_13:35
12 001
HIGH-SPEED CLOCK GENERATION
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
R382
R381AIF_ADC_CLKIN_P
AIF_ADC_CLKIN_N
SS_DAC_CLKIN_N
SS_DAC_CLKIN_P
R384
R383
J4
J3
NCNCNCNC
NCNC
FPGA_SDRAM_CLK_NFPGA_SDRAM_CLK_P
FPGA_SRAM_CLK_NFPGA_SRAM_CLK_P
NCNC
NCNC
FPGA_DSP_CLK_NFPGA_DSP_CLK_P
FPGA_ASAP_CLK_NFPGA_ASAP_CLK_P
SS_DAC_CLK_NSS_DAC_CLK_P
AIF_ADC_CLK_NAIF_ADC_CLK_P
FPGA_AD9516_STATUS
FPGA_AD9516_REFMONFPGA_AD9516_LD
FPGA_AD9516_RESET
FPGA_AD9516_PD
AD9516_BYPASS
FPGA_AD9516_SYNC
FPGA_AD9516_REF_SEL
FPGA_AD9516_SDIOFPGA_AD9516_SDOFPGA_AD9516_CSBFPGA_AD9516_SCLK
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
Control FPGA Digital Design
43
3-27-2009_12:24
13 001
CONTROL FPGA DIGITAL DESIGN
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
221
1
221
1
221
1
4.99
K
1
4.99
K
1
NL
1
NL
1
NL
1
NL
1
NL
1
NL
1
1
76SB03T
12
3
-OP
EN
-
ROCKER
4.99
K
1
4.99
K
1
1
76SB03T
12
3
-OP
EN
-
ROCKER
NL
1
NL
1
NL
1
NL
1
NL
1
NL
1
4.99
K
1
4.99
K
1
1
0.0
1
20
120
120
1
0.0
1
0.1U
2
1
1.91
K
0.1U
2
0.1U 2
0.1U 2
0.1U 2
LN
J308G8L
RA
1
GR
EE
N
0.1U
2
SN74LVC1G32DCKR
1
24
3
5VCC
AB
Y
GND
1
61.9
87832-1420
1
10
11 12
13 14
2
3 4
5 6
7 8
9
VERT
87832-1420
1
10
11 12
13 14
2
3 4
5 6
7 8
9
VERT
20
1
20
1
20
1
20
1
20
1
4.99
K
1
4.99
K
1
1
1.91
K
1
1.91
K
1
1.91
K
1
0.0
1
Y19 DONE/VCCAUXC4 PROG_B/VCCAUXD4 TMS/VCCAUX
A21 TCK/VCCAUXE19 TDO/VCCAUX
F5 TDI/VCCAUX
W5 IO_L01N_2/M0V6 IO_L01P_2/M1W4 IO_L02P_2/M2Y8 IO_L11N_2/VS0
W8 IO_L11P_2/VS1W9 IO_L09N_2/VS2
V13 IO_L26P_2/INIT_BY4 IO_L02N_2/CSO_B
AA20 IO_L36N_2/CCLKAB14 IO_L22N_2/MOSI/CSI_B
Y9 IO_L14P_2/D7AB9 IO_L14N_2/D6Y11 IO_L16P_2/D5
AB11 IO_L16N_2/D4
U13 IO_L26N_2/D3AA17 IO_L28P_2/D2
Y17 IO_L28N_2/D1AB20 IO_L36P_2/D0/DIN/MISO
V9 IO_L09P_2/RDWR_BAA15 IO_L24N_2/DOUT
XC3S1400A-4FGG484C(4 of 4)
4
4
4
4
4 4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
221
1
0.1U
2
0.01
0.01
0.0
1
LN
J208R8A
RA
1
RE
D
1
61.9
4.99
K
1
332
1
5.11
K
1
5.11
K
1
0.1U2
1
2
3
4
5
SN74LVC1G08DCKR
VCC
AB
Y
GND
TPS3823-33DBV
1
2
3
4
5
GND
VDD
WDI
MR
RESET
0.1U2
20
1
4.99
K
1
0.01
M25P64-VMF6TP
14
13
12
11
6
5
4
3
8
2
10
15
16
7
9
1
NCNCNCNC
VCC
Hold
Q
NCNCNCNC
VSS
D
CLK
Select
W/Vpp
Temp Sensor Col. 1
AsAP 2 Config Input
V5 Data
VS2 VS1 VS0 READ CMD
Fast Read
Read
Read Array
1
1
1
OTHERS
HEX CMD CODE
0x0B
0x03
0xE8
RESERVED
1
0
1
0
1
1
8, 16 bits Output
Output1 bit
CCLK Direction
Output1 bit
DATA WIDTH
Master Serial
M2CONFIG MODE
Slave Serial
Input (TCK)
Input
Input
1 bit
8, 16, 32 bits
1 bit
1 0
10
0Master BPI-Up
Master SPI 1
1
101
10
0
0 0 0
M0M1
1 1 1
1 1 0
RSVD
RSVD
JTAG
Slave Parallel
RSVD
RSVD
RSVD
RSVD
For more information see Xilinx Spartan 3A Configuration Guide (UG332)
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
TOFROM
JTAG Cable
must be placed near the Configuration PROM.
transmission line.
and is a 50 Ohm controlled impedance
FPGA_CCLK requires an end termination
FPGA_CCLK Stub Length from S3A to SPI Flash < 12.5 mm
NOTES:MASTER JTAG CHAIN MAPPING
Xilinx Platform USBJTAG Header
The end termination
Xilinx Platform USBSPI Header
Configuration SPI Flash PROM / JTAG InterfaceA
B C
RE-PROGRAMPUSH TO
Configuration starts on rising edge.Holds off configuration while low.
eachother with Silkscreen Labels.Place Green and Red LED next to
0 0
CPU Interrupts
** INPUTS ** ** OUTPUTS **
CPU Interrupts
S3A Control
S3A Control
JTAG Cable
V5 Data
Virtex 5 SX50T: VCCO_0 = 3.3V, VCCO_2 = 3.3VSpartan 3A: VCCO_2 = 3.3V, VCCAUX = 3.3V
Xilinx Spartan-3A Control FPGA Configuration
Spartan-3A FPGA CONFIG MODE Spartan-3A FPGA SPI MODE
AMC6821 Fan #2 Control
FT245BL USB Interface
AMC6821 Fan #2 Control
4314
MEAS_MAIN_BOARD
TP
278
TP
279
TP
253
TP
146
U16
R515
R72
9
R274
FPGA_PROG_B
C487
U45U54
C481
R32
1
R32
0
R29
5
R73
6
R11
1
D47
R517
R514
R511
TMS
C485
NCNC
S3A_V2
TP
145
P3V3D
P3V3D
FPGA_TMPSENS_1C_CSN14-D4,14-E5,20-E1,20-E2
FPGA_ASAP2_RST_CNTCLK14-D4,14-E5,40-D1,40-E1
FPGA_AMC6821_FAN2_SDAFPGA_AMC6821_FAN2_SCK
FPGA_FTDI_RDN
6-A4,14-D4,14-E56-A4,14-D4,14-E5
14-D4,14-E5,17-B5,17-D1
6-B1,14-D4,14-E1
FPGA_TMPSENS_1C_CSN
S3A_CCLK
S3A_INIT_B
S3A_CONFIG_DONE
TMSTCKTDI_TO_V5TDI_TO_S3A
S3A_M0S3A_M1S3A_M2S3A_V0
S3A_V1
S3A_SPI_CSO
S3A_SPI_MOSIFPGA_AMC6821_FAN2_SDAFPGA_AMC6821_FAN2_SCK
S3A_SPI_DATA_TO_V5
S3A_SPI_MISO
FPGA_ASAP2_RST_CNTCLK
FPGA_CONFIG_DONE
FPGA_CCLK
14-D2,14-E1,17-A2,17-D5FPGA_UI_PROG0 FPGA_UI_PROG2
FPGA_UI_PROG1
FPGA_UI_PROG2
FPGA_UI_PROG1
R288
P3V3D
FPGA_UI_PROG0
S3A_PROG_B
P3V3D
JTAG_CCN
U19
R512
P3V3DP3V3D
J52
CUST_TDI
CUST_TMS
R70
7
R70
9
TDI_TO_S3A
R70
8
R72
8
R72
7
TDO_TO_JTAG
CUST_TCK
CUST_TDO
S3A_SPI_CSOFPGA_CCLKS3A_SPI_MISO
R270
R269R268
R267R266
J36
J37
R11
0
U98
S3A_SPI_WPN
S3A_SPI_HOLDN
S3A_SPI_MISOS3A_SPI_MOSI
FPGA_CCLK
S3A_SPI_CSO
P3V3D
C47
9
P3V3D
D22
C483
C482
C484C486
R71
0
C480
R513
P3V3D
R273R272
R271
S3A_SPI_MOSI
TCK
R51
6
S2
P3V3D
R73
2
R73
1
R55
9
R55
8
R55
7
R55
6
R55
5
R55
4
S9
R73
0
P3V3D
S3A_M2S3A_M1S3A_M0
P3V3D
R73
5
S10
R56
5
R56
4
R56
3
R56
2
R56
1
R56
0
R73
4
R73
3
S3A_V0S3A_V1S3A_V2
R289
R290
R291
14-D2,14-E5,17-A2,17-E114-E3,14-E5,17-A2,17-E1
43
4-20-2009_13:35
14 001
XILINX SPARTAN-3A CONTROL FPGA CONFIGURATION
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
FPGA_INIT_B
FPGA_FTDI_RDN
FPGA_AMC6821_FAN2_OVRN
FPGA_AMC6821_FAN2_OVRN
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
0.1U
2
1
2
3 4
5
6
GND
Enable/Disable
NC
OUT
Comp OUT
Vcc
100.000MHz
OSC
49.9
1
AA13 B2_VCCO_2_D0AA18 B2_VCCO_2_D1
AA5 B2_VCCO_2_D2AA9 B2_VCCO_2_D3U14 B2_VCCO_2_D4U9 B2_VCCO_2_D5
AA12 B2_IO_L19P_2/GCLK0AB12 B2_IO_L19N_2/GCLK1
V12 B2_IO_L20P_2/GCLK2U12 B2_IO_L20N_2/GCLK3
U11 B2_IO_L17P_2/GCLK12V11 B2_IO_L17N_2/GCLK13W12 B2_IO_L18P_2/GCLK14Y12 B2_IO_L18N_2/GCLK15
T7 B2_IP_2/VREF_2_D0U7 B2_IP_2_D0T8 B2_IP_2/VREF_2_D1V7 B2_IP_2_D1
AB2 B2_IO_L03P_2AA3 B2_IO_L03N_2
U8 B2_IP_2_D2AB3 B2_IO_L04P_2AA4 B2_IO_L04N_2W6 B2_IO_L05P_2Y5 B2_IO_L05N_2V8 B2_IP_2/VREF_2_D2
AB4 B2_IO_L06P_2AB5 B2_IO_L06N_2W7 B2_IO_L07P_2Y6 B2_IO_L07N_2
T9 B2_IP_2_D3AA6 B2_IO_L08P_2AB6 B2_IO_L08N_2
R9 B2_IP_2_D4Y7 B2_IO_L10P_2
AB7 B2_IO_L10N_2T10 B2_IP_2/VREF_2_D3AA8 B2_IO_L12P_2AB8 B2_IO_L12N_2V10 B2_IO_L13P_2
Y10 B2_IO_L13N_2U10 B2_IP_2_D5
AA10 B2_IO_L15P_2AB10 B2_IO_L15N_2
R10 B2_IP_2_D6T11 B2_IP_2/VREF_2_D4R11 B2_IP_2_D7
AB13 B2_IO_L21P_2Y13 B2_IO_L21N_2R12 B2_IP_2/VREF_2_D5
AA14 B2_IO_L22P_2W13 B2_IO_L23P_2Y14 B2_IO_L23N_2P12 B2_IP_2_D8
AB15 B2_IO_L24P_2/AWAKEW15 B2_IO_L25P_2Y15 B2_IO_L25N_2R13 B2_IP_2/VREF_2_D6
AB16 B2_IO_L27P_2Y16 B2_IO_L27N_2
T13 B2_IP_2_D9AB17 B2_IO_L29P_2AB18 B2_IO_L29N_2
R14 B2_IP_2/VREF_2_D7V14 B2_IO_L30P_2V15 B2_IO_L30N_2W16 B2_IO_L31P_2V16 B2_IO_L31N_2U15 B2_IP_2_D10
AB19 B2_IO_L32P_2
AA19 B2_IO_L32N_2W18 B2_IO_L33P_2V17 B2_IO_L33N_2T14 B2_IP_2_D11Y18 B2_IO_L34P_2W17 B2_IO_L34N_2T16 B2_IP_2/VREF_2_D8U16 B2_IP_2_D12
AB21 B2_IO_L35P_2AA21 B2_IO_L35N_2
T15 B2_IP_2/VREF_2_D9
E2B3_VCCO_3_D0J2B3_VCCO_3_D1J6B3_VCCO_3_D2N2B3_VCCO_3_D3P6B3_VCCO_3_D4V2B3_VCCO_3_D5
L5B3_IO_L21P_3/LHCLK0L3B3_IO_L21N_3/LHCLK1K1B3_IO_L22P_3/LHCLK2L1B3_IO_L22N_3/IRDY2/LHCLK3
M1B3_IO_L24P_3/LHCLK4M2B3_IO_L24N_3/LHCLK5M3B3_IO_L25P_3/TRDY2/LHCLK6M4B3_IO_L25N_3/LHCLK7C1B3_IO_L01P_3D2B3_IO_L01N_3B1B3_IO_L02P_3C2B3_IO_L02N_3D3B3_IO_L03P_3E4B3_IO_L03N_3
H8B3_IP_L04P_3H7B3_IP_L04N_3/VREF_3G6B3_IO_L05P_3G5B3_IO_L05N_3D1B3_IO_L06P_3E1B3_IO_L06N_3F4B3_IO_L07P_3E3B3_IO_L07N_3J8B3_IP_3/VREF_3_D0F3B3_IO_L08P_3
G4B3_IO_L08N_3H5B3_IO_L09P_3H6B3_IO_L09N_3K6B3_IO_L10P_3J5B3_IO_L10N_3J7B3_IP_L11P_3K8B3_IP_L11N_3F2B3_IO_L12P_3F1B3_IO_L12N_3G3B3_IO_L13P_3
G1B3_IO_L13N_3H4B3_IO_L14P_3H3B3_IO_L14N_3K7B3_IP_L15P_3L8B3_IP_L15N_3/VREF_3H2B3_IO_L16P_3H1B3_IO_L16N_3J3B3_IO_L17P_3J1B3_IO_L17N_3/VREF_3K5B3_IO_L18P_3
K4B3_IO_L18N_3L7B3_IP_L19P_3M8B3_IP_L19N_3K3B3_IO_L20P_3K2B3_IO_L20N_3M7B3_IP_L23P_3M6B3_IP_L23N_3N1B3_IO_L26P_3/VREF_3N3B3_IO_L26N_3N8B3_IP_L27P_3
N9B3_IP_L27N_3P1B3_IO_L28P_3P2B3_IO_L28N_3P3B3_IO_L29P_3P5B3_IO_L29N_3M5B3_IO_L30P_3N4B3_IO_L30N_3N6B3_IP_L31P_3N5B3_IP_L31N_3R1B3_IO_L32P_3
R2B3_IO_L32N_3R3B3_IO_L33P_3R4B3_IO_L33N_3R5B3_IO_L34P_3T4B3_IO_L34N_3N7B3_IP_L35P_3P8B3_IP_L35N_3T1B3_IO_L36P_3/VREF_3T3B3_IO_L36N_3U1B3_IO_L37P_3
U2B3_IO_L37N_3V1B3_IO_L38P_3V3B3_IO_L38N_3P7B3_IP_L39P_3R8B3_IP_L39N_3T5B3_IO_L40P_3U5B3_IO_L40N_3U3B3_IO_L41P_3U4B3_IO_L41N_3W1B3_IO_L42P_3
W2B3_IO_L42N_3R6B3_IP_3/VREF_3_D1V4B3_IO_L43P_3W3B3_IO_L43N_3Y1B3_IO_L44P_3Y2B3_IO_L44N_3AA1B3_IO_L45P_3AA2B3_IO_L45N_3R7B3_IP_L46P_3T6B3_IP_L46N_3/VREF_3
XC3S1400A-4FGG484C(3 of 4)
33
3
3
3 3 3 3
3
3
3
3
3
3
33
33
3
3
3
3
3
3
3
3 3
3
3 3
3
33
33
33
3
3
33
33
33
3
3
33
33
3 3 3 3
3 3 3 3
3
3 33
3 3 3 3 3
3
3
3
3 3
3 3
3 3
3
3
3
33 3
3 3
3
3
3
3 3
3 3
3
3
3
3 3
3
3
3
2
2
2
22
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2 2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2 2
2
2 2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2 22 2
22
NL
1
NL
1
NL
1
NL
1
0.1U 2
B10 B0_VCCO_0_D0B14 B0_VCCO_0_D1B18 B0_VCCO_0_D2B5 B0_VCCO_0_D3
F14 B0_VCCO_0_D4F9 B0_VCCO_0_D5
C12 B0_IO_L17P_0/GCLK4E12 B0_IO_L17N_0/GCLK5A12 B0_IO_L18P_0/GCLK6A11 B0_IO_L18N_0/GCLK7
B11 B0_IO_L19P_0/GCLK8C11 B0_IO_L19N_0/GCLK9D11 B0_IO_L20P_0/GCLK10E11 B0_IO_L20N_0/GCLK11E17 B0_IO_L01P_0D18 B0_IO_L01N_0F16 B0_IP_0_D0D19 B0_IO_L02P_0/VREF_0C19 B0_IO_L02N_0E16 B0_IP_0_D1
B20 B0_IO_L03P_0A20 B0_IO_L03N_0G15 B0_IP_0_D2E15 B0_IO_L04P_0F15 B0_IO_L04N_0C18 B0_IO_L05P_0A18 B0_IO_L05N_0G16 B0_IP_0_D3B19 B0_IO_L06P_0/VREF_0A19 B0_IO_L06N_0
D17 B0_IO_L07P_0C17 B0_IO_L07N_0G14 B0_IP_0_D4D16 B0_IO_L08P_0C16 B0_IO_L08N_0C14 B0_IO_L09P_0E14 B0_IO_L09N_0H14 B0_IP_0_D5B17 B0_IO_L10P_0A17 B0_IO_L10N_0
D15 B0_IO_L11P_0C15 B0_IO_L11N_0H13 B0_IP_0_D6A16 B0_IO_L12P_0A15 B0_IO_L12N_0/VREF_0B15 B0_IO_L13P_0A14 B0_IO_L13N_0G13 B0_IP_0_D7F13 B0_IO_L14P_0E13 B0_IO_L14N_0
D13 B0_IO_L15P_0C13 B0_IO_L15N_0F12 B0_IP_0_D8B13 B0_IO_L16P_0A13 B0_IO_L16N_0H12 B0_IP_0/VREF_0_D0G12 B0_IP_0_D9A10 B0_IO_L21P_0C10 B0_IO_L21N_0G11 B0_IP_0_D10
A9 B0_IO_L22P_0A8 B0_IO_L22N_0
D10 B0_IO_L23P_0E10 B0_IO_L23N_0H10 B0_IP_0_D11B9 B0_IO_L24P_0C9 B0_IO_L24N_0/VREF_0B8 B0_IO_L25P_0C8 B0_IO_L25N_0
G10 B0_IP_0_D12
A7 B0_IO_L26P_0A6 B0_IO_L26N_0D7 B0_IO_L27P_0C7 B0_IO_L27N_0
F10 B0_IP_0_D13B6 B0_IO_L28P_0A5 B0_IO_L28N_0C6 B0_IO_L29P_0D6 B0_IO_L29N_0H9 B0_IP_0/VREF_0_D1
E9 B0_IO_L30P_0D8 B0_IO_L30N_0A4 B0_IO_L31P_0B4 B0_IO_L31N_0E8 B0_IP_0_D14C5 B0_IO_L32P_0D5 B0_IO_L32N_0A3 B0_IO_L33P_0B3 B0_IO_L33N_0G9 B0_IP_0_D15
E7 B0_IO_L34P_0F8 B0_IO_L34N_0G8 B0_IP_0/VREF_0_D2F7 B0_IO_L35P_0E6 B0_IO_L35N_0G7 B0_IP_0_D16B2 B0_IO_L36P_0/VREF_0A2 B0_IO_L36N_0/PUDC_B
E21B1_VCCO_1_D0J17B1_VCCO_1_D1K21B1_VCCO_1_D2P17B1_VCCO_1_D3P21B1_VCCO_1_D4V21B1_VCCO_1_D5
M22B1_IO_L21P_1/RHCLK0L22B1_IO_L21N_1/RHCLK1L21B1_IO_L22P_1/RHCLK2L20B1_IO_L22N_1/TRDY1/RHCLK3
M18B1_IO_L24P_1/RHCLK4M20B1_IO_L24N_1/RHCLK5K20B1_IO_L25P_1/IRDY1/RHCLK6K19B1_IO_L25N_1/RHCLK7U18B1_SUSPENDAA22B1_IO_L01P_1/HDCY21B1_IO_L01N_1/LDC2W19B1_IO_L02P_1/LDC1W20B1_IO_L02N_1/LDC0T17B1_IO_L03P_1/A0
T18B1_IO_L03N_1/A1R15B1_IP_L04P_1R16B1_IP_L04N_1/VREF_1Y22B1_IO_L05P_1W21B1_IO_L05N_1V19B1_IO_L06P_1V20B1_IO_L06N_1W22B1_IO_L07P_1V22B1_IO_L07N_1P15B1_IP_L08P_1
P16B1_IP_L08N_1U22B1_IO_L09P_1U21B1_IO_L09N_1U20B1_IO_L10P_1U19B1_IO_L10N_1T20B1_IO_L11P_1T22B1_IO_L11N_1R17B1_IP_L12P_1R18B1_IP_L12N_1/VREF_1R20B1_IO_L13P_1
T19B1_IO_L13N_1R21B1_IO_L14P_1R22B1_IO_L14N_1P20B1_IO_L15P_1P22B1_IO_L15N_1/VREF_1N15B1_IP_L16P_1N16B1_IP_L16N_1/VREF_1R19B1_IO_L17P_1/A2P18B1_IO_L17N_1/A3N22B1_IO_L18P_1/A4
N21B1_IO_L18N_1/A5N20B1_IO_L19P_1/A6N19B1_IO_L19N_1/A7N18B1_IO_L20P_1/A8N17B1_IO_L20N_1/A9M17B1_IP_L23P_1M16B1_IP_L23N_1K22B1_IO_L26P_1/A10J22B1_IO_L26N_1/A11M15B1_IP_L27P_1/VREF_1
L16B1_IP_L27N_1L18B1_IO_L28P_1L19B1_IO_L28N_1J21B1_IO_L29P_1/A12J20B1_IO_L29N_1/A13H22B1_IO_L30P_1/A14G22B1_IO_L30N_1/A15L15B1_IP_L31P_1K16B1_IP_L31N_1K17B1_IO_L32P_1
K18B1_IO_L32N_1H21B1_IO_L33P_1/A16H20B1_IO_L33N_1/A17F22B1_IO_L34P_1/A18F21B1_IO_L34N_1/A19K14B1_IP_L35P_1/VREF_1K15B1_IP_L35N_1G19B1_IO_L36P_1G20B1_IO_L36N_1J18B1_IO_L37P_1
H19B1_IO_L37N_1E20B1_IO_L38P_1F20B1_IO_L38N_1H17B1_IP_L39P_1H18B1_IP_L39N_1F19B1_IO_L40P_1F18B1_IO_L40N_1E22B1_IO_L41P_1D22B1_IO_L41N_1D21B1_IO_L42P_1
D20B1_IO_L42N_1J16B1_IP_L43P_1J15B1_IP_L43N_1/VREF_1C22B1_IO_L44P_1/A20C21B1_IO_L44N_1/A21B22B1_IO_L45P_1/A22B21B1_IO_L45N_1/A23G18B1_IO_L46P_1/A24G17B1_IO_L46N_1/A25H16B1_IP_L47P_1/VREF_1
H15B1_IP_L47N_1
XC3S1400A-4FGG484C(2 of 4)
1
111
1 1
11
1
1
1
1 1
1 1
1 1
1
1
1 1
1
1
1 1
1111
1 1
1 1 1
1
1 1
1 1
1 1
1
1
111111
11
1
1
1
1 1 1
11
1
1
1
1 1 1
11
11
1 1
1 1
1
1
1
1
1 1
11
1
111
11
11
11
11
11
1
1
1
1 1
1
0
0
00
0
0
0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0 00
00
Reach Display Interface
AMC6821 Fan #1 Control
(3.3V)
(2.5V)
(3.3V)
XC3S1400A-4FG484C
Bank 1
Bank 0
Bank 3
Bank 2
Bank 3 (2.5V):
Place near Bank 3 of Spartan 3A
*** INPUTS ***
uBlaze SDRAM
(3.3V)
Bank 2 (3.3V): SPI Device InterfacesBank 1 (3.3V): SPI Device InterfacesBank 0 (3.3V): Clock Path FPGA/Logic Analyzer
MicroSD Interface
Temp Sensor Col. 1
Temp Sensor Col. 2
AD9516 Control
DDR2 SDRAM SODIMM Control
Debug Push Buttons
DAC5682 Control
AD9516 Control
AMC6821 Fan #1 Control
Data Path FPGA Control
Data Path FPGA Control
AsAP 1 Config Input
AsAP 1 Config Output
USB to RS-232 Interface
Board Reset
CPU Interface
10MHz Reference Clock
FT245BL USB Interface
DAC5682 Control
Temp Sensor Col. 2
MicroSD Interface
Debug LEDs
USB to RS-232 Interface
10MHz Clock Control
Logic Analyzer Clk/Data
Xilinx Spartan-3A Control FPGA I/O
VREF Decoupling CapacitorsC
Custom Configuration
*** OUTPUTS ***DDR SDRAM Interface
Custom Configuration
CPU Interrupts
Place NoLoad Resistors near V5.
Place NoLoad Resistors near V5.
HW and Slot ID
B 100MHz Digital Clock
AMC6821 Fan #2 Control
AsAP 2 Config Output
FT245BL USB Interface
AsAP 2 Config Input
Temp Sensor Col. 1
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
Reach Display Interface
U19
FPGA_DDR_SDRAM_CLK_P
FPGA_DDR_SDRAM_UDMC
489
FPGA_DP_CTRL_GPIO[4:0]15-B3,15-B5,22-D1,22-D3
FPGA_DP_CTRL_GPIO4FPGA_DP_CTRL_GPIO3FPGA_DP_CTRL_GPIO2
FPGA_DP_CTRL_GPIO1FPGA_DP_CTRL_GPIO0
FPGA_DP_CTRL_MISO
FPGA_DP_CTRL_RSTN
15-C5,15-D3,34-D2
NC
NC
NC
FPGA_REACH_TXFPGA_REACH_RX
FPGA_REACH_TX
FPGA_REACH_RX
15-B3,15-D5,20-E1,20-E2
15-C3,15-C5,17-B5,17-D115-C3,15-C5,17-B5,17-D1
6-A4,15-C1,15-D3
FPGA_EXT_CLK10MHZ_LOSFPGA_CLK10MHZ_REF_CTRL0FPGA_PUSHBUTTON2FPGA_TMPSENS_1B_MISOFPGA_TMPSENS_1B_SCKFPGA_PUSHBUTTON1FPGA_TMPSENS_1B_MOSIFPGA_TMPSENS_1B_CSN
NC
FPGA_CLK10MHZ_REF_CTRL1FPGA_CLK10MHZ_REF_CTRL2FPGA_UI_SCKFPGA_UI_RSTN
NC
FPGA_UI_MOSIFPGA_CLK10MHZ_REF_CTRL3FPGA_LEDS0
NC
FPGA_PUSHBUTTON0FPGA_LOCAL_RSTNFPGA_UI_CSNFPGA_UI_RDYFPGA_UI_INTN
NC
FPGA_LEDS1FPGA_S3A_BOARD_RSTNFPGA_UI_MISO
NCFPGA_LEDS3FPGA_LEDS2
NC
NCNCNCNC
NC
FPGA_LA_DATA7FPGA_LA_DATA6
NC
FPGA_LA_DATA5FPGA_LA_DATA3
FPGA_LA_DATA2FPGA_LA_DATA0
NC
FPGA_LA_CLKFPGA_DDR2_SDRAM_SDAFPGA_DDR2_SDRAM_SCL
NC
FPGA_LA_DATA4
FPGA_TMPSENS_2C_CSNFPGA_TMPSENS_2C_MOSI
NCFPGA_LA_DATA1
NC
FPGA_TMPSENS_2C_SCKFPGA_TMPSENS_2C_MISO
NC
NC
CUST_INIT_BCUST_CFG_DONECUST_CCLKCUST_PROG_B
NCNC
NC
NC
NC
FPGA_AD9516_REF_SEL
NC
FPGA_TMPSENS_2A_CSN
FPGA_TMPSENS_2A_MOSIFPGA_TMPSENS_2A_MISO
NCNC
NC
NCNCNC
FPGA_TMPSENS_1C_MISO
NC
NC
NC
FPGA_FTDI_DATA3
NC
NC
NC
FPGA_SLOTID0
FPGA_HWID1
FPGA_SLOTID1
NC
FPGA_AMC6821_FAN1_OVRN
NC
FPGA_EXT_CLK10MHZ_REF_NFPGA_EXT_CLK10MHZ_REF_P
FPGA_INT_CLK10MHZ_REF_NFPGA_INT_CLK10MHZ_REF_P
FPGA_CLK100MHZ_NFPGA_CLK100MHZ_P
15-B1,15-C3,15-D3,17-D217-E515-B1,15-C3,15-D3,17-D217-E5
FPGA_FTDI_RSTOUTN
FPGA_SLOTID[2:0]FPGA_HWID[1:0]
FPGA_S3A_BOARD_RSTN
CUST_CFG_DONECUST_INIT_B
R568R569
22-D2,22-D522-D2,22-D5
V5_CONFIG_DONE
R567R566
V5_INIT_B
CUST_PROG_BCUST_CCLK
V5_PROG_BV5_CCLK
15-B1,15-E5,17-A2,17-E115-B1,15-E5,17-B2,17-E115-C1,15-E5,17-A2,17-E1
15-B4,15-C4,15-D4,15-E415-E5,18-D3,18-E115-C4,15-E5,18-C1,18-E115-B4,15-C4,15-E5,19-D819-E1,19-E215-B4,15-E5,18-C1,18-E1
15-B4,15-E5,19-B8,19-E119-E215-C4,15-E5,19-B8,19-E1
15-B4,15-E5,18-C1,18-E1
FPGA_CLK100MHZ_P
TP
148
FPGA_AD9516_REF_SELFPGA_AD9516_SYNC
12-E1,15-C5,15-E3
FPGA_AD9516_RESET12-E1,15-C3,15-C5
FPGA_INT_CLK10MHZ_REF_P
NC
FPGA_INT_CLK10MHZ_REF_N
FPGA_UI_MISOFPGA_UI_RDYFPGA_UI_INTN
FPGA_TMPSENS_1C_SCKFPGA_TMPSENS_1C_MOSI
FPGA_TMPSENS_1B_SCK
FPGA_TMPSENS_1B_MOSIFPGA_TMPSENS_1B_CSN
15-B1,15-D5,20-E1,20-E2
FPGA_TMPSENS_1A_SCKFPGA_TMPSENS_1A_CSNFPGA_TMPSENS_1A_MOSI
FPGA_SD_RXD
FPGA_RS232_CTSFPGA_RS232_TX
FPGA_RS232_RX
FPGA_RS232_RTS
FPGA_PUSHBUTTON[2:0]
FPGA_LEDS[3:0]
FPGA_LA_DATA[7:0]
FPGA_LA_CLK
FPGA_FTDI_WRNFPGA_FTDI_SI_WU
FPGA_EXT_CLK10MHZ_REF_NFPGA_EXT_CLK10MHZ_REF_P
FPGA_EXT_CLK10MHZ_LOS
FPGA_DP_CTRL_MISOFPGA_DP_CTRL_INTN
FPGA_DP_CTRL_MOSIFPGA_DP_CTRL_CSNFPGA_DP_CTRL_SCK
FPGA_DDR2_SDRAM_SDAFPGA_DDR2_SDRAM_SCL
FPGA_DAC5682_SDO
FPGA_CLK10MHZ_REF_CTRL[3:0]
FPGA_LOCAL_RSTN
FPGA_ASAP2_MISO
FPGA_ASAP1_MISO
FPGA_AMC6821_FAN1_SDAFPGA_AMC6821_FAN1_SCK
FPGA_AMC6821_FAN2_SMBALERTNFPGA_AMC6821_FAN2_THERMNFPGA_AMC6821_FAN2_FAULTN
FPGA_AMC6821_FAN1_SMBALERTNFPGA_AMC6821_FAN1_OVRNFPGA_AMC6821_FAN1_THERMN
15-C5,15-D1,20-D1,20-D2
15-D3,15-D5,17-D1
15-C1,15-C3,17-B5,17-D515-C1,15-C3,17-B5,17-D5
11-C5,11-E5,15-E111-C5,11-E5,15-E1
11-D5,11-E5,15-D1,15-E111-D5,11-E5,15-D1,15-E111-B1,11-E5,15-B1,15-D1
15-D3,15-E1,17-E5
15-B1,15-E1,17-A2,17-D515-B1,15-E1,17-B2,17-D515-B1,15-E1,17-A2,17-D5
15-C1,15-E1,17-B3,17-E5
15-B1,15-E1,17-E5
15-D3,15-E1,17-E5
15-D3,15-D5,17-D1
15-B1,15-C1,15-D5,17-C217-E5
15-C1,15-D1,15-D5,17-A517-D115-C1,15-D5,17-A5,17-D1
15-C1,15-D3,36-C2,36-E5
15-B3,15-C1,22-D3,22-E515-B3,15-C1,22-D3,22-E5
12-D5,15-C3,15-D112-E5,15-C3,15-D112-E5,15-C3,15-D112-E5,15-C3,15-D1
15-D1,15-D3,34-D2
15-B1,15-E1,17-C1,17-E5
15-C4,15-E5,18-D1,18-E115-B4,15-E5,18-C1,18-E1
15-D4,15-E5,18-D1,18-E115-D4,15-E5,18-D1,18-E115-D4,15-E5,18-C1,18-E115-D4,15-E5,18-C1,18-E1
15-B5,15-C1,27-D115-B5,15-C1,27-D1
FPGA_AMC6821_FAN1_FAULTN
6-C4,15-C1,15-D3
FPGA_AD9516_LD
15-D1,15-D3,20-E7,20-E815-B1,15-D1,20-E7,20-E8
12-E1,15-C3,15-C5
15-C3,15-D5,20-E1,20-E2
15-D3,15-D5,20-E1,20-E215-D3,15-D5,20-E1,20-E2
FPGA_DDR_SDRAM_DATA[15:0]FPGA_DDR_SDRAM_BA[1:0]
FPGA_DDR_SDRAM_ADDR[12:0]
FPGA_AD9516_PDFPGA_AD9516_SDIO
FPGA_AD9516_SDO
FPGA_DAC5682_SDIO
FPGA_UI_MOSIFPGA_UI_CSNFPGA_UI_SCK
U19
P1V25D_DDR_VTT
P1V25D_DDR_VREF
P3V3D_S3AP3V3D_S3A
P3V3D_S3AP2V5D_S3A
R73
P1V25D_DDR_VREF
P1V25D_DDR_VREF
P1V25D_DDR_VREF
P1V25D_DDR_VREF
P1V25D_DDR_VREF
P1V25D_DDR_VREF
P1V25D_DDR_VREF
P1V25D_DDR_VREF
FPGA_DDR_SDRAM_UDQS
FPGA_DDR_SDRAM_LDM
FPGA_DDR_SDRAM_LDQS
FPGA_DDR_SDRAM_RASNFPGA_DDR_SDRAM_CASNFPGA_DDR_SDRAM_WENFPGA_DDR_SDRAM_CSNFPGA_DDR_SDRAM_CLK_NFPGA_DDR_SDRAM_CLK_PFPGA_DDR_SDRAM_CKE
FPGA_SD_CARD_DETECTFPGA_SD_CLKFPGA_SD_TXD
FPGA_SD_BUSY_LED
FPGA_TMPSENS_2C_MISOFPGA_TMPSENS_2B_MISOFPGA_TMPSENS_2A_MISO
FPGA_TMPSENS_1C_MISOFPGA_TMPSENS_1B_MISOFPGA_TMPSENS_1A_MISO
NCNC
NCNC
NCNC
NC
NC
NCNC
NCNC
NC
NCNC
NC
FPGA_DDR_SDRAM_CLK_N
FPGA_DDR_SDRAM_ADDR12FPGA_DDR_SDRAM_ADDR11
FPGA_DDR_SDRAM_CLKFB
FPGA_DDR_SDRAM_DATA0
FPGA_DDR_SDRAM_DATA1
FPGA_DDR_SDRAM_DATA2FPGA_DDR_SDRAM_DATA3
NCFPGA_DDR_SDRAM_LDQS
FPGA_DDR_SDRAM_DATA4FPGA_DDR_SDRAM_DATA5
FPGA_DDR_SDRAM_DATA6
FPGA_DDR_SDRAM_DATA7
NC
FPGA_DDR_SDRAM_DATA8FPGA_DDR_SDRAM_LDM
FPGA_DDR_SDRAM_DATA10FPGA_DDR_SDRAM_DATA9
FPGA_DDR_SDRAM_DATA11
NCFPGA_DDR_SDRAM_UDQS
FPGA_DDR_SDRAM_DATA12FPGA_DDR_SDRAM_DATA13
FPGA_DDR_SDRAM_DATA14FPGA_DDR_SDRAM_DATA15
NC
FPGA_DDR_SDRAM_ADDR10FPGA_DDR_SDRAM_ADDR9
FPGA_DDR_SDRAM_ADDR8FPGA_DDR_SDRAM_ADDR7
FPGA_DDR_SDRAM_ADDR6FPGA_DDR_SDRAM_ADDR5
FPGA_DDR_SDRAM_ADDR4FPGA_DDR_SDRAM_ADDR3
FPGA_DDR_SDRAM_ADDR2FPGA_DDR_SDRAM_ADDR1
FPGA_DDR_SDRAM_ADDR0
FPGA_DDR_SDRAM_BA1
NC
FPGA_DDR_SDRAM_BA0FPGA_DDR_SDRAM_CKE
FPGA_DDR_SDRAM_CSNFPGA_DDR_SDRAM_RASN
FPGA_DDR_SDRAM_CASN
FPGA_DDR_SDRAM_WEN
NCNC
NCNC
NCNC
NC
NC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
FPGA_DDR_SDRAM_CLKFB
FPGA_TMPSENS_2A_CSNFPGA_TMPSENS_2A_SCK
FPGA_TMPSENS_2B_SCKFPGA_TMPSENS_2B_CSN
FPGA_TMPSENS_2C_SCKFPGA_TMPSENS_2C_CSN
FPGA_TMPSENS_2A_MOSI
FPGA_TMPSENS_2B_MOSI
FPGA_TMPSENS_2C_MOSI
FPGA_DAC5682_RSTBFPGA_DAC5682_SCLKFPGA_DAC5682_SDENB
FPGA_AD9516_REFMON
FPGA_AD9516_CSBFPGA_AD9516_SCLK
FPGA_AD9516_STATUS
15-D3,15-D5,17-D115-D3,15-D5,17-D115-D3,15-D5,17-D115-D3,15-D5,17-C5,17-D1
15-D3,15-D5,20-E1,20-E2
15-B1,15-D5,20-E1,20-E2
15-C5,15-D3,20-D1,20-D215-C5,15-D3,20-D1,20-D215-C3,15-C5,20-D1,20-D2
15-C3,15-C5,20-D1,20-D215-C3,15-C5,20-D1,20-D215-C3,15-C5,20-D1,20-D2
15-C5,15-D1,20-D1,20-D215-C5,15-D1,20-D1,20-D2
15-C5,15-D3,34-D215-C5,15-D3,34-D2
15-C5,15-D3,34-D2
12-E1,15-C3,15-C512-E1,15-C3,15-C5
12-E1,15-C3,15-C5
15-D1,15-D3,17-D5
15-B3,15-D1,20-E7,20-E8
15-D1,20-E7,20-E815-C3,15-D1,20-E7,20-E815-D1,15-D3,20-E7,20-E8
6-D1,15-C1,15-D36-D1,15-C1,15-D36-C1,15-C1,15-D3
6-B1,15-C1,15-D36-B1,15-C1,15-D3
6-C4,15-B5,15-D36-C4,15-B5,15-D3
15-B5,15-C3,22-D1,22-D315-B3,15-B5,22-D1,22-D315-B3,15-B5,22-D1,22-D315-B3,15-B5,22-D1,22-D3
FPGA_ASAP2_MOSIFPGA_ASAP2_SPI_LOADFPGA_ASAP2_SPI_CSNFPGA_ASAP2_SPI_CLKFPGA_ASAP2_CFG_VALIDFPGA_ASAP2_CFG_CLKFPGA_ASAP2_RESET_COLD
FPGA_ASAP1_RST_CNTCLKFPGA_ASAP1_MOSIFPGA_ASAP1_SPI_LOADFPGA_ASAP1_SPI_CSNFPGA_ASAP1_SPI_CLKFPGA_ASAP1_CFG_VALIDFPGA_ASAP1_CFG_CLKFPGA_ASAP1_RESET_COLD
15-B5,15-D3,36-D2,36-E115-B5,15-D3,36-C1,36-E115-B5,15-D3,36-C1,36-E115-B5,15-D3,36-C1,36-E115-B5,15-D3,36-D1,36-E1
15-B5,15-D3,36-C2,36-E115-B5,15-D3,36-C2,36-E115-B5,15-D3,36-D1,36-E1
15-A5,15-B3,40-C2,40-E115-A5,15-C3,40-C2,40-E1
15-B5,15-C3,40-D1,40-E115-B3,15-B5,40-C1,40-E115-A5,15-B3,40-C1,40-E115-A5,15-C3,40-C1,40-E115-A5,15-C3,40-D2,40-E1
15-C1,15-C3,40-C2,40-E5
11-B1,11-C1,11-E1,15-B115-D5
P3V3D
U81 C488
NC
FPGA_FTDI_DATA[7:0]FPGA_FTDI_TXENFPGA_FTDI_RXFNFPGA_FTDI_PWRENN
15-C1,15-C3,17-B5,17-D515-C1,15-C3,17-B5,17-D5
15-C1,15-C3,17-D5
15-B1,15-D5,20-E1,20-E2
NCNC
NCNC
12-E1,15-C3,15-C5
TP
147
FPGA_CLK100MHZ_N
22-C1,22-D222-B2,22-C1,22-D2
43
4-20-2009_13:35
15 001
XILINX SPARTAN-3A CONTROL FPGA I/O
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
NCNC
NCNCNC
FPGA_AMC6821_FAN1_FAULTNFPGA_AMC6821_FAN1_THERMN
FPGA_AMC6821_FAN1_SMBALERTNFPGA_SD_TXDFPGA_SD_CLK
FPGA_AMC6821_FAN2_FAULTNFPGA_SD_RXDFPGA_SD_CARD_DETECT
FPGA_RS232_TXFPGA_AMC6821_FAN2_THERMNFPGA_SD_BUSY_LEDFPGA_RS232_RXFPGA_AMC6821_FAN1_SCKFPGA_RS232_CTS
FPGA_AMC6821_FAN2_SMBALERTNFPGA_RS232_RTSFPGA_TMPSENS_1A_MISOFPGA_HWID0FPGA_AMC6821_FAN1_SDAFPGA_TMPSENS_1A_SCK
FPGA_TMPSENS_1A_CSNFPGA_TMPSENS_1A_MOSIJTAG_CCN
CUST_TCKCUST_TDOCUST_TDICUST_TMS
FPGA_SLOTID2
S3A_SPI_HOLDN
FPGA_FTDI_RXFN
S3A_SPI_WPNFPGA_FTDI_SI_WU
FPGA_FTDI_TXENFPGA_FTDI_DATA6FPGA_FTDI_DATA2FPGA_FTDI_DATA4FPGA_FTDI_PWRENNFPGA_FTDI_DATA7FPGA_FTDI_DATA5
FPGA_ASAP2_RESET_COLDFPGA_ASAP2_SPI_CLKFPGA_FTDI_RSTOUTNFPGA_FTDI_WRNFPGA_FTDI_DATA0
FPGA_FTDI_DATA1
FPGA_ASAP2_SPI_LOAD
FPGA_ASAP2_SPI_CSNFPGA_ASAP2_MISOFPGA_TMPSENS_1C_SCK
FPGA_ASAP2_MOSIFPGA_TMPSENS_1C_MOSI
NC
FPGA_ASAP2_CFG_VALIDFPGA_ASAP2_CFG_CLK
FPGA_AD9516_SYNC
NC
NCFPGA_ASAP1_MISOFPGA_ASAP1_SPI_CLKFPGA_ASAP1_CFG_VALIDFPGA_ASAP1_CFG_CLK
NCFPGA_ASAP1_MOSIFPGA_ASAP1_SPI_LOADFPGA_ASAP1_RESET_COLDFPGA_ASAP1_RST_CNTCLKFPGA_ASAP1_SPI_CSNFPGA_DAC5682_SCLK
NCFPGA_DAC5682_SDIOFPGA_DAC5682_SDENBFPGA_DAC5682_RSTBFPGA_DAC5682_SDO
NC
FPGA_AD9516_PDFPGA_AD9516_SDO
NCFPGA_TMPSENS_2A_SCKFPGA_AD9516_LD
FPGA_AD9516_RESETFPGA_AD9516_SDIOFPGA_AD9516_CSBFPGA_AD9516_SCLKFPGA_AD9516_STATUSFPGA_AD9516_REFMON
NCFPGA_TMPSENS_2B_CSNFPGA_TMPSENS_2B_MOSI
NCNC
FPGA_TMPSENS_2B_SCK
NC
FPGA_TMPSENS_2B_MISONCNCNCNC
NCNCNC
FPGA_DP_CTRL_MOSIFPGA_DP_CTRL_CSN
NCNCNCNC
FPGA_DP_CTRL_SCKNCNC
FPGA_DP_CTRL_RSTN
NC
FPGA_DP_CTRL_INTNNCNC
NCNCNCNCNC
NCNCNC
NCNC
NC
NCNCNC
NCNC
NC
NC
15-A5,15-E3,17-D1,17-E4
15-B1,15-E3,17-D5,17-E4
NC
NC
NCNC
NC
NCNC
NCNC
NCNC
NC
C493
C492
C491
C490
C289
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
42-OHM
1 2
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
47U
2
0.1U 2
47U
2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
42-OHM
1 2
33U
2
47U
2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
330U 2
330U 2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
47U
2
47U
2
47U
2
47U
2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
LP2996MR/NOPB
SD2
5
6
7
1 9
8
3
4
PVin
Vsense
Vtt
GND PMH
AVin
Vddq
Vref
42-OHM
1 2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1U 2
0.1U 2
0.1UFA B
G1 G2
D12 VCCAUX_D0E18 VCCAUX_D1
E5 VCCAUX_D2H11 VCCAUX_D3
L4 VCCAUX_D4M19 VCCAUX_D5P11 VCCAUX_D6V18 VCCAUX_D7
V5 VCCAUX_D8W11 VCCAUX_D9
J10 VCCINT_D0J12 VCCINT_D1K11 VCCINT_D2K13 VCCINT_D3K9 VCCINT_D4
L10 VCCINT_D5L12 VCCINT_D6L14 VCCINT_D7M11 VCCINT_D8M13 VCCINT_D9
M9 VCCINT_D10N10 VCCINT_D11N12 VCCINT_D12N14 VCCINT_D13P13 VCCINT_D14
A1GND_D0A22GND_D1AA11GND_D2AA16GND_D3AA7GND_D4AB1GND_D5AB22GND_D6B12GND_D7B16GND_D8B7GND_D9
C20GND_D10C3GND_D11D14GND_D12D9GND_D13F11GND_D14F17GND_D15F6GND_D16G2GND_D17G21GND_D18J11GND_D19
J13GND_D20J14GND_D21J19GND_D22J4GND_D23J9GND_D24K10GND_D25K12GND_D26L11GND_D27L13GND_D28L17GND_D29
L2GND_D30L6GND_D31L9GND_D32M10GND_D33M12GND_D34M14GND_D35M21GND_D36N11GND_D37N13GND_D38P10GND_D39
P14GND_D40P19GND_D41P4GND_D42P9GND_D43T12GND_D44T2GND_D45T21GND_D46U17GND_D47U6GND_D48W10GND_D49
W14GND_D50Y20GND_D51Y3GND_D52
XC3S1400A-4FGG484C(1 of 4)
P P
P PP
P P
P PP
PP
PP
P PP
P P
P P P PP P
P P
P P PP P P
P P P P
P P
P P PP P
PP P
PP
P P
PP
P
PP
P
P
P
P
PP
P
P P
P PP
P P P
P PP
P P P
P
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2YX2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
TANT
TANT TANT
TANT
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2YX2Y
X2Y
X2Y
X2Y
X2Y
X2Y
Rated @ 6A
Rated @ 6A
Rated @ 6A
TANT
TANTTANT
TANT
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
0402 0402 0402 0402 0402 0402
0402
0402
0402
0402
0402
0402
Connect at midpoint of bus.Use this as a sense line.
Bank 2 (3.3V):Bank 1 (3.3V): SPI Device InterfacesBank 0 (3.3V):
(3.3V)
(2.5V)
(3.3V)Bank 1
Bank 0
Bank 3
Bank 2(3.3V)
Bank 3 (2.5V):
Capacitor Placement(top side)
Tantalum/O402 Via Placement
X2Y Capacitor Via Placement
(3.3V)Bank 2
(3.3V)Bank 0
(3.3V)Bank 1
(2.5V)Bank 3
XC3S1400A-4FG484C
Xilinx Spartan-3A Control FPGA Power Supplies
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
(bottom side)
Capacitor Placement
(3.3V)
Bank 0
(3.3V)
Bank 2
XC3S1400A-4FG484C
(3.3V)Bank 1
(2.5V)Bank 3
XC3S1400A-4FG484C
UI, 10MHz, LEDs, ...
FTDI, AsAP #2, microSD, Fan Ctrl, ...uBlaze SDRAM
U19
TP
104
TP
105
C876
C193
C192
C875
C676C677
L21
U71
C660C653C656C655C654C659
C662C864C663C863C665C666C667C668C669C664
C678C675C674C673C672C671C670C679
C186
C187
C188
C189
C190
C191
C185
C179
C180
C178
C184
C183
C182
C181
C680 C689 C688 C687C686
C685 C684 C681 C682 C683
C647
C648
C649
C646
C869 C870 C866 C865 C868 C867
C874
C154
C155C872 C871 C873
C877 C878 C879 C880 C881 C882
C894 C893 C892 C891
C887 C888
C650
C651
L22
C883 C884 C885 C886 C361
C494
C360
P3V3D_S3A
P1V2D_S3A
P1V25D_DDR_VREF
P1V25D_DDR_VTT
43
3-27-2009_12:24
16 001
XILINX SPARTAN-3A CONTROL FPGA POWER SUPPLIES
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
L20
P3V3D
P3V3D_S3A
P1V2D
P1V2D_S3A
P2V5D
P2V5D_S3A
C657 C658
C890 C889
1U
2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
1
VERT
42-OHM
1 2
10U
2
0.1U
2
42-OHM
1 2
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
20
1
20
1
20
1
0.1U2
0.1U
2
0.1U
2
0.1U
2
10U
2
0.1U
2
10K
1
20P
2
20
1
87832-1420
1
10
11 12
13 14
2
3 4
5 6
7 8
9
VERT
LN
J308G8L
RA
1
GR
EE
N301
1
1
1
1
0.1U2
47U
2
0.1U 2
0.1U 2
2.2U2
2.2U2
10K
1
2.2U2
LN
J308G8L
RA
1
GR
EE
N
301
1
0.1U2
LN
J308G8L
RA
1
GR
EE
N301
1
10K
1
10K
1
LN
J308G8L
RA
1
GR
EE
N
3011
LN
J308G8L
RA
1
GR
EE
N
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
MT46V32M16BN-6:F
A0K7
A1L8
A10K8
A11J2
A12H2
A2L7
A3M8
A4M2
A5L3
A6L2
A7K3
A8K2
A9J3
BA0J8
BA1J7
CAS#G8
CKG2
CK#G3
CKEH3
CS#H8
F9DNU
A8DQ0DQ1 B9
DQ10 D1
C3DQ11C1DQ12
DQ13 B3
DQ14 B1
DQ15 A2
DQ2 B7
DQ3 C9
DQ4 C7
D9DQ5D7DQ6
DQ7 E9
DQ8 E1
DQ9 D3
LDM F7
LDQS E7
RAS#H7
UDM F3
UDQS E3
D2
A7
VDD
F8
M7
A9
VDDQ
B2
C8
E8
VREF F1
A3
VSS
F2
M3
A1
VSSQ
B8
C2
D8
E2
WE#G7
3011
3011
LN
J308G8L
RA
1
GR
EE
N
TPS3823-33DBV
1
2
3
4
5
GND
VDD
WDI
MR
RESET
1
20
1
20
1
20
1
20
1
20
1
20
1
20
1
20
1
20
1
1
2
3
4
5
SN74LVC1G08DCKR
VCC
AB
Y
GND
1
2
3
4
5
SN74LVC1G08DCKR
VCC
AB
Y
GND
42-OHM
1 2
4.7U
2
5.11
K
1
FQ1045A-6
1 X1 2X2XTAL
6.000MHz
20P
2
1
2
3
4 5
6
7
8
AT93C46-10SU-1.8
SKDIDO
NCNC
VCC
GND
SP
I EE
PR
OMCS
2.21K
1
0.1U
2
4751
10K
1
0.22U
2
10U
2
42-OHM
1 2
1
18
VERT
0.1U2
0.1U
2
0.1U
2
10K
1
5.11
K
1
10U
2
42-OHM
1 2
42-OHM
1 2
4.75K1
22.1
1
22.1
1
14
2
6
7T_OUT
13
9 R_OUT12
T_IN10
11
15
5
4
3
1
16
MAX3232ECAE+
R_IN 8
0V
C1+C1-C2+C2-
VS-
VS+
VCC
0.1U
2
0.1U
2
0.1U
2
0.1U
2
0.1U
2
1.50K
1
1
Vert
1
Vert
0.1U
2
10U
2
1
10
11
12
14
15
16
18
19
2
20
22
24
25
27
28
32
4
5 21
23
8
7
6
31
9 17 29
30263 13
D6D5D4D3D2D1
VCC VCCIO AVCC
GND
D0
AGND
EEDATAEESKEECS
TEST
D7
RD#WR
TXE#RXF#
SI/WUPWREN#
RESET#RSTO#
XTIN
XTOUT
USB-2-Parallel
FT245BL
FIFO
USBDM
USBDP
3V3OUT
1
Vert
NL
0.0
1
NL
1
0.0
1
NL
1
0.0
1
0.0
1
NL
1
NL
1
0.0
1
1 CLK_IN
GND4
2 OE
VDD6
Y0 3
Y1 5
Y2 7
8Y3
PI6CV2304WE
9
8
7
6
5
4
3
2827262524
222120
2
19181716151413
12
11
10
1
23
3029
QFN
CP21025x5mm
REGIN
VDD
D-
D+
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RTSRXDTXDDSRDTR
RIDCD
SUSPEND
SUSPEND
RST
GND
VBUS
CTS
GNDPADDLE
SHIE
LD
(SDcard)microSD
CD/CE
CLK
DATO/MISO
GN
D
VC
C
RSV
1
RSV
0
DATI/MOSI
USB Bus-Powered
*** OUTPUTS ***
Logic Analyzer Clk/Data
Momentary ButtonsActive Low
DEBUG LEDs
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
SDRAM Data/Address/Ctrl
CPU Interface
CPU InterruptsClock Path Board Reset
*** INPUTS ***
MicroSD Interface
USB to RS-232
User Interface Board
MicroSD Interface
Xilinx Spartan-3A Control FPGA Peripherals
Reset Circuit
USB-to-RS-232 Debug Interface LOGIC ANALYZER HEADER
HW and Slot IDA
Debug Push Buttons
Debug LEDs
USB to RS-232 Interface
HW and Slot IDB DDR SDRAM
USB Type-B Peripheral
Reach Display
FT245BL USB Interface
Reach Display Interface
PUSH-BUTTONs
FT245BL USB Interface
Reach Display Interface
C
DE
F
G
H
I J K
micro SD Card (2GB)
FIFO_USB_N
FIFO_USB_P
FTDI_POWER
DDR_SDRAM_ADDR7
USB_VBUS
USB_D_N
USB_D_P
TP
176
TP172
TP175
FPGA_SD_TXD
6 9
2
3
5
7
4 1 8J64
DDR_SDRAM_CLK_P
USB_D_N
TP177
U67
P3V3D_CP2102
DDR_SDRAM_BA0
U75
P3V3D_RST
R52
1
R57
3
R57
2
R52
2
R52
0
R57
1
R51
9
R57
0
R51
8
R52
3
FPGA_SLOTID1
FPGA_HWID1
DDR_SDRAM_CLK_PDDR_SDRAM_CLK_N
TP156TP155TP158TP157
TP154TP153
TP152TP151
TP150
TP149
J59
U1
C127 C
509
J55
J58
R212
REACH_RX
REACH_TX
FPGA_REACH_RX
FPGA_REACH_TX
FPGA_REACH_TX
15-B1,15-E3,17-D5,17-E4
FPGA_REACH_RX
C206
C207
C204
C205
C203
P3V3D_REACH
U22
USB_D_P
R596
R597
R217
L27
L24
C130
P5VD_UI
FPGA_S3A_BOARD_RSTNFPGA_V5_BOARD_RSTNCPLD_BOARD_RSTN
17-B3,17-E5,22-C1,22-D3
FPGA_LOCAL_RSTN
FPGA_S3A_BOARD_RSTN
FPGA_V5_BOARD_RSTN
CPLD_BOARD_RSTN
P5VA_USBP5VD_USB
P3V3D_RST
R32
3
NC
R13
3
C517
C510
FPGA_HWID[1:0]FPGA_SLOTID[2:0]
15-B1,15-C3,15-D3,17-D217-E515-B1,15-C3,15-D3,17-D217-E5
15-B1,15-C1,15-D5,17-C217-E5
15-D3,15-E1,17-E515-D3,15-E1,17-E5
FPGA_HWID0
FPGA_SLOTID0
FPGA_SLOTID2
C520
P3V3D_RST
P3V3D
FPGA_LA_DATA3
FPGA_LA_CLKJ67
FPGA_FTDI_RSTOUTN
FTDI_USBDP
FPGA_FTDI_RSTOUTN
FPGA_FTDI_DATA[7:0]FPGA_FTDI_TXENFPGA_FTDI_RXFNFPGA_FTDI_PWRENN
15-C3,15-C5,17-B5,17-D1FPGA_FTDI_SI_WU
15-C1,15-C3,17-B5,17-D5
15-C1,15-C3,17-D5
15-C1,15-C3,17-B5,17-D515-C1,15-C3,17-B5,17-D515-C1,15-C3,17-B5,17-D5
FPGA_FTDI_RDNFPGA_FTDI_WRN
FPGA_FTDI_DATA[7:0]
FPGA_FTDI_DATA7
FPGA_FTDI_DATA0
FPGA_FTDI_DATA6FPGA_FTDI_DATA5FPGA_FTDI_DATA4FPGA_FTDI_DATA3FPGA_FTDI_DATA2FPGA_FTDI_DATA1
L25
C129
P5VD
P3V3D_USB
FTDI_XTAL_OUT
C311
FTDI_XTAL_IN
R13
2
FPGA_FTDI_SI_WU
FPGA_RS232_TX
FPGA_FTDI_RXFN
FPGA_FTDI_WRNFPGA_FTDI_RDN
P5VA_USB
R651
C51
2
P5VD_USB
P5VD_USB
R337
FTDI_EESDIOU99
FTDI_EECSFTDI_EESCK
FTDI_XTAL_OUT
C62
3
U12
15-B1,15-E1,17-E5
17-C4,17-E1,19-B1,19-E719-E8
15-D3,15-D5,17-D115-D3,15-D5,17-D1
FPGA_RS232_CTS
FPGA_RS232_TX
FPGA_RS232_RTS
FPGA_RS232_CTSFPGA_RS232_RTS
DDR_SDRAM_CKE
DDR_SDRAM_CSN
R32
2
FPGA_LA_DATA[7:0]
FPGA_LA_CLK
DDR_SDRAM_DATA[15:0]
DDR_SDRAM_BA[1:0]
DDR_SDRAM_ADDR[12:0]
17-C4,17-D4,17-E1,19-D119-E7,19-E8
17-C3,17-E1,18-C3,18-E5
17-C3,17-D3,17-E1,18-C518-D5,18-E5
DDR_SDRAM_UDQS
FPGA_SD_RXD15-D1,15-D3,17-D5
14-D2,14-E1,17-A2,17-D515-B1,15-E1,17-A2,17-D515-B1,15-E1,17-B2,17-D515-B1,15-E1,17-A2,17-D5
FPGA_UI_PROG2FPGA_UI_PROG1FPGA_UI_INTNFPGA_UI_RDY
FPGA_SD_CARD_DETECTFPGA_SD_CLKFPGA_SD_TXD
FPGA_UI_PROG1
FPGA_UI_PROG0
FPGA_UI_INTN
FPGA_UI_MOSI
FPGA_UI_MISO
FPGA_UI_SCK
FPGA_UI_CSN
FP
GA
_SD
_BU
SY
_LE
D
FPGA_UI_SCK
FPGA_UI_MOSI
C10
8
L23
P3V3D_SD
U56
U55
FPGA_UI_RSTN
P3V3D
FPGA_UI_PROG0
TP
171
TP
169
UI_PROG1
UI_RSTN
P3V3D_RST
FPGA_LOCAL_RSTN
FPGA_UI_RSTN
R280UI_PROG1
FPGA_UI_PROG2R281
UI_PROG2
R278
R279UI_PROG0
UI_INTN
R277
R276UI_MOSI
UI_MISO
R283
R282UI_CSN
UI_SCK
FPGA_UI_RDYR275
UI_RDY
FPGA_UI_CSN
FPGA_UI_MISO
UI_CSNUI_PROG0
S3
FPGA_PUSHBUTTON[2:0]
FPGA_LEDS[3:0]
FPGA_RS232_RX
P2V5D_S3A
FPGA_CONFIG_DONE
U46
NC
D24
R99
FP
GA
_LE
DS
1
FP
GA
_LE
DS
0
FP
GA
_LE
DS
2
FP
GA
_LE
DS
3
FPGA_LEDS[3:0]
R98
DDR_SDRAM_CSN
U48
C498
C499
C500
C501
C502
DDR_SDRAM_BA1
C495
DDR_SDRAM_CKE
DDR_SDRAM_CASNDDR_SDRAM_RASN
DDR_SDRAM_WENDDR_SDRAM_DATA1DDR_SDRAM_DATA0
FPGA_PUSHBUTTON0
P3V3D
D25
R100
D23
R13
0
R12
9
TP
178
R103
D28
C51
9
R10
2
D27
C15
1
R13
4
C15
0
C14
9
FPGA_PUSHBUTTON2
FPGA_PUSHBUTTON1
C497
C496
C363
FPGA_LA_DATA2FPGA_LA_DATA1FPGA_LA_DATA0
P1V25D_DDR_VREF
DDR_SDRAM_DATA2DDR_SDRAM_DATA3DDR_SDRAM_DATA4DDR_SDRAM_DATA5DDR_SDRAM_DATA6DDR_SDRAM_DATA7DDR_SDRAM_DATA8DDR_SDRAM_DATA9DDR_SDRAM_DATA10DDR_SDRAM_DATA11DDR_SDRAM_DATA12DDR_SDRAM_DATA13DDR_SDRAM_DATA14DDR_SDRAM_DATA15
DDR_SDRAM_UDQS
DDR_SDRAM_LDMDDR_SDRAM_UDM
DDR_SDRAM_LDQS
DDR_SDRAM_ADDR1DDR_SDRAM_ADDR2DDR_SDRAM_ADDR3DDR_SDRAM_ADDR4DDR_SDRAM_ADDR5DDR_SDRAM_ADDR6
DDR_SDRAM_ADDR8DDR_SDRAM_ADDR9DDR_SDRAM_ADDR10DDR_SDRAM_ADDR11DDR_SDRAM_ADDR12
DDR_SDRAM_ADDR0
DDR_SDRAM_LDM
DDR_SDRAM_LDQSDDR_SDRAM_UDM
DDR_SDRAM_RASNDDR_SDRAM_CASNDDR_SDRAM_WEN
DDR_SDRAM_CLK_N
P3V3D_RST
C508
TP159
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
S4
S5
S6
P3V3D_SDP3V3D
R101
D26
TP
170
TP
168
TP
167
J38
TP
166
TP
165
TP
164
TP
163
TP
162
UI_PROG2UI_RDY
UI_MOSIUI_INTNUI_MISO
UI_SCK
FPGA_SD_BUSY_LED
R284
UI_RSTN
15-C1,15-E5,17-A2,17-E115-B1,15-E5,17-B2,17-E115-B1,15-E5,17-A2,17-E114-D2,14-E5,17-A2,17-E114-E3,14-E5,17-A2,17-E1
17-D3,17-E1,18-D3,18-E517-D3,17-E1,18-C3,18-E517-D3,17-E1,18-C3,18-E517-D3,17-E1,18-D3,18-E517-D3,17-E1,18-D3,18-E517-D3,17-E1,18-C3,18-E517-D3,17-E1,18-C3,18-E517-C4,17-E1,18-C3,18-E517-C4,17-E1,18-C3,18-E517-C4,17-E1,19-B1,19-E7
19-E8
15-C1,15-D1,15-D5,17-A517-D1
15-C1,15-D5,17-A5,17-D1
15-D3,15-D5,17-D115-D3,15-D5,17-D115-D3,15-D5,17-D1
15-D3,15-D5,17-C5,17-D1
15-B1,15-E1,17-C1,17-E5
C62
2
R131
C51
1
P5VD_USB
FPGA_FTDI_TXEN
FPGA_FTDI_PWRENN
NCFTDI_EECSFTDI_EESCK
NCFTDI_EESDIO
FTDI_USBDM
FTDI_XTAL_IN
P3V3D
C128 C
513
C514
C515
14-D4,14-E5,17-B5,17-D115-C3,15-C5,17-B5,17-D1
FPGA_LA_DATA4FPGA_LA_DATA5FPGA_LA_DATA6FPGA_LA_DATA7
P3V3D_RST
C516
P3V3D_S3A
R285
R286
R287
NC
15-C1,15-E1,17-B3,17-E5
7-D4,17-B3,17-E5
43
4-20-2009_13:35
17 001
XILINX SPARTAN-3A CONTROL FPGA PERIPHERALS
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
P5VD
L26
C518
FTDI_RESETN
C3
L15
P3V3D
P3V3D_REACH
TP60
TP61
TP62
TP63
15-A5,15-E3,17-D1,17-E4
J5REACH_TXREACH_RX
FPGA_RS232_RX
C507
C506
C505
C504
C503
TP173TP174
P3V3D_SD
TP
160
TP
161
FPGA_SD_CARD_DETECT
FPGA_SD_CLKFPGA_SD_RXD
C28
7
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
121
12149
.9
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
0.1U 2
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
0.1U 2
121
121
22.1
1
49.9
121
121
22.1
1
VTTDDRSDRAMFPGA
Address/Control Termination Placement:
Place the series terminations close to the Spartan 3A FPGAPlace parallel terminations just beyond the SDRAM.
*** INPUTS *** *** OUTPUTS ***
Place near DDR SDRAM Terminations
DDR SDRAM Address and Control Terminations
B DDR SDRAM Address TerminationsDDR SDRAM Control TerminationsA
C VTT Termination Decoupling Capacitors
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
FPGA_DDR_SDRAM_CLK_N
FPGA_DDR_SDRAM_CLK_P DDR_SDRAM_CLK_P
DDR_SDRAM_UDMFPGA_DDR_SDRAM_UDM
DDR_SDRAM_BA1
DDR_SDRAM_CLK_N
DDR_SDRAM_ADDR9FPGA_DDR_SDRAM_ADDR9
FPGA_DDR_SDRAM_ADDR10
FPGA_DDR_SDRAM_ADDR11
FPGA_DDR_SDRAM_ADDR12
FPGA_DDR_SDRAM_ADDR0
FPGA_DDR_SDRAM_ADDR6
FPGA_DDR_SDRAM_ADDR4
FPGA_DDR_SDRAM_ADDR5
FPGA_DDR_SDRAM_ADDR1
FPGA_DDR_SDRAM_ADDR2
FPGA_DDR_SDRAM_ADDR[12:0]
FPGA_DDR_SDRAM_ADDR3
FPGA_DDR_SDRAM_ADDR7
FPGA_DDR_SDRAM_ADDR8
DDR_SDRAM_ADDR10
DDR_SDRAM_ADDR11
DDR_SDRAM_ADDR12
DDR_SDRAM_ADDR8
DDR_SDRAM_ADDR7
DDR_SDRAM_ADDR6
DDR_SDRAM_ADDR5
DDR_SDRAM_ADDR4
DDR_SDRAM_ADDR3
DDR_SDRAM_ADDR2
DDR_SDRAM_ADDR1
DDR_SDRAM_ADDR0
DDR_SDRAM_CASN
DDR_SDRAM_BA0
DDR_SDRAM_LDM
DDR_SDRAM_RASN
DDR_SDRAM_WEN
DDR_SDRAM_CSN
DDR_SDRAM_CKEFPGA_DDR_SDRAM_CKE
FPGA_DDR_SDRAM_WEN
FPGA_DDR_SDRAM_CSN
R611
R17
7
R17
1
R74
R607
R18
9
R17
6
C539
P1V25D_DDR_VTT
R619
R620
R621
R598
R599
R600
R601
R602
R606
R605
R604
R603
R610
R609
R608R613
R614
R615
R616
R617
R618
R612
15-C4,18-C1,18-E1
15-C4,15-E5,18-D1,18-E115-B4,15-E5,18-C1,18-E1
15-B4,15-E5,18-C1,18-E1
15-D4,15-E5,18-D1,18-E115-D4,15-E5,18-D1,18-E115-D4,15-E5,18-C1,18-E115-D4,15-E5,18-C1,18-E1
FPGA_DDR_SDRAM_ADDR[12:0]
FPGA_DDR_SDRAM_UDMFPGA_DDR_SDRAM_LDM
DDR_SDRAM_UDM
DDR_SDRAM_ADDR[12:0]
DDR_SDRAM_BA[1:0]
17-C3,17-D3,17-E1,18-C518-D5,18-E5
17-C3,17-E1,18-C3,18-E5
P1V25D_DDR_VTT
FPGA_DDR_SDRAM_LDM
FPGA_DDR_SDRAM_BA1
FPGA_DDR_SDRAM_BA0FPGA_DDR_SDRAM_BA[1:0]
FPGA_DDR_SDRAM_RASN
FPGA_DDR_SDRAM_CASN
FPGA_DDR_SDRAM_BA[1:0]
FPGA_DDR_SDRAM_RASNFPGA_DDR_SDRAM_CASNFPGA_DDR_SDRAM_WENFPGA_DDR_SDRAM_CSN
FPGA_DDR_SDRAM_CLK_N
FPGA_DDR_SDRAM_CLK_PFPGA_DDR_SDRAM_CKE
DDR_SDRAM_LDM
DDR_SDRAM_RASNDDR_SDRAM_CASNDDR_SDRAM_WENDDR_SDRAM_CSNDDR_SDRAM_CLK_NDDR_SDRAM_CLK_PDDR_SDRAM_CKE
17-C4,17-E1,18-C3,18-E517-C4,17-E1,18-C3,18-E5
17-D3,17-E1,18-C3,18-E517-D3,17-E1,18-C3,18-E517-D3,17-E1,18-D3,18-E517-D3,17-E1,18-D3,18-E517-D3,17-E1,18-C3,18-E517-D3,17-E1,18-C3,18-E517-D3,17-E1,18-D3,18-E5
15-B4,15-C4,15-D4,15-E415-E5,18-D3,18-E1
15-C4,15-E5,18-C1,18-E1
15-B4,15-E5,18-C1,18-E1
43
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18 001
DDR SDRAM ADDRESS AND CONTROL TERMINATIONS
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
P1V25D_DDR_VTT
C521
C533
C531
C532
C530
C527
C528
C529
C526
C525
C524
C523
C522
C536
C535
C534
C540
C538
C537
R75
R19
1
R19
2
R18
5
R18
6
R18
7
R18
8
R18
4
R18
3
R18
2
R18
1
R19
0
R17
8
R17
9
R18
0
R17
2
R17
5
R17
4
R17
3
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
D
1
1 2 3 4 5 6 7 8
2 3 4 5 6 7 8
A
B
C
E
D
A
B
C
E
D
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
22.1
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
22.1
1
22.1
1
22.1
1
22.1
1
VTT VTT
*** OUTPUTS ****** INPUTS ***
Data/DQS Termination Placement:
Place the series terminations in between the Spartan 3A FPGA and SDRAMPlace parallel terminations just beyond the SDRAM and FPGA.
DDR
SDRAM
FPGA
DDR SDRAM Data Terminations
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
FPGA_DDR_SDRAM_UDQS
FPGA_DDR_SDRAM_LDQS
FPGA_DDR_SDRAM_DATA15
FPGA_DDR_SDRAM_DATA3
FPGA_DDR_SDRAM_DATA[15:0]
FPGA_DDR_SDRAM_DATA2
FPGA_DDR_SDRAM_DATA1
FPGA_DDR_SDRAM_DATA0
FPGA_DDR_SDRAM_DATA4
FPGA_DDR_SDRAM_DATA5
FPGA_DDR_SDRAM_DATA6
FPGA_DDR_SDRAM_DATA7
FPGA_DDR_SDRAM_DATA8
FPGA_DDR_SDRAM_DATA9
FPGA_DDR_SDRAM_DATA10
FPGA_DDR_SDRAM_DATA11
FPGA_DDR_SDRAM_DATA14
FPGA_DDR_SDRAM_DATA13
FPGA_DDR_SDRAM_DATA12
DDR_SDRAM_UDQS
DDR_SDRAM_LDQS
DDR_SDRAM_DATA[15:0]
DDR_SDRAM_DATA11
DDR_SDRAM_DATA0
DDR_SDRAM_DATA1
DDR_SDRAM_DATA2
DDR_SDRAM_DATA3
DDR_SDRAM_DATA4
DDR_SDRAM_DATA5
DDR_SDRAM_DATA6
DDR_SDRAM_DATA7
DDR_SDRAM_DATA8
DDR_SDRAM_DATA9
DDR_SDRAM_DATA10
DDR_SDRAM_DATA12
DDR_SDRAM_DATA13
DDR_SDRAM_DATA14
DDR_SDRAM_DATA15
R639
R638
R637
R629
R25
3
R22
8
R25
2
R25
9
R26
0
R24
4
R25
7
R25
8
FPGA_DDR_SDRAM_UDQS17-C4,17-E1,19-B1,19-E717-C4,17-E1,19-B1,19-E7
17-C4,17-D4,17-E1,19-D119-E7
DDR_SDRAM_DATA[15:0]
DDR_SDRAM_UDQSDDR_SDRAM_LDQS
FPGA_DDR_SDRAM_DATA[15:0]
R24
6
R23
7
R23
8
R23
9
R24
0
R23
6
R23
5
R23
4
R23
3
R23
2
R23
1
R23
0
R22
9
R22
7
R22
6
R22
5
R623
R622
R633
R632
R631
R630
R628
R627
R626
R624
R625
P1V25D_DDR_VTT P1V25D_DDR_VTT
R636
R635
R634
R24
3
R24
2
R24
1
R24
8
R24
7
R24
5
R25
1
R25
0
R24
9
R25
6
R25
5
R25
4
15-C4,15-E5,19-B8,19-E115-B4,15-E5,19-B8,19-E2
15-B4,15-C4,15-E5,19-D819-E2
342
JEREMY W. WEBB
MEAS_MAIN_BOARD
DDR SDRAM DATA TERMINATIONS
43
4-20-2009_13:35
19 001
FPGA_DDR_SDRAM_LDQS
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
D
1
1 2 3 4 5 6 7 8
2 3 4 5 6 7 8
A
B
C
E
D
A
B
C
E
D1
GND
SCK4SI 2
SO6
V+3
5CS
TMP125AIDBV
0.1U
2
0.1U
2
1
GND
SCK4SI 2
SO6
V+3
5CS
TMP125AIDBV
0.1U
2
0.1U
2
1
GND
SCK4SI 2
SO6
V+3
5CS
TMP125AIDBV
1
GND
SCK4SI 2
SO6
V+3
5CS
TMP125AIDBV
0.1U
2
1
GND
SCK4SI 2
SO6
V+3
5CS
TMP125AIDBV
1
GND
SCK4SI 2
SO6
V+3
5CS
TMP125AIDBV
0.1U
2
*** INPUTS *** *** OUTPUTS ***
Temp Sensor Col. 2
Temp Sensor Col. 1
Temp Sensor Col. 2
Temp Sensor Col. 1
TM
P12
5
TM
P12
5T
MP
125
TM
P12
5T
MP
125
TM
P12
5
1A
2B1B
1C
2A
2C
A Temp Sensor 1A
Temp Sensor 1BB
C Temp Sensor 1C Temp Sensor 2CF
Temp Sensor 2BE
Temp Sensor 2AD
Digital Temperature Sensors
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
Temp sensors will be placed on a 2x3 Grid on the bottom side of the Measurement board.
C545
TP183
TP181
15-C5,15-D1,20-D2
U89
P3V3D
U88
C546
U87
P3V3D
P3V3D
U86
C544C543
U85
P3V3D
P3V3D
C542
C541
U84
P3V3D
FPGA_TMPSENS_2C_MOSI
FPGA_TMPSENS_2B_MOSI
FPGA_TMPSENS_2A_MOSI
FPGA_TMPSENS_1A_MOSI
FPGA_TMPSENS_1B_MOSI
FPGA_TMPSENS_1C_MOSI
FPGA_TMPSENS_1A_CSN
FPGA_TMPSENS_1A_CSN
FPGA_TMPSENS_1A_MOSIFPGA_TMPSENS_1A_SCK FPGA_TMPSENS_2A_MOSI
FPGA_TMPSENS_2A_MISO
FPGA_TMPSENS_2A_SCK
FPGA_TMPSENS_2A_CSN
FPGA_TMPSENS_2B_CSN
FPGA_TMPSENS_2B_SCK
FPGA_TMPSENS_2B_MISO
FPGA_TMPSENS_2B_MOSI
FPGA_TMPSENS_2C_MOSI
FPGA_TMPSENS_2C_MISO
FPGA_TMPSENS_2C_SCK
FPGA_TMPSENS_2C_CSNFPGA_TMPSENS_1C_CSN
FPGA_TMPSENS_1C_SCK
FPGA_TMPSENS_1C_MISO
FPGA_TMPSENS_1C_MOSI
FPGA_TMPSENS_1B_MOSI
FPGA_TMPSENS_1B_MISO
FPGA_TMPSENS_1B_SCK
FPGA_TMPSENS_1B_CSN
FPGA_TMPSENS_1A_MISO
FPGA_TMPSENS_1A_SCK
FPGA_TMPSENS_1B_SCKFPGA_TMPSENS_1B_CSN
FPGA_TMPSENS_1C_SCKFPGA_TMPSENS_1C_CSN
FPGA_TMPSENS_2C_CSNFPGA_TMPSENS_2C_SCK
FPGA_TMPSENS_2B_CSNFPGA_TMPSENS_2B_SCK
FPGA_TMPSENS_2A_SCKFPGA_TMPSENS_2A_CSN
FPGA_TMPSENS_2C_MISOFPGA_TMPSENS_2B_MISOFPGA_TMPSENS_2A_MISO
FPGA_TMPSENS_1C_MISOFPGA_TMPSENS_1B_MISOFPGA_TMPSENS_1A_MISO
15-D1,20-E715-C3,15-D1,20-E715-D1,15-D3,20-E7
15-B3,15-D1,20-E715-B1,15-D1,20-E715-D1,15-D3,20-E715-D3,15-D5,20-E2
15-D3,15-D5,20-E215-D3,15-D5,20-E2
15-B1,15-D5,20-E215-B1,15-D5,20-E215-B1,15-D5,20-E2
15-C3,15-D5,20-E214-D4,14-E5,20-E215-B3,15-D5,20-E2
15-C3,15-C5,20-D215-C5,15-D3,20-D215-C5,15-D3,20-D2
15-C3,15-C5,20-D215-C3,15-C5,20-D215-C3,15-C5,20-D2
15-C5,15-D1,20-D215-C5,15-D1,20-D2
TP179
TP180
TP182
TP184
TP185
TP186
TP187
TP188
TP189
TP190
TP191
TP192
TP193
TP194
TP195
TP196TP197
TP198
TP199
TP200
TP201
TP202
342
JEREMY W. WEBB
MEAS_MAIN_BOARD
DIGITAL TEMPERATURE SENSORS
43
4-20-2009_13:35
20 001
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
Data Path FPGA Digital Design
43
3-27-2009_12:24
21 001
DATA PATH FPGA DIGITAL DESIGN
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
4.99
K
1
4.99
K
1
NL
1
NL
1
NL
1
NL
1
NL
1
NL
11
76SB03T
12
3
-OP
EN
-
ROCKER
4.99
K
1
4.99
K
1
NL
1
NL
1
NL
1
NL
1
NL
1
NL
1
4.99
K
1
4.99
K
1
7
NIC1
TP4
GND8
2 VIN
TEMP3 5TRIM
VOUT 6
ADR03ARZ
AL12 B4_VCCO_4_D0AG14 B4_VCCO_4_D1
AG22 B4_IO_L0P_GC_D15_4AH22 B4_IO_L0N_GC_D14_4AH12 B4_IO_L1P_GC_D13_4AG13 B4_IO_L1N_GC_D12_4AH20 B4_IO_L2P_GC_D11_4AH19 B4_IO_L2N_GC_D10_4AH14 B4_IO_L3P_GC_D9_4AH13 B4_IO_L3N_GC_D8_4
AG21 B4_IO_L4P_GC_4AG20 B4_IO_L4N_GC_VREF_4AH15 B4_IO_L5P_GC_4AG15 B4_IO_L5N_GC_4AG18 B4_IO_L6P_GC_4AF19 B4_IO_L6N_GC_4AH17 B4_IO_L7P_GC_VRN_4AG16 B4_IO_L7N_GC_VRP_4AF18 B4_IO_L8P_CC_GC_4AE18 B4_IO_L8N_CC_GC_4
AH18 B4_IO_L9P_CC_GC_4AG17 B4_IO_L9N_CC_GC_4
C16B5_VCCO_5_D0F17B5_VCCO_5_D1B19B5_VCCO_5_D2
B16NOPAD/UNCONNECTED_D0B15NOPAD/UNCONNECTED_D1A15NOPAD/UNCONNECTED_D2A14NOPAD/UNCONNECTED_D3B17NOPAD/UNCONNECTED_D4A16NOPAD/UNCONNECTED_D5C14NOPAD/UNCONNECTED_D6
C15NOPAD/UNCONNECTED_D7E19NOPAD/UNCONNECTED_D8F19NOPAD/UNCONNECTED_D9C17NOPAD/UNCONNECTED_D10D17NOPAD/UNCONNECTED_D11E21NOPAD/UNCONNECTED_D12D20NOPAD/UNCONNECTED_D13D16NOPAD/UNCONNECTED_D14D15NOPAD/UNCONNECTED_D15G20NOPAD/UNCONNECTED_D16
F20NOPAD/UNCONNECTED_D17D14NOPAD/UNCONNECTED_D18E14NOPAD/UNCONNECTED_D19E17NOPAD/UNCONNECTED_D20E16NOPAD/UNCONNECTED_D21F21NOPAD/UNCONNECTED_D22G21NOPAD/UNCONNECTED_D23E18NOPAD/UNCONNECTED_D24D19NOPAD/UNCONNECTED_D25D21NOPAD/UNCONNECTED_D26
D22NOPAD/UNCONNECTED_D27F18NOPAD/UNCONNECTED_D28G18NOPAD/UNCONNECTED_D29E22NOPAD/UNCONNECTED_D30F23NOPAD/UNCONNECTED_D31G17NOPAD/UNCONNECTED_D32F16NOPAD/UNCONNECTED_D33D24NOPAD/UNCONNECTED_D34E23NOPAD/UNCONNECTED_D35F14NOPAD/UNCONNECTED_D36
F15NOPAD/UNCONNECTED_D37F24NOPAD/UNCONNECTED_D38E24NOPAD/UNCONNECTED_D39
xc5vsx50t-3ff1136(4 of 11)
55
55
5
5
5 5
5
5
5
5
5
555
5
5
5
5 55
5
5
5
5 5 5
5
5
5
5
5
5
5
5
5 5 5
5
5
5
5
4
44
4
4444
44
4
4 4
4
4
4
4
4
4
4
4
4
0.1U
2 1U2
1U2
390-OHM
0.0
1
0.01
0.01
49.9
1
49.9
1
390-OHM
1
76SB03T
12
3
-OP
EN
-
ROCKER
100
100
AA22 B0_VCCO_0_D0AD23 B0_VCCO_0_D1
W18 B0_DXP_0W17 B0_DXN_0T18 B0_AVDD_0T17 B0_AVSS_0U18 B0_VP_0V17 B0_VN_0V18 B0_VREFP_0U17 B0_VREFN_0
L23 B0_VBATT_0M22 B0_PROGRAM_B_0M23 B0_HSWAPEN_0P15 B0_D_IN_0M15 B0_DONE_0N15 B0_CCLK_0N14 B0_INIT_B_0N22 B0_CS_B_0N23 B0_RDWR_B_0
AB23 B0_RSVD_D0
AC23 B0_RSVD_D1AB15 B0_TCK_0AD21 B0_M0_0AD22 B0_M2_0AC22 B0_M1_0AC14 B0_TMS_0AC15 B0_TDI_0AD15 B0_D_OUT_BUSY_0AD14 B0_TDO_0
AM19 B2_VCCO_2_D0AH21 B2_VCCO_2_D1
AE13 B2_IO_L0P_CC_RS1_2AE12 B2_IO_L0N_CC_RS0_2AF23 B2_IO_L1P_CC_A25_2AG23 B2_IO_L1N_CC_A24_2AF13 B2_IO_L2P_A23_2AG12 B2_IO_L2N_A22_2AE22 B2_IO_L3P_A21_2AE23 B2_IO_L3N_A20_2
AE14 B2_IO_L4P_FCS_B_2AF14 B2_IO_L4N_VREF_FOE_B_MOSI_2AF20 B2_IO_L5P_FWE_B_2AF21 B2_IO_L5N_CSO_B_2AF15 B2_IO_L6P_D7_2AE16 B2_IO_L6N_D6_2AE21 B2_IO_L7P_D5_2AD20 B2_IO_L7N_D4_2AF16 B2_IO_L8P_D3_2AE17 B2_IO_L8N_D2_FS2_2
AE19 B2_IO_L9P_D1_FS1_2AD19 B2_IO_L9N_D0_FS0_2
D13B1_VCCO_1_D0G14B1_VCCO_1_D1
L21B1_IO_L0P_A19_1L20B1_IO_L0N_A18_1L15B1_IO_L1P_A17_1L16B1_IO_L1N_A16_1J22B1_IO_L2P_A15_D31_1K21B1_IO_L2N_A14_D30_1K16B1_IO_L3P_A13_D29_1J15B1_IO_L3N_A12_D28_1
G22B1_IO_L4P_A11_D27_1H22B1_IO_L4N_VREF_A10_D26_1L14B1_IO_L5P_A9_D25_1K14B1_IO_L5N_A8_D24_1K23B1_IO_L6P_A7_D23_1K22B1_IO_L6N_A6_D22_1J12B1_IO_L7P_A5_D21_1H12B1_IO_L7N_A4_D20_1G23B1_IO_L8P_CC_A3_D19_1H23B1_IO_L8N_CC_A2_D18_1
K13B1_IO_L9P_CC_A1_D17_1K12B1_IO_L9N_CC_A0_D16_1
E20B3_VCCO_3_D0D23B3_VCCO_3_D1
H17B3_IO_L0P_CC_GC_3H18B3_IO_L0N_CC_GC_3K17B3_IO_L1P_CC_GC_3L18B3_IO_L1N_CC_GC_3G15B3_IO_L2P_GC_VRN_3G16B3_IO_L2N_GC_VRP_3K18B3_IO_L3P_GC_3J19B3_IO_L3N_GC_3
J16B3_IO_L4P_GC_3J17B3_IO_L4N_GC_VREF_3L19B3_IO_L5P_GC_3K19B3_IO_L5N_GC_3H14B3_IO_L6P_GC_3H15B3_IO_L6N_GC_3J20B3_IO_L7P_GC_3J21B3_IO_L7N_GC_3J14B3_IO_L8P_GC_3H13B3_IO_L8N_GC_3
H19B3_IO_L9P_GC_3H20B3_IO_L9N_GC_3
xc5vsx50t-3ff1136(3 of 11)
3 3
3
3
3 3
3
33 3
3
3
3 3
3 33
3 3 3
3
3
22
2
2
2
2
2 22
2 2 22
2 2
2
2
2 2
2
2
2
111 1
1
11
1
1
1
1
1 11
1
1
1
1
11
1
1
00
00
0
0 0
0
0
0 0
0
0
00 0 0
0
0
0
0 0
00 0
00
0
0
Board Reset
FT245BL USB Interface
MicroSD Interface
Data Path FPGA Control
Virtex 5 SX50T: VCCO_0 = 3.3V, VCCO_2 = 3.3VSpartan 3A: VCCO_2 = 3.3V, VCCAUX = 3.3V
0x03
0xE8
00
0
0
0
1
1
0
1
11
1
1
0
0
1
011
111
M1 M0
000
0
0 1
JTAG/Bndry Scan 1 0 1
1
Slave SelectMAP
1Master SPI 0 0
Master BPI-Up
Master BPI-Down
0
0 1
01 8, 16 bits
1 bit
8, 16, 32 bits
1 bit
Output
Input
Input
Input (TCK)
For more information see Xilinx Virtex 5 Configuration Guide (UG191)
Slave Serial
CONFIG MODE M2
Master Serial
DATA WIDTH
1 bit Output
CCLK Direction
1 bit Output
Output
Output8, 16 bits
8, 16 bits
"Master SelectMAP"
must be placed near the Configuration PROM.
The end terminationtransmission line.
and is a 50 Ohm controlled impedance
FPGA_CCLK requires an end termination
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
FS2 FS1 FS0
1
11 0
1
0 0
0
0x0B
0x55
0x52
RESERVED
HEX CMD CODE
0xFF
RCMD[7:0]
See pages 46-49 of Xilinx UG192 for PC Design Guidlines
Virtex-5 SX50T FPGA Configuration Mode Virtex-5 SX50T FPGA SPI Mode
** INPUTS **
SPI Configuration
JTAG Configuration
** OUTPUTS **
SPI Configuration
JTAG Configuration
USB to RS-232
Trigger Output
the V5 System Monitormore information onSee Xilinx UG192 for
Xilinx Virtex-5 SX50T Configuration
System Monitor Precision ReferenceC D
FPGA_CCLK Stub Length from S3A to SPI Flash < 12.5 mm
NOTES:
E
LVDS Clocks
Data Path FPGA Control
MicroSD Interface
100MHz FPGA Clock
Auxiliary Input
Trigger Input
FT245BL USB Interface
Custom Configuration
Virtex-5 SX50T CCLKB
Custom Configuration
Logic Analyzer
LVPECL Clocks
USB to RS-232 Interface
Debug Push Buttons
Debug LEDs
U69
FPGA_AUX_IN_NFPGA_AUX_IN_P
FPGA_TRIG_OUT_NFPGA_TRIG_OUT_PFPGA_TRIG_IN_NFPGA_TRIG_IN_P
R72
1R
720
V5_FS0
V5_FS2V5_FS1
V5_INIT_B
V5_CONFIG_DONE
V5_PROG_BP3V3D_V5
S3A_SPI_DATA_TO_V5
V5_CCLK
S11
L86
1.2A, 390R
R15
7R
15
R525
R524
TP203
R526 V5_HSWAPEN
NC
NCNC
FPGA_V5_CLK100MHZ_PFPGA_V5_CLK100MHZ_N
P2V5REF P2V5REF_FPGA
P2V5REF_FPGA
P2V5REF_FPGA
VP_VN_SM
22-D1,22-D3,30-C2,30-E5
22-C2,22-D1,30-C2,30-E5
22-D1,22-D3,30-E522-D1,22-D3,30-E5
FPGA_DP_CTRL_GPIO[4:0]15-B3,15-B5,22-D1,22-D3
FPGA_DP_CTRL_GPIO0FPGA_DP_CTRL_GPIO1
FPGA_DP_CTRL_GPIO2FPGA_DP_CTRL_GPIO3FPGA_DP_CTRL_GPIO4
FPGA_BANK3_VRNFPGA_BANK3_VRP
FPGA_BANK3_VRNFPGA_BANK3_VRP
P3V3D_V5
FPGA_V5_FTDI_DATA7FPGA_V5_FTDI_SI_WU
NC
FPGA_V5_LA_DATA0
FPGA_DSP_CLKIN_NFPGA_DSP_CLKIN_P
FPGA_DSP_CLKIN_P
FPGA_ASAP_CLKIN_NFPGA_ASAP_CLKIN_P
FPGA_ASAP_CLKIN_P
FPGA_V5_LA_CLK
FPGA_V5_LA_DATA[7:0]
V5_INIT_BV5_CONFIG_DONE
22-C2,22-D2,22-D5,30-B530-E1
22-D2,22-D5,30-B5,30-E1
FPGA_V5_BOARD_RSTN
V5_PROG_BV5_CCLK
15-E5,22-B2,22-D215-E5,22-D2
15-B1,22-D2,22-D5
22-C1,22-E3,30-D522-C1,22-E3,30-C4,30-D522-C1,22-E3,30-C4,30-D522-C1,22-E3,30-C4,30-D522-C1,22-D3,22-E3,30-C5
30-D5
22-C1,22-D3,35-D3,35-E522-C1,22-D3,35-D3,35-E5
22-D1,22-D3,35-B3,35-E522-D1,22-D3,35-B3,35-E5
22-D1,22-D3,30-B3,30-D522-D1,22-D3,30-B3,30-E5
22-C3,22-D1,30-E5
15-B3,15-B5,22-D1,22-D3
15-B5,15-C3,22-D1,22-D315-B3,15-B5,22-D1,22-D3
12-C3,12-E5,22-E1,22-E3
12-C3,12-E5,22-E1,22-E312-C3,12-E5,22-E1,22-E312-C3,12-E5,22-E1,22-E3
12-A3,12-E5,22-E1,22-E312-A3,12-E5,22-E1,22-E312-B3,12-E5,22-E1,22-E312-B3,12-E5,22-E1,22-E3
FPGA_V5_FTDI_DATA[7:0]
TP204TP205
FPGA_TRIG_OUT_PFPGA_TRIG_OUT_N
22-D3,22-E5,30-E122-D3,22-E5,30-E1
FPGA_TRIG_IN_PFPGA_TRIG_IN_N
FPGA_AUX_IN_PFPGA_AUX_IN_N
FPGA_V5_RS232_TX
FPGA_V5_RS232_CTS
FPGA_V5_CLK100MHZ_NFPGA_V5_CLK100MHZ_P
FPGA_V5_SD_RXD
FPGA_V5_LEDS[3:0]
FPGA_V5_RS232_RTSFPGA_V5_RS232_RX
FPGA_V5_SD_TXDFPGA_V5_SD_CLKFPGA_V5_SD_CARD_DETECTFPGA_V5_SD_BUSY_LED
22-C3,22-E5,30-E122-C3,22-E5,30-E122-C3,22-E5,30-E122-C3,22-E5,30-B4,30-E1
FPGA_DP_CTRL_RSTN
FPGA_DP_CTRL_MOSI
FPGA_DP_CTRL_MISOFPGA_DP_CTRL_INTN
17-B1,22-E522-E5
FPGA_CONFIG_DONEFPGA_INIT_B
14-C3,22-D2,22-E5TDO_TO_JTAG
14-D4,22-D2,22-E114-C3,14-D4,22-D2,22-E114-C3,14-D4,22-D2,22-E1
14-B3,14-C4,14-D3,22-E1
FPGA_PROG_BFPGA_CCLK
P3V3D_V5
V5_CCLK
P3V3D_V5
P3V3D_V5TDI_TO_V5
GNDA_FPGA
P2V5D_V5 P3V3D_V5
GNDA_FPGA
L85
GNDA_FPGA
GNDA_FPGA
C32
3C32
2
NC
NC
NC
C15
P3V3D_V5
FPGA_SRAM_CLK_PFPGA_SRAM_CLK_NFPGA_SDRAM_CLK_P
FPGA_SDRAM_CLK_N
FPGA_ASAP_CLKIN_N
FPGA_DSP_CLKIN_N
P3V3D_V5
U69
U72
P12VFD
NC
NC
GNDA_FPGAGNDA_FPGA
NC
NC
NCNCNC
NCNCNC
NCNC
NC
NC
NCNC
NCNCNC
NCNCNC
NC
NC
NCNC
NCNCNC
NCNCNC
NC
NC
NCNCNC
NCNCNC
S3A_SPI_DATA_TO_V5
TMSTCK
P3V3D_V5
R73
9
R73
8
R57
9
R57
8
R57
7
R57
6
R57
5
R57
4
R73
7
P3V3D_V5P3V3D_V5
R74
2
S12R
585
R58
4
R58
3
R58
2
R58
1
R58
0
R74
1
R74
0
V5_M0V5_M1V5_M2
14-D4,22-E114-D3,22-E1
FPGA_DP_CTRL_SCKFPGA_DP_CTRL_CSN
15-B3,15-C1,22-D3,22-E515-B3,15-C1,22-D3,22-E5
22-D3,22-D5,35-D3,35-E122-D3,22-D5,35-D3,35-E1
FPGA_V5_PUSHBUTTON[1:0]
FPGA_V5_FTDI_RSTOUTN
FPGA_V5_FTDI_TXENFPGA_V5_FTDI_RXFNFPGA_V5_FTDI_PWRENN
FPGA_V5_FTDI_SI_WU
FPGA_V5_FTDI_RDNFPGA_V5_FTDI_WRN
22-D5,22-E3,30-C4,30-E122-D5,22-E3,30-C4,30-E122-D5,22-E3,30-C4,30-E1
V5_FS0V5_FS1
V5_FS2
TDO_TO_JTAGNC
TDI_TO_V5TMSV5_M1V5_M2V5_M0TCK
VP_VN_SM
FPGA_RDWR_BFPGA_CS_B
15-B1,22-D2,22-D5
17-B3,17-E5,22-C1,22-D3
43
4-20-2009_13:35
22 001
XILINX VIRTEX-5 SX50T CONFIGURATION
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
FPGA_V5_SD_RXD
FPGA_DP_CTRL_RSTNFPGA_DP_CTRL_INTN
FPGA_DP_CTRL_MISO
FPGA_DP_CTRL_MOSI
FPGA_DP_CTRL_CSN
FPGA_DP_CTRL_SCK
FPGA_V5_RS232_RXFPGA_V5_RS232_RTS
FPGA_V5_RS232_CTS
FPGA_V5_RS232_TX
FPGA_V5_SD_BUSY_LEDFPGA_V5_SD_CARD_DETECTFPGA_V5_SD_CLKFPGA_V5_SD_TXD
FPGA_SDRAM_CLK_NFPGA_SDRAM_CLK_PFPGA_SRAM_CLK_NFPGA_SRAM_CLK_P
FPGA_V5_LEDS0FPGA_V5_LEDS1FPGA_V5_LEDS2FPGA_V5_LEDS3
FPGA_V5_FTDI_DATA0FPGA_V5_FTDI_DATA1FPGA_V5_FTDI_DATA2FPGA_V5_FTDI_DATA3FPGA_V5_FTDI_DATA4FPGA_V5_FTDI_DATA5FPGA_V5_FTDI_DATA6
FPGA_V5_FTDI_WRNFPGA_V5_FTDI_RDNFPGA_V5_FTDI_RSTOUTNFPGA_V5_FTDI_PWRENNFPGA_V5_FTDI_RXFNFPGA_V5_FTDI_TXEN
FPGA_V5_LA_CLK
FPGA_V5_LA_DATA6FPGA_V5_LA_DATA7
FPGA_V5_LA_DATA5FPGA_V5_LA_DATA4FPGA_V5_LA_DATA3FPGA_V5_LA_DATA2FPGA_V5_LA_DATA1
FPGA_V5_PUSHBUTTON1FPGA_V5_PUSHBUTTON0
NCNCNCNCNC
P3V3D_V5
FPGA_V5_BOARD_RSTN
15-B3,15-B5,22-D1,22-D3
NC
TP245TP252
49.9
1
49.9
1
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
100U 2
56-OHM
1 2
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
49.9
1
AK15 B6_VCCO_6_D0AN16 B6_VCCO_6_D1AJ18 B6_VCCO_6_D2
AH24 NOPAD/UNCONNECTED_D0AJ24 NOPAD/UNCONNECTED_D1AK12 NOPAD/UNCONNECTED_D2AJ12 NOPAD/UNCONNECTED_D3AH23 NOPAD/UNCONNECTED_D4AJ22 NOPAD/UNCONNECTED_D5AL13 NOPAD/UNCONNECTED_D6
AK13 NOPAD/UNCONNECTED_D7AK24 NOPAD/UNCONNECTED_D8AL23 NOPAD/UNCONNECTED_D9AJ14 NOPAD/UNCONNECTED_D10AK14 NOPAD/UNCONNECTED_D11AK23 NOPAD/UNCONNECTED_D12AK22 NOPAD/UNCONNECTED_D13AL15 NOPAD/UNCONNECTED_D14AL14 NOPAD/UNCONNECTED_D15AJ21 NOPAD/UNCONNECTED_D16
AJ20 NOPAD/UNCONNECTED_D17AJ16 NOPAD/UNCONNECTED_D18AJ15 NOPAD/UNCONNECTED_D19AK16 NOPAD/UNCONNECTED_D20AL16 NOPAD/UNCONNECTED_D21AL21 NOPAD/UNCONNECTED_D22AK21 NOPAD/UNCONNECTED_D23AK17 NOPAD/UNCONNECTED_D24AJ17 NOPAD/UNCONNECTED_D25AL19 NOPAD/UNCONNECTED_D26
AL20 NOPAD/UNCONNECTED_D27AK18 NOPAD/UNCONNECTED_D28AL18 NOPAD/UNCONNECTED_D29AJ19 NOPAD/UNCONNECTED_D30AK19 NOPAD/UNCONNECTED_D31AM15 NOPAD/UNCONNECTED_D32AM16 NOPAD/UNCONNECTED_D33AP16 NOPAD/UNCONNECTED_D34AP17 NOPAD/UNCONNECTED_D35AN15 NOPAD/UNCONNECTED_D36
AP15 NOPAD/UNCONNECTED_D37AM17 NOPAD/UNCONNECTED_D38AN17 NOPAD/UNCONNECTED_D39
T27B11_VCCO_11_D0R30B11_VCCO_11_D1V31B11_VCCO_11_D2
B32B11_IO_L0P_11A33B11_IO_L0N_11B33B11_IO_L1P_11C33B11_IO_L1N_11C32B11_IO_L2P_11D32B11_IO_L2N_11C34B11_IO_L3P_11
D34B11_IO_L3N_11G32B11_IO_L4P_11H32B11_IO_L4N_VREF_11F33B11_IO_L5P_11E34B11_IO_L5N_11E32B11_IO_L6P_11E33B11_IO_L6N_11G33B11_IO_L7P_11F34B11_IO_L7N_11J32B11_IO_L8P_CC_11
H33B11_IO_L8N_CC_11H34B11_IO_L9P_CC_11J34B11_IO_L9N_CC_11L34B11_IO_L10P_CC_SM15P_11K34B11_IO_L10N_CC_SM15N_11K33B11_IO_L11P_CC_SM14P_11K32B11_IO_L11N_CC_SM14N_11N33B11_IO_L12P_VRN_11M33B11_IO_L12N_VRP_11L33B11_IO_L13P_11
M32B11_IO_L13N_11P34B11_IO_L14P_11N34B11_IO_L14N_VREF_11P32B11_IO_L15P_SM13P_11N32B11_IO_L15N_SM13N_11T33B11_IO_L16P_SM12P_11R34B11_IO_L16N_SM12N_11R33B11_IO_L17P_SM11P_11R32B11_IO_L17N_SM11N_11U33B11_IO_L18P_SM10P_11
T34B11_IO_L18N_SM10N_11U32B11_IO_L19P_SM9P_11U31B11_IO_L19N_SM9N_11
xc5vsx50t-3ff1136(5 of 11)
11
11
11
1111
11
11
11
11
11
11
1111 11
11
11
11
11 11
11
11
111111
11
11
11
11
11
11
11
11
11
111111
11
11
1111
11
11
11
6
6
6
6
6
6
6
6 6
6
6
6 66
66
6666
6
6 6
66
6
6 6
6
6
6
6
6 6
6 6
6
6
6
6
6
6
6
N6 B12_VCCO_12_D0T7 B12_VCCO_12_D1M9 B12_VCCO_12_D2
M6 B12_IO_L0P_12M5 B12_IO_L0N_12N8 B12_IO_L1P_12N7 B12_IO_L1N_12M7 B12_IO_L2P_12L6 B12_IO_L2N_12N5 B12_IO_L3P_12
P5 B12_IO_L3N_12L4 B12_IO_L4P_12L5 B12_IO_L4N_VREF_12P7 B12_IO_L5P_12P6 B12_IO_L5N_12K7 B12_IO_L6P_12K6 B12_IO_L6N_12R6 B12_IO_L7P_12T6 B12_IO_L7N_12J6 B12_IO_L8P_CC_12
J5 B12_IO_L8N_CC_12R7 B12_IO_L9P_CC_12R8 B12_IO_L9N_CC_12T8 B12_IO_L10P_CC_12U7 B12_IO_L10N_CC_12H7 B12_IO_L11P_CC_12J7 B12_IO_L11N_CC_12R9 B12_IO_L12P_VRN_12P9 B12_IO_L12N_VRP_12H5 B12_IO_L13P_12
G5 B12_IO_L13N_12R11 B12_IO_L14P_12P10 B12_IO_L14N_VREF_12
F5 B12_IO_L15P_12F6 B12_IO_L15N_12
T10 B12_IO_L16P_12T11 B12_IO_L16N_12G6 B12_IO_L17P_12G7 B12_IO_L17N_12T9 B12_IO_L18P_12
U10 B12_IO_L18N_12E6 B12_IO_L19P_12E7 B12_IO_L19N_12
W28B13_VCCO_13_D0AB29B13_VCCO_13_D1AA32B13_VCCO_13_D2
V32B13_IO_L0P_SM8P_13V33B13_IO_L0N_SM8N_13W34B13_IO_L1P_SM7P_13V34B13_IO_L1N_SM7N_13Y33B13_IO_L2P_SM6P_13AA33B13_IO_L2N_SM6N_13AA34B13_IO_L3P_SM5P_13
Y34B13_IO_L3N_SM5N_13Y32B13_IO_L4P_13W32B13_IO_L4N_VREF_13AC34B13_IO_L5P_SM4P_13AD34B13_IO_L5N_SM4N_13AC32B13_IO_L6P_SM3P_13AB32B13_IO_L6N_SM3N_13AC33B13_IO_L7P_SM2P_13AB33B13_IO_L7N_SM2N_13AF33B13_IO_L8P_CC_SM1P_13
AE33B13_IO_L8N_CC_SM1N_13AF34B13_IO_L9P_CC_SM0P_13AE34B13_IO_L9N_CC_SM0N_13AH34B13_IO_L10P_CC_13AJ34B13_IO_L10N_CC_13AD32B13_IO_L11P_CC_13AE32B13_IO_L11N_CC_13AG33B13_IO_L12P_VRN_13AH33B13_IO_L12N_VRP_13AK34B13_IO_L13P_13
AK33B13_IO_L13N_13AG32B13_IO_L14P_13AH32B13_IO_L14N_VREF_13AJ32B13_IO_L15P_13AK32B13_IO_L15N_13AL34B13_IO_L16P_13AL33B13_IO_L16N_13AM33B13_IO_L17P_13AM32B13_IO_L17N_13AN34B13_IO_L18P_13
AN33B13_IO_L18N_13AN32B13_IO_L19P_13AP32B13_IO_L19N_13
xc5vsx50t-3ff1136(6 of 11)
13 13
13
13
13
13 13
1313
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
1313
13
13
13
13
1313
1313
131313
13
13
13
13
1212
1212
12
12
12
12
12 12
1212
1212
12
12
1212
12 12
12
12
12
12
12
12
12
12
12
12
12 12
12 12
12 12
12
12
12 12
12
12
12
M29 B15_VCCO_15_D0L32 B15_VCCO_15_D1P33 B15_VCCO_15_D2
E29 B15_IO_L0P_15F29 B15_IO_L0N_15G30 B15_IO_L1P_15F30 B15_IO_L1N_15H29 B15_IO_L2P_15J29 B15_IO_L2N_15F31 B15_IO_L3P_15
E31 B15_IO_L3N_15L29 B15_IO_L4P_15K29 B15_IO_L4N_VREF_15H30 B15_IO_L5P_15G31 B15_IO_L5N_15J30 B15_IO_L6P_15J31 B15_IO_L6N_15L30 B15_IO_L7P_15M30 B15_IO_L7N_15N29 B15_IO_L8P_CC_15
P29 B15_IO_L8N_CC_15K31 B15_IO_L9P_CC_15L31 B15_IO_L9N_CC_15P31 B15_IO_L10P_CC_15P30 B15_IO_L10N_CC_15M31 B15_IO_L11P_CC_15N30 B15_IO_L11N_CC_15R28 B15_IO_L12P_VRN_15R29 B15_IO_L12N_VRP_15T31 B15_IO_L13P_15
R31 B15_IO_L13N_15U30 B15_IO_L14P_15T30 B15_IO_L14N_VREF_15T28 B15_IO_L15P_15T29 B15_IO_L15N_15U27 B15_IO_L16P_15U28 B15_IO_L16N_15R26 B15_IO_L17P_15R27 B15_IO_L17N_15U26 B15_IO_L18P_15
T26 B15_IO_L18N_15U25 B15_IO_L19P_15T25 B15_IO_L19N_15
AE30B17_VCCO_17_D0AH31B17_VCCO_17_D1AD33B17_VCCO_17_D2
W24B17_IO_L0P_17V24B17_IO_L0N_17Y26B17_IO_L1P_17W26B17_IO_L1N_17V25B17_IO_L2P_17W25B17_IO_L2N_17Y27B17_IO_L3P_17
W27B17_IO_L3N_17V30B17_IO_L4P_17W30B17_IO_L4N_VREF_17V28B17_IO_L5P_17V27B17_IO_L5N_17W31B17_IO_L6P_17Y31B17_IO_L6N_17W29B17_IO_L7P_17V29B17_IO_L7N_17Y28B17_IO_L8P_CC_17
Y29B17_IO_L8N_CC_17AB31B17_IO_L9P_CC_17AA31B17_IO_L9N_CC_17AB30B17_IO_L10P_CC_17AC30B17_IO_L10N_CC_17AA29B17_IO_L11P_CC_17AA30B17_IO_L11N_CC_17AD31B17_IO_L12P_VRN_17AE31B17_IO_L12N_VRP_17AD30B17_IO_L13P_17
AC29B17_IO_L13N_17AF31B17_IO_L14P_17AG31B17_IO_L14N_VREF_17AE29B17_IO_L15P_17AD29B17_IO_L15N_17AJ31B17_IO_L16P_17AK31B17_IO_L16N_17AF29B17_IO_L17P_17AF30B17_IO_L17N_17AJ30B17_IO_L18P_17
AH30B17_IO_L18N_17AH29B17_IO_L19P_17AG30B17_IO_L19N_17
xc5vsx50t-3ff1136(7 of 11)
17
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1515 15
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15 15
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15
AC6 B18_VCCO_18_D0W8 B18_VCCO_18_D1
AB9 B18_VCCO_18_D2
AC4 B18_IO_L0P_18AC5 B18_IO_L0N_18AB6 B18_IO_L1P_18AB7 B18_IO_L1N_18AA5 B18_IO_L2P_18AB5 B18_IO_L2N_18AC7 B18_IO_L3P_18
AD7 B18_IO_L3N_18Y8 B18_IO_L4P_18Y9 B18_IO_L4N_VREF_18
AD4 B18_IO_L5P_18AD5 B18_IO_L5N_18AA6 B18_IO_L6P_18
Y7 B18_IO_L6N_18AD6 B18_IO_L7P_18AE6 B18_IO_L7N_18W6 B18_IO_L8P_CC_18
Y6 B18_IO_L8N_CC_18AE7 B18_IO_L9P_CC_18AF6 B18_IO_L9N_CC_18AG5 B18_IO_L10P_CC_18AF5 B18_IO_L10N_CC_18W7 B18_IO_L11P_CC_18V7 B18_IO_L11N_CC_18
AH5 B18_IO_L12P_VRN_18AG6 B18_IO_L12N_VRP_18Y11 B18_IO_L13P_18
W11 B18_IO_L13N_18AH7 B18_IO_L14P_18AG7 B18_IO_L14N_VREF_18W10 B18_IO_L15P_18
W9 B18_IO_L15N_18AJ7 B18_IO_L16P_18AJ6 B18_IO_L16N_18
V8 B18_IO_L17P_18U8 B18_IO_L17N_18
AK7 B18_IO_L18P_18
AK6 B18_IO_L18N_18V10 B18_IO_L19P_18
V9 B18_IO_L19N_18
J28B19_VCCO_19_D0E30B19_VCCO_19_D1H31B19_VCCO_19_D2
K24B19_IO_L0P_19L24B19_IO_L0N_19L25B19_IO_L1P_19L26B19_IO_L1N_19J24B19_IO_L2P_19J25B19_IO_L2N_19M25B19_IO_L3P_19
M26B19_IO_L3N_19J27B19_IO_L4P_19J26B19_IO_L4N_VREF_19G25B19_IO_L5P_19G26B19_IO_L5N_19H25B19_IO_L6P_19H24B19_IO_L6N_19F25B19_IO_L7P_19F26B19_IO_L7N_19G27B19_IO_L8P_CC_19
H27B19_IO_L8N_CC_19H28B19_IO_L9P_CC_19G28B19_IO_L9N_CC_19E28B19_IO_L10P_CC_19F28B19_IO_L10N_CC_19E26B19_IO_L11P_CC_19E27B19_IO_L11N_CC_19N27B19_IO_L12P_VRN_19M27B19_IO_L12N_VRP_19K28B19_IO_L13P_19
L28B19_IO_L13N_19K27B19_IO_L14P_19K26B19_IO_L14N_VREF_19M28B19_IO_L15P_19N28B19_IO_L15N_19P26B19_IO_L16P_19P27B19_IO_L16N_19N24B19_IO_L17P_19P24B19_IO_L17N_19P25B19_IO_L18P_19
N25B19_IO_L18N_19R24B19_IO_L19P_19T24B19_IO_L19N_19
xc5vsx50t-3ff1136(8 of 11)
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DAC5682 Data/Clock
** INPUTS **
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
AsAP 1 Data Input
AsAP 1 Data Output
SRAM Read Data
AsAP 1 Data Input
** OUTPUTS **
AsAP 1 Data Output
SRAM Read Clock
Xilinx Virtex-5 SX50T I/O
B DDR2/QDR-II Reference
SRAM Write Data
SRAM Control
SDRAM Signals
U69
FPGA_DAC_SYNC_PFPGA_DAC_SYNC_N
NC
NC
FPGA_DDR2_SDRAM_DQSN_NC6FPGA_DDR2_SDRAM_DQ54
FPGA_DDR2_SDRAM_CK_N1FPGA_DDR2_SDRAM_CK_P1FPGA_DDR2_SDRAM_DQ44
FPGA_DDR2_SDRAM_CK_N0FPGA_DDR2_SDRAM_CK_P0FPGA_DDR2_SDRAM_DQSN_NC2
FPGA_DDR2_SDRAM_DQSN_NC7FPGA_DDR2_SDRAM_DQS7
FPGA_DDR2_SDRAM_DQSN_NC5FPGA_DDR2_SDRAM_DQS5
FPGA_DDR2_SDRAM_DQSN_NC4FPGA_DDR2_SDRAM_DQS4
FPGA_DDR2_SDRAM_DQS3
FPGA_DDR2_SDRAM_DQS2
FPGA_DDR2_SDRAM_DQSN_NC0
FPGA_DDR2_SDRAM_DQS0FPGA_DDR2_SDRAM_DM1
FPGA_DDR2_SDRAM_DQS1FPGA_DDR2_SDRAM_DQSN_NC1
FPGA_DDR2_SDRAM_A1FPGA_DDR2_SDRAM_A2
FPGA_DDR2_SDRAM_A4
FPGA_DDR2_SDRAM_A6
FPGA_DDR2_SDRAM_A7FPGA_DDR2_SDRAM_A11
FPGA_DDR2_SDRAM_A3FPGA_DDR2_SDRAM_A0
FPGA_DDR2_SDRAM_A9
FPGA_DDR2_SDRAM_A5
FPGA_DDR2_SDRAM_A8
FPGA_DDR2_SDRAM_A12
FPGA_DDR2_SDRAM_BA2FPGA_DDR2_SDRAM_BA1
FPGA_DDR2_SDRAM_A13FPGA_DDR2_SDRAM_A10
FPGA_DDR2_SDRAM_DQ58FPGA_DDR2_SDRAM_DQ59
FPGA_DDR2_SDRAM_DQ62
FPGA_DDR2_SDRAM_DQ63FPGA_DDR2_SDRAM_DM7
FPGA_DDR2_SDRAM_DQ57
FPGA_DDR2_SDRAM_DQ61
FPGA_DDR2_SDRAM_DQ60FPGA_DDR2_SDRAM_DQ56
FPGA_DDR2_SDRAM_DQ35
FPGA_DDR2_SDRAM_DQ39
FPGA_DDR2_SDRAM_DQ38FPGA_DDR2_SDRAM_DQ34
FPGA_DDR2_SDRAM_DM4
FPGA_DDR2_SDRAM_DQ37
FPGA_DDR2_SDRAM_DQ36
FPGA_DDR2_SDRAM_DQ33
FPGA_DDR2_SDRAM_DQ32
FPGA_DDR2_SDRAM_DQ11FPGA_DDR2_SDRAM_DQ15
FPGA_DDR2_SDRAM_DQ14FPGA_DDR2_SDRAM_DQ10
FPGA_DDR2_SDRAM_DQ8
FPGA_DDR2_SDRAM_DQ13
FPGA_DDR2_SDRAM_DQ12
FPGA_DDR2_SDRAM_DQ9
FPGA_DDR2_SDRAM_DQ51
FPGA_DDR2_SDRAM_DQ50FPGA_DDR2_SDRAM_DQ55
FPGA_DDR2_SDRAM_DM6
FPGA_DDR2_SDRAM_DQ49
FPGA_DDR2_SDRAM_DQ53
FPGA_DDR2_SDRAM_DQ52
FPGA_DDR2_SDRAM_DQ48
FPGA_DDR2_SDRAM_DQ47FPGA_DDR2_SDRAM_DQ46
FPGA_DDR2_SDRAM_DQ45
FPGA_DDR2_SDRAM_DM5FPGA_DDR2_SDRAM_DQ41
FPGA_DDR2_SDRAM_DQ42
FPGA_DDR2_SDRAM_DQ43FPGA_DDR2_SDRAM_DQ40
FPGA_DDR2_SDRAM_DQSN_NC3
FPGA_DDR2_SDRAM_DQ26
FPGA_DDR2_SDRAM_DQ27FPGA_DDR2_SDRAM_DQ24
FPGA_DDR2_SDRAM_DM3
FPGA_DDR2_SDRAM_DQ31
FPGA_DDR2_SDRAM_DQ25
FPGA_DDR2_SDRAM_DQ30FPGA_DDR2_SDRAM_DQ29
FPGA_DDR2_SDRAM_DQ28
FPGA_DDR2_SDRAM_DQ17
FPGA_DDR2_SDRAM_DQ23
FPGA_DDR2_SDRAM_DQ22FPGA_DDR2_SDRAM_DM2
FPGA_DDR2_SDRAM_DQ19
FPGA_DDR2_SDRAM_DQ20FPGA_DDR2_SDRAM_DQ18
FPGA_DDR2_SDRAM_DQ16
FPGA_DDR2_SDRAM_DQ3
FPGA_DDR2_SDRAM_DQ2
FPGA_DDR2_SDRAM_DQ7FPGA_DDR2_SDRAM_DQ6
FPGA_DDR2_SDRAM_DQ1
FPGA_DDR2_SDRAM_DM0
FPGA_DDR2_SDRAM_DQ5FPGA_DDR2_SDRAM_DQ4
FPGA_SRAM_WDATA0
FPGA_SRAM_WDATA9
FPGA_SRAM_WDATA1
FPGA_SRAM_WDATA10
FPGA_SRAM_WDATA2
FPGA_SRAM_WDATA11FPGA_SRAM_WDATA3
FPGA_SRAM_WDATA12FPGA_SRAM_WDATA4
FPGA_SRAM_WDATA5FPGA_SRAM_WDATA13
FPGA_SRAM_WDATA14
FPGA_SRAM_WDATA6
FPGA_SRAM_WDATA7
FPGA_SRAM_WDATA15
FPGA_SRAM_WDATA8FPGA_SRAM_WDATA16FPGA_SRAM_WDATA17
FPGA_SRAM_WDATA18
FPGA_SRAM_WDATA19
FPGA_SRAM_WDATA27
FPGA_SRAM_WDATA20FPGA_SRAM_WDATA28
FPGA_SRAM_WDATA29
FPGA_SRAM_WDATA21FPGA_SRAM_WDATA22
FPGA_SRAM_WDATA30FPGA_SRAM_WDATA31
FPGA_SRAM_WDATA23
U69
FPGA_SRAM_WDATA32
FPGA_SRAM_WDATA24
FPGA_SRAM_WDATA33
FPGA_SRAM_WDATA25
FPGA_SRAM_WDATA34FPGA_SRAM_WDATA26
FPGA_SRAM_BWN0
U69
FPGA_SRAM_RDATA30FPGA_SRAM_RDATA21FPGA_SRAM_RDATA29
FPGA_SRAM_RDATA19FPGA_SRAM_RDATA22FPGA_SRAM_RDATA20FPGA_SRAM_RDATA31FPGA_SRAM_RDATA28FPGA_SRAM_RDATA23FPGA_SRAM_RDATA33
FPGA_SRAM_RDATA25FPGA_SRAM_RDATA32
FPGA_SRAM_RDATA27FPGA_SRAM_RDATA24FPGA_SRAM_RDATA34FPGA_SRAM_RDATA35FPGA_SRAM_RDATA26FPGA_SRAM_RDATA18FPGA_SRAM_RDATA17FPGA_SRAM_RDATA16
FPGA_SRAM_RDATA8
FPGA_SRAM_RDATA5FPGA_SRAM_RDATA15FPGA_SRAM_RDATA13FPGA_SRAM_RDATA7FPGA_SRAM_RDATA6FPGA_SRAM_RDATA14
FPGA_SRAM_RDATA1FPGA_SRAM_RDATA3
FPGA_SRAM_RDATA4
FPGA_SRAM_RDATA2FPGA_SRAM_RDATA10FPGA_SRAM_RDATA11FPGA_SRAM_RDATA0FPGA_SRAM_RDATA9
U69
FPGA_ASAP1_CLK_OUTFPGA_ASAP1_REQ_OUT
FPGA_ASAP1_VLD_OUT
P1V8D_V5
FPGA_BANK19_VRPFPGA_BANK19_VRNFPGA_BANK12_VRN
FPGA_BANK12_VRP
FPGA_BANK15_VRNFPGA_BANK15_VRP
FPGA_BANK11_VRNFPGA_BANK11_VRP
FPGA_BANK12_VRPFPGA_BANK12_VRN
23-D3,23-E5,27-B4,27-C227-E1
23-B3,23-D5,28-B2,28-E128-E2,29-C4,29-E1
23-B3,23-E5,28-B2,28-E128-E2,29-C4,29-E1
23-C3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-C3,23-D5,28-B2,28-E128-E2,29-C4,29-E1
FPGA_DDR2_SDRAM_BA2
FPGA_DDR2_SDRAM_BA1
23-B1,23-B4,23-D3,23-E527-A3,27-C2,27-D3,27-E127-E3
23-B1,23-B4,23-C1,23-C423-D3,23-E3,23-E5,27-C127-C2,27-C3,27-C4,27-D127-D2,27-D3,27-D4,27-E127-E4
P2V5D_V5
NCNCNC
23-D4,23-E1,23-E4,28-B428-C4,28-E7,28-E8
23-D4,23-E1,28-A4,28-E728-E8
23-D4,23-E1,28-A4,28-E728-E8
23-D3,23-E1,36-D4,36-E5
23-D3,23-E1,36-C4,36-E523-D3,23-E1,36-D4,36-E5
23-B1,23-B4,23-C1,23-D323-E3,23-E5,27-C1,27-C327-C4,27-D1,27-D2,27-D427-E1,27-E223-B1,23-B4,23-C1,23-D323-E3,23-E5,27-C1,27-C327-C4,27-D1,27-D2,27-D427-E123-B1,23-B4,23-E5,27-C127-D4,27-E123-B1,23-B4,23-E5,27-C127-D4,27-E123-B1,23-B4,23-C1,23-C423-D3,23-E3,23-E5,27-C127-C3,27-C4,27-D1,27-D227-D4,27-E1,27-E2
FPGA_ASAP1_DATA_IN[15:0]
FPGA_ASAP1_VLD_INFPGA_ASAP1_CLK_IN
23-B5,23-D3,36-C3,36-E137-B2,37-D1,37-D2
23-C5,23-D3,36-D3,36-E137-C4,37-D1,37-D2
23-C5,23-D3,23-E3,36-D336-E1,37-C2,37-C4,37-D137-D2
FPGA_ASAP1_REQ_OUT23-C5,23-D3,36-C4,36-E1
P0V9D_MEM_VREF
P0V9D_MEM_VREF
P0V9D_MEM_VREF
P0V9D_MEM_VREF
P0V9D_MEM_VREF
P1V8D_V5
P0V9D_MEM_VREF
P1V8D_V5
P0V9D_MEM_VREF
P1V8D_V5
P1V8D_V5
P1V8D_V5
P1V8D_V5
P1V8D_V5
P0V9D_MEM_VREF
NC
FPGA_BANK15_VRN FPGA_BANK19_VRNFPGA_BANK19_VRP
P0V9D_MEM_VREF
R76
R77
FPGA_BANK11_VRNFPGA_BANK11_VRP
FPGA_SRAM_CQ_CLK_N
FPGA_SRAM_CQ_CLK_P
FPGA_SRAM_BWN2
FPGA_SRAM_BWN1
P0V9D_MEM_VREF
FPGA_SRAM_RDATA[35:0]
FPGA_SRAM_CQ_CLK_P
FPGA_DDR2_SDRAM_DM[7:0]
FPGA_DDR2_SDRAM_DQSN_NC[7:0]
FPGA_DDR2_SDRAM_DQS[7:0]
FPGA_DDR2_SDRAM_DQ[63:0]
FPGA_DDR2_SDRAM_CK_N[1:0]
FPGA_DDR2_SDRAM_CK_P[1:0]
FPGA_DDR2_SDRAM_A[15:0]
FPGA_SRAM_CQ_CLK_N
R79
R78
P0V9D_MEM_VREF
FPGA_BANK15_VRP
R81
R80
NCNC
NC
NCNC
NC
NCNC
NC
NC
NC
NC
NC
NCNC
NC
NCNC
NC
NC
NC
NCNC
NCNC
NC
NC
NC
NCNC
NC
NC
NC
NCNC
P0V9D_VREF
L111
C853
P2V5D_V5
P2V5D_V5
23-D3,23-E1,36-C3,36-E5
FPGA_ASAP1_VLD_OUTFPGA_ASAP1_CLK_OUTFPGA_ASAP1_DATA_OUT[15:0]
FPGA_ASAP1_REQ_IN
43
4-20-2009_13:35
23 001
XILINX VIRTEX-5 SX50T I/O
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
FPGA_DAC_CLK_N
FPGA_DAC_DATA_N15FPGA_DAC_DATA_P15
NC
FPGA_DAC_CLK_P
FPGA_DAC_DATA_P2
FPGA_DAC_DATA_P5FPGA_DAC_DATA_N6
FPGA_DAC_DATA_P10FPGA_DAC_DATA_N11FPGA_DAC_DATA_P11
FPGA_DAC_DATA_P12
FPGA_DAC_DATA_P13
FPGA_DAC_DATA_P14FPGA_DAC_DATA_N14
FPGA_DAC_DATA_N13
FPGA_DAC_DATA_N12
FPGA_DAC_DATA_N10FPGA_DAC_DATA_P9FPGA_DAC_DATA_N9FPGA_DAC_DATA_P8FPGA_DAC_DATA_N8FPGA_DAC_DATA_P7
FPGA_DAC_DATA_N7FPGA_DAC_DATA_P6
FPGA_DAC_DATA_N5FPGA_DAC_DATA_P4FPGA_DAC_DATA_N4FPGA_DAC_DATA_P3FPGA_DAC_DATA_N3
FPGA_DAC_DATA_N2FPGA_DAC_DATA_P1FPGA_DAC_DATA_N1FPGA_DAC_DATA_P0FPGA_DAC_DATA_N0
NCNC
FPGA_ASAP1_DATA_IN0
FPGA_ASAP1_DATA_IN13
FPGA_ASAP1_VLD_INFPGA_ASAP1_REQ_IN
FPGA_ASAP1_CLK_IN
FPGA_ASAP1_DATA_IN1FPGA_ASAP1_DATA_IN2FPGA_ASAP1_DATA_IN3FPGA_ASAP1_DATA_IN4FPGA_ASAP1_DATA_IN5FPGA_ASAP1_DATA_IN6FPGA_ASAP1_DATA_IN7FPGA_ASAP1_DATA_IN8
FPGA_ASAP1_DATA_IN9FPGA_ASAP1_DATA_IN10FPGA_ASAP1_DATA_IN11
FPGA_ASAP1_DATA_IN14FPGA_ASAP1_DATA_IN15
FPGA_ASAP1_DATA_IN12
23-B3,23-B5,23-C3,34-D134-E1
23-B3,23-B5,34-D123-B3,23-B5,34-D123-B3,23-B5,34-E123-B3,23-B5,34-E1
23-B3,23-B5,23-C3,34-D134-E1
FPGA_DAC_CLK_PFPGA_DAC_CLK_NFPGA_DAC_SYNC_PFPGA_DAC_SYNC_N
FPGA_DAC_DATA_N[15:0]
FPGA_DAC_DATA_P[15:0]
FPGA_SRAM_BWN2
FPGA_SRAM_BWN1
FPGA_SRAM_BWN0
23-D3,23-E5,27-B4,27-D327-E1
FPGA_SRAM_WDATA0
FPGA_SRAM_WDATA1
FPGA_SRAM_WDATA2
FPGA_SRAM_WDATA3
FPGA_SRAM_WDATA4
FPGA_SRAM_WDATA5
FPGA_SRAM_WDATA6
FPGA_SRAM_WDATA7
FPGA_SRAM_WDATA8
FPGA_SRAM_WDATA25
FPGA_SRAM_WDATA24
FPGA_SRAM_WDATA23
FPGA_SRAM_WDATA15
FPGA_SRAM_WDATA20
FPGA_SRAM_WDATA19
FPGA_SRAM_WDATA22
FPGA_SRAM_WDATA21
FPGA_SRAM_WDATA10
FPGA_SRAM_WDATA12
FPGA_SRAM_WDATA11
FPGA_SRAM_WDATA14
FPGA_SRAM_WDATA13
FPGA_SRAM_WDATA16
FPGA_SRAM_WDATA18
FPGA_SRAM_WDATA17
FPGA_SRAM_WDATA9
FPGA_SRAM_WDATA34
FPGA_SRAM_WDATA27
FPGA_SRAM_WDATA26
FPGA_SRAM_WDATA32
FPGA_SRAM_WDATA28
FPGA_SRAM_WDATA30
23-C3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-C3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-C3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-C3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-C3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-B3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-B3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-C3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-C3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-C3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-C3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-C3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-C3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-C3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-B3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-B3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-C3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-B3,23-C5,28-B2,28-E128-E2,29-C4,29-E1
23-B3,23-C5,28-B2,28-E128-E2,29-C4,29-E1
23-B3,23-D5,28-C2,28-E128-E2,29-C4,29-E1
23-B3,23-C5,28-B2,28-E128-E2,29-C4,29-E1
23-B3,23-C5,28-B2,28-E128-E2,29-C4,29-E1
23-B3,23-C5,28-B2,28-E128-E2,29-C4,29-E1
23-B3,23-C5,28-B2,28-E128-E2,29-C4,29-E1
23-B3,23-C5,28-B2,28-E128-E2,29-C4,29-E1
23-B3,23-C5,28-B2,28-E128-E2,29-C4,29-E1
23-B3,23-C5,28-B2,28-E128-E2,29-C4,29-E1
23-B3,23-C5,28-B2,28-E128-E2,29-C4,29-E1
23-B3,23-C5,28-B2,28-E128-E2,29-C4,29-E1
23-B3,23-C5,28-B2,28-E128-E2,29-C4,29-E1
23-B3,23-C5,28-B2,28-E128-E2,29-C4,29-E1
23-B3,23-C5,28-B2,28-E128-E2,29-C4,29-E1
23-B3,23-C5,28-B2,28-E128-E2,29-C4,29-E1
23-B3,23-C5,28-B2,28-E128-E2,29-C4,29-E1
R15
4R
153
P2V5D_V5
FPGA_ASAP1_DATA_OUT2FPGA_ASAP1_DATA_OUT1FPGA_ASAP1_DATA_OUT0
FPGA_ASAP1_DATA_OUT5
FPGA_ASAP1_DATA_OUT7FPGA_ASAP1_DATA_OUT6
FPGA_ASAP1_DATA_OUT4FPGA_ASAP1_DATA_OUT3
FPGA_ASAP1_DATA_OUT9FPGA_ASAP1_DATA_OUT8
FPGA_ASAP1_DATA_OUT10
FPGA_ASAP1_DATA_OUT12FPGA_ASAP1_DATA_OUT11
FPGA_ASAP1_DATA_OUT13
FPGA_ASAP1_DATA_OUT15FPGA_ASAP1_DATA_OUT14
FPGA_SRAM_RDATA12
FPGA_SRAM_WDATA33
FPGA_SRAM_WDATA31
FPGA_SRAM_WDATA29
FPGA_DDR2_SDRAM_DQ0
FPGA_DDR2_SDRAM_DQ21
FPGA_DDR2_SDRAM_DQS6
49.9
1
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
49.9
1
49.9
1
AL22 B25_VCCO_25_D0AK25 B25_VCCO_25_D1AN26 B25_VCCO_25_D2
AL29 NOPAD/UNCONNECTED_D0AL30 NOPAD/UNCONNECTED_D1AM31 NOPAD/UNCONNECTED_D2AL31 NOPAD/UNCONNECTED_D3AN30 NOPAD/UNCONNECTED_D4AM30 NOPAD/UNCONNECTED_D5AP30 NOPAD/UNCONNECTED_D6
AP31 NOPAD/UNCONNECTED_D7AM27 NOPAD/UNCONNECTED_D8AL28 NOPAD/UNCONNECTED_D9AP29 NOPAD/UNCONNECTED_D10AN29 NOPAD/UNCONNECTED_D11AP27 NOPAD/UNCONNECTED_D12AN27 NOPAD/UNCONNECTED_D13AN28 NOPAD/UNCONNECTED_D14AM28 NOPAD/UNCONNECTED_D15AN25 NOPAD/UNCONNECTED_D16
AM25 NOPAD/UNCONNECTED_D17AM26 NOPAD/UNCONNECTED_D18AL26 NOPAD/UNCONNECTED_D19AP26 NOPAD/UNCONNECTED_D20AP25 NOPAD/UNCONNECTED_D21AL25 NOPAD/UNCONNECTED_D22AL24 NOPAD/UNCONNECTED_D23AN24 NOPAD/UNCONNECTED_D24AP24 NOPAD/UNCONNECTED_D25AM21 NOPAD/UNCONNECTED_D26
AM20 NOPAD/UNCONNECTED_D27AN23 NOPAD/UNCONNECTED_D28AM23 NOPAD/UNCONNECTED_D29AN20 NOPAD/UNCONNECTED_D30AP20 NOPAD/UNCONNECTED_D31AN22 NOPAD/UNCONNECTED_D32AM22 NOPAD/UNCONNECTED_D33AN18 NOPAD/UNCONNECTED_D34AM18 NOPAD/UNCONNECTED_D35AP22 NOPAD/UNCONNECTED_D36
AP21 NOPAD/UNCONNECTED_D37AN19 NOPAD/UNCONNECTED_D38AP19 NOPAD/UNCONNECTED_D39
xc5vsx50t-3ff1136(11 of 11)
25 25
25
25
25
25
25 25
25
25
25
25
25
25 25
25
25
25 25
25
2525
2525
25
25
2525
25
25
25
25
25
25
25
25
2525
25
25
25
25
25
49.9
1
AF7 B22_VCCO_22_D0AJ8 B22_VCCO_22_D1
AH11 B22_VCCO_22_D2
AN14 B22_IO_L0P_22AP14 B22_IO_L0N_22AB10 B22_IO_L1P_22AA10 B22_IO_L1N_22AN13 B22_IO_L2P_22AM13 B22_IO_L2N_22
AA8 B22_IO_L3P_22
AA9 B22_IO_L3N_22AP12 B22_IO_L4P_22AN12 B22_IO_L4N_VREF_22
AC8 B22_IO_L5P_22AB8 B22_IO_L5N_22
AM12 B22_IO_L6P_22AM11 B22_IO_L6N_22AC10 B22_IO_L7P_22
AC9 B22_IO_L7N_22AL11 B22_IO_L8P_CC_22
AL10 B22_IO_L8N_CC_22AE8 B22_IO_L9P_CC_22AD9 B22_IO_L9N_CC_22
AD10 B22_IO_L10P_CC_22AD11 B22_IO_L10N_CC_22AK11 B22_IO_L11P_CC_22AJ11 B22_IO_L11N_CC_22AF8 B22_IO_L12P_VRN_22AE9 B22_IO_L12N_VRP_22AK8 B22_IO_L13P_22
AK9 B22_IO_L13N_22AF9 B22_IO_L14P_22
AF10 B22_IO_L14N_VREF_22AJ9 B22_IO_L15P_22
AJ10 B22_IO_L15N_22AF11 B22_IO_L16P_22AE11 B22_IO_L16N_22AH9 B22_IO_L17P_22
AH10 B22_IO_L17N_22AG8 B22_IO_L18P_22
AH8 B22_IO_L18N_22AG10 B22_IO_L19P_22AG11 B22_IO_L19N_22
G24B23_VCCO_23_D0C26B23_VCCO_23_D1F27B23_VCCO_23_D2
C20NOPAD/UNCONNECTED_D0B20NOPAD/UNCONNECTED_D1B21NOPAD/UNCONNECTED_D2A21NOPAD/UNCONNECTED_D3C19NOPAD/UNCONNECTED_D4C18NOPAD/UNCONNECTED_D5C22NOPAD/UNCONNECTED_D6
B22NOPAD/UNCONNECTED_D7B18NOPAD/UNCONNECTED_D8A18NOPAD/UNCONNECTED_D9C23NOPAD/UNCONNECTED_D10B23NOPAD/UNCONNECTED_D11A19NOPAD/UNCONNECTED_D12A20NOPAD/UNCONNECTED_D13A23NOPAD/UNCONNECTED_D14A24NOPAD/UNCONNECTED_D15C24NOPAD/UNCONNECTED_D16
D25NOPAD/UNCONNECTED_D17B26NOPAD/UNCONNECTED_D18A25NOPAD/UNCONNECTED_D19B27NOPAD/UNCONNECTED_D20A26NOPAD/UNCONNECTED_D21B25NOPAD/UNCONNECTED_D22C25NOPAD/UNCONNECTED_D23C29NOPAD/UNCONNECTED_D24B28NOPAD/UNCONNECTED_D25D26NOPAD/UNCONNECTED_D26
C27NOPAD/UNCONNECTED_D27A29NOPAD/UNCONNECTED_D28A28NOPAD/UNCONNECTED_D29C28NOPAD/UNCONNECTED_D30D27NOPAD/UNCONNECTED_D31B31NOPAD/UNCONNECTED_D32A31NOPAD/UNCONNECTED_D33C30NOPAD/UNCONNECTED_D34D29NOPAD/UNCONNECTED_D35D31NOPAD/UNCONNECTED_D36
D30NOPAD/UNCONNECTED_D37A30NOPAD/UNCONNECTED_D38B30NOPAD/UNCONNECTED_D39
xc5vsx50t-3ff1136(10 of 11)
23
23 23
23
2323 23
2323
23
23
23
23 23 23 23
23
23
23
23
23
23
23
23 23
23
23
23
2323
23
23
23
23
23
23 2323
23
23
23
23
23
22
22
22
22
22
22
22 22
22
22
22
22
2222
2222
2222
22
22 22 22
22
22
22
22
22 22
22 22
22 22
22
22
22 22
22
22
22 22
22
22
22
J8 B20_VCCO_20_D0E10 B20_VCCO_20_D1H11 B20_VCCO_20_D2
E9 B20_IO_L0P_20E8 B20_IO_L0N_20F9 B20_IO_L1P_20F8 B20_IO_L1N_20
F10 B20_IO_L2P_20G10 B20_IO_L2N_20G8 B20_IO_L3P_20
H8 B20_IO_L3N_20D11 B20_IO_L4P_20D10 B20_IO_L4N_VREF_20K11 B20_IO_L5P_20J11 B20_IO_L5N_20D12 B20_IO_L6P_20C12 B20_IO_L6N_20H10 B20_IO_L7P_20H9 B20_IO_L7N_20
A13 B20_IO_L8P_CC_20
B12 B20_IO_L8N_CC_20J10 B20_IO_L9P_CC_20
J9 B20_IO_L9N_CC_20K8 B20_IO_L10P_CC_20K9 B20_IO_L10N_CC_20
B13 B20_IO_L11P_CC_20C13 B20_IO_L11N_CC_20L10 B20_IO_L12P_VRN_20L11 B20_IO_L12N_VRP_20G11 B20_IO_L13P_20
G12 B20_IO_L13N_20M8 B20_IO_L14P_20L8 B20_IO_L14N_VREF_20
F11 B20_IO_L15P_20E11 B20_IO_L15N_20M10 B20_IO_L16P_20
L9 B20_IO_L16N_20E12 B20_IO_L17P_20E13 B20_IO_L17N_20N10 B20_IO_L18P_20
N9 B20_IO_L18N_20F13 B20_IO_L19P_20G13 B20_IO_L19N_20
AJ28B21_VCCO_21_D0AM29B21_VCCO_21_D1AL32B21_VCCO_21_D2
AA25B21_IO_L0P_21AA26B21_IO_L0N_21AB27B21_IO_L1P_21AC27B21_IO_L1N_21Y24B21_IO_L2P_21AA24B21_IO_L2N_21AB25B21_IO_L3P_21
AB26B21_IO_L3N_21AC28B21_IO_L4P_21AD27B21_IO_L4N_VREF_21AB28B21_IO_L5P_21AA28B21_IO_L5N_21AG28B21_IO_L6P_21AH28B21_IO_L6N_21AE28B21_IO_L7P_21AF28B21_IO_L7N_21AK26B21_IO_L8P_CC_21
AJ27B21_IO_L8N_CC_21AK29B21_IO_L9P_CC_21AJ29B21_IO_L9N_CC_21AK28B21_IO_L10P_CC_21AK27B21_IO_L10N_CC_21AH27B21_IO_L11P_CC_21AJ26B21_IO_L11N_CC_21AJ25B21_IO_L12P_VRN_21AH25B21_IO_L12N_VRP_21AF24B21_IO_L13P_21
AG25B21_IO_L13N_21AG27B21_IO_L14P_21AG26B21_IO_L14N_VREF_21AF25B21_IO_L15P_21AF26B21_IO_L15N_21AE27B21_IO_L16P_21AE26B21_IO_L16N_21AC25B21_IO_L17P_21AC24B21_IO_L17N_21AD26B21_IO_L18P_21
AD25B21_IO_L18N_21AD24B21_IO_L19P_21AE24B21_IO_L19N_21
xc5vsx50t-3ff1136(9 of 11)
21 21
21
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21 21
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21
21
2121
21
2121
21
21
21 2121
21 21
2121
2121
212121
21
21
21
21
2020
2020 20
2020
20
2020
20
20
20
20
2020
20
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2020
20 20
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20 20
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2020
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SDRAM Signals
SRAM Clocks
ADS5463 Data/Clock
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
AsAP 2 Data Output
AsAP 2 Data Input
AsAP 2 Data Output
AsAP 2 Data Input
** INPUTS **** OUTPUTS **
SRAM Control
Xilinx Virtex-5 SX50T I/O
(requires Master Bank to contain at leastSlave Bank(s): 13, 17
QDR-II SRAM DCI Constraint: DCI_CASCADE = "21 13 17";
one I/O standard that uses VRN/VRP)
Master Bank: 21
Banks 13, 17, and 21 are in the same column in order.Pin AB27 will be used as dummy Input and fed to a register.
FPGA_ADC_DATA_N15FPGA_ADC_DATA_P15
FPGA_DDR2_SDRAM_CASN
FPGA_SRAM_K_CLK_P
FPGA_SRAM_K_CLK_NFPGA_SRAM_K_CLK_P
FPGA_SRAM_RDN
FPGA_SRAM_ADDR12FPGA_SRAM_ADDR4FPGA_SRAM_ADDR2
FPGA_SRAM_ADDR0
FPGA_SRAM_ADDR3
FPGA_SRAM_ADDR1
FPGA_BANK21_VRPFPGA_BANK21_VRN
FPGA_SRAM_ADDR8
FPGA_SRAM_ADDR13FPGA_SRAM_ADDR5
FPGA_SRAM_ADDR14FPGA_SRAM_ADDR9
FPGA_SRAM_ADDR6
FPGA_SRAM_ADDR7
FPGA_SRAM_ADDR15FPGA_SRAM_ADDR10
FPGA_SRAM_ADDR16
FPGA_SRAM_ADDR11
FPGA_SRAM_ADDR17
U69
FPGA_SRAM_DLL_OFFN24-D3,24-E5,28-C5,28-D128-D2
24-D3,24-E5,28-A2,28-E128-E2,29-C4,29-E124-C3,24-D3,24-E5,28-C728-E1,28-E2,29-C3,29-E1
NCNC
U69
FPGA_ADC_DATA_RDY_N
FPGA_ADC_DATA_RDY_PFPGA_ADC_DATA_N8
FPGA_ADC_DATA_P4FPGA_ADC_DATA_N4FPGA_ADC_DATA_P3
FPGA_ADC_DATA_N3FPGA_ADC_DATA_P2FPGA_ADC_DATA_N2FPGA_ADC_DATA_P1
FPGA_ADC_DATA_P0FPGA_ADC_DATA_N1
FPGA_ADC_DATA_N0FPGA_ADC_OVR_PFPGA_ADC_OVR_N
FPGA_ADC_DATA_P7
P1V8D_V5
FPGA_BANK21_VRNFPGA_BANK21_VRP
FPGA_BANK20_VRNFPGA_BANK20_VRP
R15
5
FPGA_DDR2_SDRAM_RASN
FPGA_DDR2_SDRAM_CASN
FPGA_DDR2_SDRAM_WEN
FPGA_DDR2_SDRAM_BA0
FPGA_SRAM_K_CLK_N
FPGA_SRAM_RDN
FPGA_SRAM_WRN
FPGA_SRAM_WDATA35
FPGA_SRAM_BWN3
24-C3,24-D5,27-A4,27-D127-D324-C3,24-D5,27-A4,27-D127-D3
P2V5D_V5
FPGA_ASAP2_VLD_INFPGA_ASAP2_CLK_IN
FPGA_ASAP2_DATA_IN[15:0]
FPGA_ASAP2_REQ_OUT24-D1,24-E5,40-D4,40-E1
24-D1,24-E5,40-D3,40-E141-C4,41-D1,41-D224-D1,24-E5,40-C3,40-E141-C2,41-D1,41-D2
24-D1,24-E5,40-D3,40-E141-C2,41-C4,41-E1,41-E2
24-D1,24-E1,40-D3,40-E5
FPGA_ASAP2_VLD_OUTFPGA_ASAP2_CLK_OUT
24-C1,24-D1,24-E1,40-D440-E5
FPGA_ASAP2_DATA_OUT[15:0]
NCNC
P2V5D_V5P1V8D_V5
P0V9D_MEM_VREF
P0V9D_MEM_VREF
U69
NC
NCNCNC
NCNCNC
NCNCNC
NCNC
NC
NC
NCNC
NCNCNC
NCNCNC
NC
NC
NCNC
NCNCNC
NCNCNC
NC
NC
NCNCNC
NCNCNC
NCNCNC
NCNC
NC
NCNCNC
NCNCNC
NCNC
NC
NC
NCNCNC
NCNCNC
NCNC
NC
NC
NCNC
NCNCNC
NCNCNC
NCNCNC
NC
R83
R82
P2V5D_V5P3V3D_V5
24-D1,24-E1,40-D4,40-E524-D1,24-E1,40-C4,40-E5
FPGA_ASAP2_REQ_IN
43
4-20-2009_13:35
24 001
XILINX VIRTEX-5 SX50T I/O
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
NC
FPGA_ADC_DATA_P8FPGA_ADC_DATA_N9FPGA_ADC_DATA_P9FPGA_ADC_DATA_N10FPGA_ADC_DATA_P10FPGA_ADC_DATA_N11FPGA_ADC_DATA_P11FPGA_ADC_DATA_N12
FPGA_ADC_DATA_P12FPGA_ADC_DATA_N13FPGA_ADC_DATA_P13FPGA_ADC_DATA_N14FPGA_ADC_DATA_P14
NC
24-C3,24-D3,24-E1,33-B533-C5
24-C3,24-E1,33-C524-C3,24-E1,33-C524-D3,24-E1,33-C524-D3,24-E1,33-C5
24-C3,24-D3,24-E1,33-B533-C5
FPGA_ADC_DATA_RDY_N
FPGA_ADC_DATA_N[15:0]
FPGA_ADC_DATA_P[15:0]
FPGA_ADC_OVR_NFPGA_ADC_OVR_P
FPGA_ADC_DATA_RDY_P
24-C3,24-E5,28-B4,28-E128-E2,29-C4,29-E1
24-D3,24-D5,28-A2,28-D128-D2,29-C3,29-E1
24-D3,24-D5,28-A2,28-D128-D2,29-C3,29-E1
24-C3,24-E5,28-B2,28-E128-E2,29-C4,29-E1
FPGA_SRAM_ADDR[17:0]
24-D3,24-E5,28-B2,28-E128-E2,29-C4,29-E1
FPGA_DDR2_SDRAM_ODT[1:0]
FPGA_DDR2_SDRAM_SN[1:0]
24-C3,24-D5,27-A5,27-D327-E124-C3,24-D5,27-A5,27-D327-E124-C3,24-D5,27-A5,27-D327-E124-C3,24-D5,27-A4,27-C227-E1
FPGA_DDR2_SDRAM_CKE[1:0]
24-C3,24-D5,27-B4,27-D327-E1
R15
6
P2V5D_V5
FPGA_ADC_DATA_P5FPGA_ADC_DATA_N5
FPGA_ADC_DATA_N7FPGA_ADC_DATA_P6FPGA_ADC_DATA_N6
FPGA_DDR2_SDRAM_CKE0FPGA_DDR2_SDRAM_CKE1FPGA_DDR2_SDRAM_ODT0
FPGA_DDR2_SDRAM_ODT1FPGA_DDR2_SDRAM_SN0FPGA_DDR2_SDRAM_SN1FPGA_DDR2_SDRAM_WEN
FPGA_DDR2_SDRAM_RASNFPGA_DDR2_SDRAM_BA0
FPGA_SRAM_WRN
FPGA_SRAM_BWN3FPGA_SRAM_WDATA35FPGA_SRAM_DLL_OFFN
NC
FPGA_ASAP2_DATA_OUT0FPGA_ASAP2_DATA_OUT1FPGA_ASAP2_DATA_OUT2
FPGA_ASAP2_DATA_OUT3FPGA_ASAP2_DATA_OUT4FPGA_ASAP2_DATA_OUT5FPGA_ASAP2_DATA_OUT6FPGA_ASAP2_DATA_OUT7FPGA_ASAP2_DATA_OUT8FPGA_ASAP2_DATA_OUT9FPGA_ASAP2_DATA_OUT10FPGA_ASAP2_DATA_OUT11FPGA_ASAP2_DATA_OUT12
FPGA_ASAP2_DATA_OUT13FPGA_BANK20_VRPFPGA_BANK20_VRNFPGA_ASAP2_DATA_OUT14FPGA_ASAP2_DATA_OUT15FPGA_ASAP2_VLD_OUTFPGA_ASAP2_CLK_OUTFPGA_ASAP2_REQ_OUTFPGA_ASAP2_VLD_INFPGA_ASAP2_REQ_IN
FPGA_ASAP2_CLK_INFPGA_ASAP2_DATA_IN0FPGA_ASAP2_DATA_IN1FPGA_ASAP2_DATA_IN2FPGA_ASAP2_DATA_IN3FPGA_ASAP2_DATA_IN4FPGA_ASAP2_DATA_IN5FPGA_ASAP2_DATA_IN6FPGA_ASAP2_DATA_IN7FPGA_ASAP2_DATA_IN8
FPGA_ASAP2_DATA_IN9FPGA_ASAP2_DATA_IN10FPGA_ASAP2_DATA_IN11FPGA_ASAP2_DATA_IN12FPGA_ASAP2_DATA_IN13FPGA_ASAP2_DATA_IN14FPGA_ASAP2_DATA_IN15
0.0
1
0.0
1
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
0.0
1
0.0
1
0.0
1
0.0
1
M2 MGTTXP0_112_D0N2 MGTTXN0_112_D0N1 MGTRXP0_112_D0P1 MGTRXN0_112_D0R1 MGTRXN1_112_D0P3 MGTREFCLKN_112_D0T1 MGTRXP1_112_D0P4 MGTREFCLKP_112_D0T2 MGTTXN1_112_D0U2 MGTTXP1_112_D0
V4 MGTRREF_112_D0V2 MGTTXP0_114_D0W2 MGTTXN0_114_D0W1 MGTRXP0_114_D0Y1 MGTRXN0_114_D0
AA1 MGTRXN1_114_D0Y3 MGTREFCLKN_114_D0
AB1 MGTRXP1_114_D0Y4 MGTREFCLKP_114_D0
AB2 MGTTXN1_114_D0
AC2 MGTTXP1_114_D0F2 MGTTXP0_116_D0G2 MGTTXN0_116_D0G1 MGTRXP0_116_D0H1 MGTRXN0_116_D0J1 MGTRXN1_116_D0H3 MGTREFCLKN_116_D0K1 MGTRXP1_116_D0H4 MGTREFCLKP_116_D0K2 MGTTXN1_116_D0
L2 MGTTXP1_116_D0AD2 MGTTXP0_118_D0AE2 MGTTXN0_118_D0AE1 MGTRXP0_118_D0AF1 MGTRXN0_118_D0AG1 MGTRXN1_118_D0AF3 MGTREFCLKN_118_D0AH1 MGTRXP1_118_D0AF4 MGTREFCLKP_118_D0AH2 MGTTXN1_118_D0
AJ2 MGTTXP1_118_D0B4 MGTTXP0_120_D0B3 MGTTXN0_120_D0A3 MGTRXP0_120_D0A2 MGTRXN0_120_D0C1 MGTRXN1_120_D0D4 MGTREFCLKN_120_D0D1 MGTRXP1_120_D0E4 MGTREFCLKP_120_D0D2 MGTTXN1_120_D0
E2 MGTTXP1_120_D0AK2 MGTTXP0_122_D0AL2 MGTTXN0_122_D0AL1 MGTRXP0_122_D0AM1 MGTRXN0_122_D0AP2 MGTRXN1_122_D0AL4 MGTREFCLKN_122_D0AP3 MGTRXP1_122_D0AL5 MGTREFCLKP_122_D0AN3 MGTTXN1_122_D0AN4 MGTTXP1_122_D0
B10 NOPAD/UNCONNECTED_D0C10 NOPAD/UNCONNECTED_D1B9 NOPAD/UNCONNECTED_D2A9 NOPAD/UNCONNECTED_D3C9 NOPAD/UNCONNECTED_D4A8 NOPAD/UNCONNECTED_D5C6 NOPAD/UNCONNECTED_D6A7 NOPAD/UNCONNECTED_D7C8 NOPAD/UNCONNECTED_D8
A6 NOPAD/UNCONNECTED_D9D8 NOPAD/UNCONNECTED_D10B6 NOPAD/UNCONNECTED_D11C5 NOPAD/UNCONNECTED_D12B5 NOPAD/UNCONNECTED_D13
AN5 NOPAD/UNCONNECTED_D14AM10 NOPAD/UNCONNECTED_D15
AN6 NOPAD/UNCONNECTED_D16AP6 NOPAD/UNCONNECTED_D17AM6 NOPAD/UNCONNECTED_D18
AP7 NOPAD/UNCONNECTED_D19AM9 NOPAD/UNCONNECTED_D20AP8 NOPAD/UNCONNECTED_D21AM7 NOPAD/UNCONNECTED_D22AP9 NOPAD/UNCONNECTED_D23AL7 NOPAD/UNCONNECTED_D24AN9 NOPAD/UNCONNECTED_D25AM5 NOPAD/UNCONNECTED_D26
AN10 NOPAD/UNCONNECTED_D27C7 NOPAD/UNCONNECTED_D28
D7 NOPAD/UNCONNECTED_D29AL8 NOPAD/UNCONNECTED_D30AM8 NOPAD/UNCONNECTED_D31
M3MGTAVTTTX_112_D0N3MGTAVTTRX_112_D0T3MGTAVCCPLL_112_D0U3MGTAVTTTX_112_D1V5MGTAVTTRXC_D0AC3MGTAVTTTX_114_D0W3MGTAVTTRX_114_D0AB3MGTAVCCPLL_114_D0V3MGTAVTTTX_114_D1F3MGTAVTTTX_116_D0
G3MGTAVTTRX_116_D0K3MGTAVCCPLL_116_D0L3MGTAVTTTX_116_D1AD3MGTAVTTTX_118_D0AE3MGTAVTTRX_118_D0AH3MGTAVCCPLL_118_D0AJ3MGTAVTTTX_118_D1C4MGTAVTTTX_120_D0C3MGTAVTTRX_120_D0D3MGTAVCCPLL_120_D0
E3MGTAVTTTX_120_D1AK3MGTAVTTTX_122_D0AL3MGTAVTTRX_122_D0AM4MGTAVCCPLL_122_D0AM3MGTAVTTTX_122_D1R3MGTAVCC_112_D0R4MGTAVCC_112_D1AA3MGTAVCC_114_D0AA4MGTAVCC_114_D1J3MGTAVCC_116_D0
J4MGTAVCC_116_D1AG3MGTAVCC_118_D0AG4MGTAVCC_118_D1D5MGTAVCC_120_D0F4MGTAVCC_120_D1AJ4MGTAVCC_122_D0AK5MGTAVCC_122_D1
U5 NOPAD/UNCONNECTED_D32
xc5vsx50t-3ff1136(2 of 11)
MGT MGT
MGTMGT MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGTMGT
MGTMGTMGT
MGT
MGTMGT MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT MGT
MGTMGT MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGTMGT
MGT MGT
MGTMGT MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGTMGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGTMGT
MGT
MGT
MGTMGT
MGT MGT
MGTMGT MGT
MGT MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT MGT
MGT MGT
MGT MGT
MGT MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
MGT
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
Xilinx Virtex-5 SX50T MGT I/O and Power Inputs
U69
R487NC
NC
NCNC
NCNC
R488
P1V0D_V5
NCNC
NC
NC
NCNCNC
NC
NCNCNCNCNCNCNCNC
NCNCNCNCNCNCNCNCNC
NCNCNCNCNC
NC
NC
NCNCNCNC
NC
NC
NC
NC
NC
NC
NC
NC
NCNC
NC
NC
NC
NC
NCNCNC
NCNC
R489
R490
43
3-27-2009_12:24
25 001
XILINX VIRTEX-5 SX50T MGT I/O AND POWER INPUTS
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
NC
NC
NC
NCNCNC
NC
NCNC
NC
R145
R146
330U
2
330U
2
0.22U 2
0.22
U
2
0.22U 2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.22
U
2
0.22
U
2
0.22
U
2
0.22
U
2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
42-O
HM
12
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.22U 2
0.22U 2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.22U 2
0.1UFA B
G1 G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.22
U
2
0.22
U
2
0.22
U
2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.22
U
2
0.22
U
2
0.22
U
2
0.22
U
2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.22
U
2
0.22
U
2
0.22
U
2
0.1UF AB
G1G2
0.1UF AB
G1G2
42-O
HM
12
42-O
HM
12
42-OHM
1 2
0.22U 2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UF AB
G1G2
0.1UF AB
G1G2
0.22U 2
0.22
U
2
0.22U 2
47U
247U
247U
2 33U
2
47U
2
47U
2
47U
2
47U
2
330U
2
330U
2
U4
FL
OA
T_D
0
B1
AN
1
AF
2
AE
15H
16M
16P
16T
16V
16Y
16A
B16
AD
16A
H16
AG
2
A17
L17
N17
R17
AA
17A
C17
AF
17A
L17
D18 J18
AM
2
M18
P18
Y18
AB
18A
D18
AP
18G
19N
19R
19U
19
AN
2
W19
AA
19A
C19
AG
19K
20M
20P
20T
20V
20Y
20G4
AB
20A
E20
AK
20C
21H
21N
21R
21U
21W
21A
A21K4
AC
21A
N21
A22
F22
L22
P22
T22
V22
Y22
AB
22M4
AF
22 J23
R23
U23
W23
AA
23A
J23
AP
23B
24M
24N4
AB
24A
G24
AM
24E
25K
25R
25Y
25A
E25
H26
N26T
4
V26
AC
26A
H26
A27
L27
AA
27A
F27
AL
27D
28P
28W4
AD
28A
P28
B29
G29
U29
AG
29K
30Y
30A
K30
C31B2
AB
4
N31
AC
31A
N31
A32
F32
T32
AF
32D
33 J33
W33
AE
4
AJ3
3A
P33
B34
G34
M34
U34
AB
34A
G34
AM
34
AH
4A
K4
E5
K5
R5
T5
W5
Y5
C2
AE
5A
J5 D6
H6
U6
V6
AH
6A
L6
B7
F7
H2
L7
AA
7A
N7
B8
P8
AD
8A
N8
D9
G9
U9J2
AG
9A
L9
K10
R10
Y10
AE
10A
K10
A11
B11
C11P2
N11
U11
AA
11A
C11
AN
11A
P11
A12
F12
M12
P12R2
T12
V12
Y12
AB
12A
D12
AF
12 J13
L13
N13
R13Y2
U13
W13
AA
13A
C13
AJ1
3A
P13
B14
M14
P14
T14
AA
2
V14
Y14
AB
14A
M14
E15
K15
R15
U15
W15
AA
15
M11
P11
Y23
U24
V11
AB
11L
12A
C12
M21
P23
T23
V23
N12
R12
AB
13A
D13
R14
U14
W14
AA
14T
15V
15
Y15
N16
U12
R16
U16
W16
AA
16A
C16
M17
P17
Y17
AB
17A
D17
W12
N18
R18
AA
18A
C18
M19
P19
T19
V19
Y19
AB
19
AA
12
N20
R20
U20
W20
AA
20A
C20
P21
T21
V21
Y21
M13
AB
21R
22U
22W
22
P13
T13
V13
Y13
VC
CA
UX
P
P
PP
PP
P
P
P
P
PP
PP
P
P
PP
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
PP
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
PPP
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
GN
D
VC
CIN
T
(1 of 11)
XILINX FPGA
xc5vsx50t-3ff1136
(1 o
f 11
)
X2Y
X2Y
X2Y
X2Y
+1.8
V
+2.5
V+2
.5V
Ban
k 11
+1.8
VB
ank
13+1
.8V+1
.8V
+2.5V
+3.3V
+3.3V
No
Co
nn
ect
Ban
kN
o C
on
nec
t B
ank
X2Y
X2Y
X2Y
TA
NT
X2Y
X2Y
X2Y
+3.3VBank 3
+3.3V
+2.5V
+3.3V
+2.5V
X2Y
TA
NT
TA
NT
X2Y
VC
CA
UX
X2Y
X2Y
X2Y
X2Y
X2Y
TA
NT
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
TA
NT
X2Y
X2Y
X2Y
SX50T
+2.5V
Bank 12
+1.8V
+1.8V
(XC5VSX50T-3FF1136)
+2.5V
Bank 1
Bank 18
Bank 20 Bank 19
Bank 17
Bank 15
Bank 21Bank 22 Bank 2
Bank 4
+3.3V
Bank 0
Virtex 5Xilinx FPGA
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
TA
NT
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
TA
NT
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
Tantalum/O402 Via Placement
Xilinx FPGAVirtex 5
Bank 0
+3.3V
Bank 4
Bank 2Bank 22 Bank 21
Bank 15
Bank 17
Bank 19Bank 20
Bank 18
Bank 1
+2.5V
(XC5VSX50T-3FF1136)
+1.8V
+1.8V
Bank 12
+2.5V
SX50T
Rated @ 6A
X2Y
X2Y
X2Y
TA
NT
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
TA
NT
X2Y
X2Y
+1.8V
+1V
0402PWR X2Y / TANT
X2Y
X2Y
X2Y
VC
CA
UX
Rated @ 6ARated @ 6A
Rated @ 6A
X2YT
AN
T
TA
NT
X2Y
+2.5V
+3.3V
+2.5V
+3.3V
Bank 3 +3.3V
X2Y
X2Y
X2Y
TA
NT
X2Y
X2Y
X2Y
No
Co
nn
ect
Ban
kN
o C
on
nec
t B
ank
+3.3V
+3.3V
No Connect Bank 6 +2.5V
No Connect Bank 25
+1.8
V
+1.8
VB
ank
13+1
.8V
Ban
k 11
+2.5
V+2
.5V
+1.8
V
X2Y
No Connect Bank 25
+3.3V
+2.5V
X2Y Capacitor Via Placement
No Connect Bank 23
No Connect Bank 5
No Connect Bank 6
(bottom side)Capacitor Placement
No Connect Bank 23
No Connect Bank 5
(top side)Capacitor Placement
Capacitor Legend:
Xilinx Virtex-5 SX50T Core, I/O, and Auxiliary Power InputsUC Davis Confidential Copyright © 2008 VLSI Computation Lab
U69
C15
6
C15
7
C375
C377
C371
C370
C62
1
C19
6
C36
4
C36
5
C308
C29
1
C295
C702
C723
C743
C734
P1V8D
C733
C293
L30
L29
P1V0D_V5
P3V3D
P1V0D
P2V5D
P2V5D_V5 L28
C721
C720
C28
3
C28
2
C28
1
C719
C716
C713
C28
0
C27
9
C27
8
C27
7
C712C711C710C709 C708
C707C706 C705 C704 C703
C700C699C698 C696
C695C694 C693C690
C729
C728 C727
C28
6
C28
5
C28
4
C726
C725 C724
C722
C732
C292
C731 C730
P3V3D_V5
C296
C294
C745
C744 C742 C741
C740C739 C738
C737C736C735
L31
P1V8D_V5
C749 C748 C747C746
C753 C752
C30
7
C30
6
C30
5
C30
4
C751C750
C754
C761 C760 C759C758 C757C756
C755
C765C764 C763 C762
43
3-27-2009_12:24
26 001
XILINX VIRTEX-5 SX50T CORE, I/O, AND AUXILIARY POWER INPUTS
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
C470C469
C472 C471
C473
C474
C210
C211
C213C212
C215 C214
C319 C309
C399 C320
C290
C29
7
C298
NC
C29
9
C27
6
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.90.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
4.75
K1
56-OHM
1 2
100U 2
100U 2
100U 2
100U
2
76 DQ3177 VSS_D078 VSS_D179 CKE080 CKE181 VDD_D082 VDD_D183 NC_D084 NC_D185 NC/BA2
86 NC_D287 VDD_D288 VDD_D389 A1290 A1191 A992 A793 A894 A695 VDD_D4
96 VDD_D597 A598 A499 A3
100 A2
SODIMM ConnectorMT16HTF12864H
(4 of 9)
101 A1102 A0103 VDD_D0104 VDD_D1105 A10/AP106 BA1107 BA0108 RAS#109 WE#110 S0#
111 VDD_D2112 VDD_D3113 CAS#114 ODT0115 S1#116 NC/A13117 VDD_D4118 VDD_D5119 ODT1120 NC_D0
121 VSS_D0122 VSS_D1123 DQ32124 DQ36125 DQ33
SODIMM ConnectorMT16HTF12864H
(5 of 9)
51 DQS252 DM253 VSS_D054 VSS_D155 DQ1856 DQ2257 DQ1958 DQ2359 VSS_D260 VSS_D3
61 DQ2462 DQ2863 DQ2564 DQ2965 VSS_D466 VSS_D567 DM368 DQS3#69 NC_D070 DQS3
71 VSS_D672 VSS_D773 DQ2674 DQ3075 DQ27
SODIMM ConnectorMT16HTF12864H
(3 of 9)
176 DQ55177 VSS_D0178 VSS_D1179 DQ56180 DQ60181 DQ57182 DQ61183 VSS_D2184 VSS_D3185 DM7
186 DQS7#187 VSS_D4188 DQS7189 DQ58190 VSS_D5191 DQ59192 DQ62193 VSS_D6194 DQ63195 SDA
196 VSS_D7197 SCL198 SA0199 VDDSPD200 SA1
SODIMM ConnectorMT16HTF12864H
(8 of 9)
10K1
10K1
100U 2
56-OHM
1 2
56-OHM
1 2
56-OHM
1 2
126 DQ37127 VSS_D0128 VSS_D1129 DQS4#130 DM4131 DQS4132 VSS_D2133 VSS_D3134 DQ38135 DQ34
136 DQ39137 DQ35138 VSS_D4139 VSS_D5140 DQ44141 DQ40142 DQ45143 DQ41144 VSS_D6145 VSS_D7
146 DQS5#147 DM5148 DQS5149 VSS_D8150 VSS_D9
SODIMM ConnectorMT16HTF12864H
(6 of 9)
4.75
K1
26 DM127 VSS_D028 VSS_D129 DQS1#30 CK031 DQS132 CK0#33 VSS_D234 VSS_D335 DQ10
36 DQ1437 DQ1138 DQ1539 VSS_D440 VSS_D541 VSS_D642 VSS_D743 DQ1644 DQ2045 DQ17
46 DQ2147 VSS_D848 VSS_D949 DQS2#50 NC_D0
SODIMM ConnectorMT16HTF12864H
(2 of 9)
0.1UFA B
G1 G2
100U
2
151 DQ42152 DQ46153 DQ43154 DQ47155 VSS_D0156 VSS_D1157 DQ48158 DQ52159 DQ49160 DQ53
161 VSS_D2162 VSS_D3163 NC_D0164 CK1165 VSS_D4166 CK1#167 DQS6#168 VSS_D5169 DQS6170 DM6
171 VSS_D6172 VSS_D7173 DQ50174 DQ54175 DQ51
SODIMM ConnectorMT16HTF12864H
(7 of 9)
1 VREF2 VSS_D03 VSS_D14 DQ45 DQ06 DQ57 DQ18 VSS_D29 VSS_D3
10 DM0
11 DQS0#12 VSS_D413 DQS014 DQ615 VSS_D516 DQ717 DQ218 VSS_D619 DQ320 DQ12
21 VSS_D722 DQ1323 DQ824 VSS_D825 DQ9
SODIMM ConnectorMT16HTF12864H
(1 of 9)
PAD1PAD2
PIN1PIN2
SODIMM ConnectorMT16HTF12864H
(9 of 9)
49.9
49.9
49.9
49.9
49.9
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
** INPUTS **
SDRAM Signals
Pull-up required due to open drain interface
Fo
r se
lf r
efre
sh
DDR2 Termination/Power Inputs
C D DDR2 Terminations
B
DDR2 SDRAM SODIMM - MT16HTF25664H – 2GB256 Meg x 64-bits
Provides between 1.024 GS and 1.280 GS storage of sampled data.
Place DDR2 SDRAM termination Decoupling near terminated signals.
near SODIMM. One 0.1uF capacitor per 2 VDD pins.Place DDR2 SDRAM termination Decoupling
DDR2 Termination Decoupling
R27
R28
R29
R35
R34
FPGA_DDR2_SDRAM_DQ16
203204
201202
U42
U42 U42
P0V9D_SDRAM_VTT
C85
5
C331
FPGA_DDR2_SDRAM_A0
U42
R21
8
U42
P3V3D_SDRAM P3V3D_SDRAM
P3V3D_SDRAM
24-C3,24-D5,27-A5,27-D327-E1
24-C3,24-D5,27-A5,27-D327-E1
P0V9D_SDRAM_VTT
P0V9D_SDRAM_VREF
24-C3,24-D5,27-A4,27-C227-E1
23-B1,23-B4,23-C1,23-D323-E3,23-E5,27-C1,27-C327-C4,27-D1,27-D2,27-D4
27-E1,27-E223-B1,23-B4,23-C1,23-D323-E3,23-E5,27-C1,27-C327-C4,27-D1,27-D2,27-D4
27-E1
15-B5,15-C1,27-D1
P1V8D
P0V9D_VTT
P0V9D_VREF
L114
L113
L112
P1V8D_SDRAM
P0V9D_SDRAM_VTT
C854
FPGA_DDR2_SDRAM_ODT0
FPGA_DDR2_SDRAM_ODT1FPGA_DDR2_SDRAM_ODT[1:0]
FPGA_DDR2_SDRAM_A15
FPGA_DDR2_SDRAM_A3
FPGA_DDR2_SDRAM_A4
FPGA_DDR2_SDRAM_A5
FPGA_DDR2_SDRAM_A6
FPGA_DDR2_SDRAM_A7
FPGA_DDR2_SDRAM_A8
FPGA_DDR2_SDRAM_A9
FPGA_DDR2_SDRAM_A10
FPGA_DDR2_SDRAM_A11
FPGA_DDR2_SDRAM_A12
FPGA_DDR2_SDRAM_A13
FPGA_DDR2_SDRAM_A14
FPGA_DDR2_SDRAM_A[15:0]
FPGA_DDR2_SDRAM_A0
FPGA_DDR2_SDRAM_A1
FPGA_DDR2_SDRAM_A2
FPGA_DDR2_SDRAM_CK_N0
FPGA_DDR2_SDRAM_CK_P0
FPGA_DDR2_SDRAM_CK_N1
FPGA_DDR2_SDRAM_CK_P1
FPGA_DDR2_SDRAM_DQ[63:0]
P0V9D_SDRAM_VTT
FPGA_DDR2_SDRAM_BA2FPGA_DDR2_SDRAM_BA[2:0]
FPGA_DDR2_SDRAM_BA0
FPGA_DDR2_SDRAM_BA1
FPGA_DDR2_SDRAM_SN1FPGA_DDR2_SDRAM_SN[1:0]
FPGA_DDR2_SDRAM_SN0
FPGA_DDR2_SDRAM_CKE1
FPGA_DDR2_SDRAM_CKE0
FPGA_DDR2_SDRAM_CKE[1:0]
FPGA_DDR2_SDRAM_CASN
FPGA_DDR2_SDRAM_WEN
FPGA_DDR2_SDRAM_RASN
FPGA_DDR2_SDRAM_SCL
P1V8D_SDRAM
FPGA_DDR2_SDRAM_SDA
FPGA_DDR2_SDRAM_CKE1FPGA_DDR2_SDRAM_CKE0
R136
R135
P1V8D_SDRAM
NC
NC
NC
FPGA_DDR2_SDRAM_DQSN_NC0
FPGA_DDR2_SDRAM_DQS0
FPGA_DDR2_SDRAM_DM0
FPGA_DDR2_SDRAM_DM1
FPGA_DDR2_SDRAM_DQSN_NC1
FPGA_DDR2_SDRAM_DQS1
FPGA_DDR2_SDRAM_DQSN_NC2
FPGA_DDR2_SDRAM_DM2FPGA_DDR2_SDRAM_DQS2
FPGA_DDR2_SDRAM_DM3FPGA_DDR2_SDRAM_DQSN_NC3
FPGA_DDR2_SDRAM_DQS3
FPGA_DDR2_SDRAM_DQSN_NC4FPGA_DDR2_SDRAM_DM4FPGA_DDR2_SDRAM_DQS4
FPGA_DDR2_SDRAM_DM5FPGA_DDR2_SDRAM_DQSN_NC5
FPGA_DDR2_SDRAM_DQS5
FPGA_DDR2_SDRAM_DM7
FPGA_DDR2_SDRAM_DQSN_NC7
FPGA_DDR2_SDRAM_DQS7
FPGA_DDR2_SDRAM_WENFPGA_DDR2_SDRAM_RASN
FPGA_DDR2_SDRAM_CASN
FPGA_DDR2_SDRAM_ODT1
FPGA_DDR2_SDRAM_ODT0FPGA_DDR2_SDRAM_SN1
FPGA_DDR2_SDRAM_SN0
FPGA_DDR2_SDRAM_DQ4
FPGA_DDR2_SDRAM_BA2
FPGA_DDR2_SDRAM_BA1
FPGA_DDR2_SDRAM_A[15:0]
FPGA_DDR2_SDRAM_A15
FPGA_DDR2_SDRAM_A14
FPGA_DDR2_SDRAM_A13
FPGA_DDR2_SDRAM_A10
FPGA_DDR2_SDRAM_A1
FPGA_DDR2_SDRAM_A11FPGA_DDR2_SDRAM_A12
FPGA_DDR2_SDRAM_A9
FPGA_DDR2_SDRAM_A8FPGA_DDR2_SDRAM_A7
FPGA_DDR2_SDRAM_A6
FPGA_DDR2_SDRAM_A5FPGA_DDR2_SDRAM_A4FPGA_DDR2_SDRAM_A3FPGA_DDR2_SDRAM_A2
FPGA_DDR2_SDRAM_DQ1
FPGA_DDR2_SDRAM_DQ63
FPGA_DDR2_SDRAM_DQ62FPGA_DDR2_SDRAM_DQ59
FPGA_DDR2_SDRAM_DQ58
FPGA_DDR2_SDRAM_DQ61FPGA_DDR2_SDRAM_DQ57FPGA_DDR2_SDRAM_DQ60
FPGA_DDR2_SDRAM_DQ55
FPGA_DDR2_SDRAM_DQ36
FPGA_DDR2_SDRAM_DQ37
FPGA_DDR2_SDRAM_DQ38FPGA_DDR2_SDRAM_DQ34
FPGA_DDR2_SDRAM_DQ39FPGA_DDR2_SDRAM_DQ35
FPGA_DDR2_SDRAM_DQ44FPGA_DDR2_SDRAM_DQ40FPGA_DDR2_SDRAM_DQ45FPGA_DDR2_SDRAM_DQ41
FPGA_DDR2_SDRAM_DQ21
FPGA_DDR2_SDRAM_DQ33
FPGA_DDR2_SDRAM_DQ32
FPGA_DDR2_SDRAM_DQ31
FPGA_DDR2_SDRAM_DQ30FPGA_DDR2_SDRAM_DQ27
FPGA_DDR2_SDRAM_DQ26
FPGA_DDR2_SDRAM_DQ28
FPGA_DDR2_SDRAM_DQ29FPGA_DDR2_SDRAM_DQ25
FPGA_DDR2_SDRAM_DQ24
FPGA_DDR2_SDRAM_DQ23
FPGA_DDR2_SDRAM_DQ22FPGA_DDR2_SDRAM_DQ18
FPGA_DDR2_SDRAM_DQ19
U42
U42 U42
U42
FPGA_DDR2_SDRAM_DQ9
FPGA_DDR2_SDRAM_DQ8FPGA_DDR2_SDRAM_DQ13
FPGA_DDR2_SDRAM_DQ12FPGA_DDR2_SDRAM_DQ3
FPGA_DDR2_SDRAM_DQ2FPGA_DDR2_SDRAM_DQ7
FPGA_DDR2_SDRAM_DQ6
FPGA_DDR2_SDRAM_DQ5FPGA_DDR2_SDRAM_DQ0
FPGA_DDR2_SDRAM_DQ17FPGA_DDR2_SDRAM_DQ20
FPGA_DDR2_SDRAM_DQ15FPGA_DDR2_SDRAM_DQ11FPGA_DDR2_SDRAM_DQ14
FPGA_DDR2_SDRAM_DQ10
FPGA_DDR2_SDRAM_DQ56
FPGA_DDR2_SDRAM_BA0
NC
P0V9D_SDRAM_VREF
FPGA_DDR2_SDRAM_DQ42FPGA_DDR2_SDRAM_DQ46FPGA_DDR2_SDRAM_DQ43FPGA_DDR2_SDRAM_DQ47
FPGA_DDR2_SDRAM_DQ48
FPGA_DDR2_SDRAM_DQ49FPGA_DDR2_SDRAM_DQ53
FPGA_DDR2_SDRAM_DQ52
FPGA_DDR2_SDRAM_DQ50
FPGA_DDR2_SDRAM_DQ51FPGA_DDR2_SDRAM_DQ54
FPGA_DDR2_SDRAM_DQS6
FPGA_DDR2_SDRAM_DQSN_NC6
FPGA_DDR2_SDRAM_DM6
NC
C85
6
C857
C858
15-B5,15-C1,27-D1
23-B1,23-B4,23-E5,27-C127-D4,27-E1
23-B1,23-B4,23-E5,27-C127-D4,27-E1
23-B1,23-B4,23-C1,23-C423-D3,23-E3,23-E5,27-C127-C3,27-C4,27-D1,27-D2
27-D4,27-E1,27-E2
24-C3,24-D5,27-A4,27-D127-D3
24-C3,24-D5,27-A4,27-D127-D3
24-C3,24-D5,27-A5,27-D327-E1
23-D3,23-E5,24-C3,24-D527-B4,27-C2,27-D3,27-E1
23-B1,23-B4,23-D3,23-E527-A3,27-C2,27-D3,27-E1
27-E3
23-B1,23-B4,23-C1,23-C423-D3,23-E3,23-E5,27-C127-C2,27-C3,27-C4,27-D127-D2,27-D3,27-D4,27-E1
27-E4
C859
L115
P3V3D
FPGA_DDR2_SDRAM_CKE[1:0]
FPGA_DDR2_SDRAM_DQS[7:0]
FPGA_DDR2_SDRAM_DQSN_NC[7:0]
FPGA_DDR2_SDRAM_SDAFPGA_DDR2_SDRAM_SCL
FPGA_DDR2_SDRAM_CK_P[1:0]
FPGA_DDR2_SDRAM_CK_N[1:0]
FPGA_DDR2_SDRAM_DM[7:0]
FPGA_DDR2_SDRAM_SN[1:0]
FPGA_DDR2_SDRAM_ODT[1:0]
FPGA_DDR2_SDRAM_WEN
FPGA_DDR2_SDRAM_CASN
FPGA_DDR2_SDRAM_RASN
FPGA_DDR2_SDRAM_BA[2:0]
R21
9
43
4-20-2009_13:35
27 001
DDR2 SDRAM SODIMM - MT16HTF25664H – 2GB
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
C235 C234C233C232 C231 C315
C332C330 C329 C327C316R41
R44
R40
R39
R38
R37
R36
R47
R46
R45
R43
R42
R26
R25
R24
R23
R22
R21
R20
R30
R31
R33
R32
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
D
1
1 2 3 4 5 6 7 8
2 3 4 5 6 7 8
A
B
C
E
D
A
B
C
E
D
249
1
H1 B0_Doff_N
C6 B0_NC
R2 B0_TCKR11 B0_TDI
R1 B0_TDO
R10 B0_TMS
H11 B0_ZQ
A3B1_NC/SA_D18A10B1_NC/SA_D19A2B1_NC/SA_D20
A9B1_SA_D0B4B1_SA_D1
P7B1_SA_D10P8B1_SA_D11R3B1_SA_D12R4B1_SA_D13R5B1_SA_D14R7B1_SA_D15R8B1_SA_D16R9B1_SA_D17
B8B1_SA_D2C5B1_SA_D3C7B1_SA_D4N5B1_SA_D5N6B1_SA_D6N7B1_SA_D7P4B1_SA_D8P5B1_SA_D9
1
1 1
1 1
1 1 1
1 1 1 1
1 1 1 1 1 1
0 000
0 0 0
0
00
k7r323684c-ec25(2 of 3)
NL
1
10K
NL
1
1.91
K
1
1.91
K
1
1.91
K
10K
B7 B2_BW0_NA7 B2_BW1_NA5 B2_BW2_NB5 B2_BW3_N
P6 B2_CR6 B2_C_N
P10 B2_D0N11 B2_D1
M9 B2_D10L9 B2_D11J9 B2_D12
G10 B2_D13F9 B2_D14
D10 B2_D15C9 B2_D16B9 B2_D17B3 B2_D18C3 B2_D19
M11 B2_D2
D2 B2_D20F3 B2_D21G2 B2_D22J3 B2_D23L3 B2_D24M3 B2_D25N2 B2_D26C1 B2_D27D1 B2_D28E2 B2_D29
K10 B2_D3
G1 B2_D30J1 B2_D31K2 B2_D32M1 B2_D33N1 B2_D34P2 B2_D35
J11 B2_D4G11 B2_D5E10 B2_D6D11 B2_D7C11 B2_D8N10 B2_D9
B6 B2_KA6 B2_K_N
A4 B2_W_N
A11B3_CQA1B3_CQ_N
P11B3_Q0M10B3_Q1
N9B3_Q10L10B3_Q11K9B3_Q12G9B3_Q13F10B3_Q14E9B3_Q15D9B3_Q16B10B3_Q17B2B3_Q18D3B3_Q19
L11B3_Q2
E3B3_Q20F2B3_Q21G3B3_Q22K3B3_Q23L2B3_Q24N3B3_Q25P3B3_Q26B1B3_Q27C2B3_Q28E1B3_Q29
K11B3_Q3
F1B3_Q30J2B3_Q31K1B3_Q32L1B3_Q33M2B3_Q34P1B3_Q35
J10B3_Q4F11B3_Q5E11B3_Q6C10B3_Q7B11B3_Q8P9B3_Q9
A8B3_R_N
k7r323684c-ec25(3 of 3)
33
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
33
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
22
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
22
2
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
Adding 10Kohm Pull-Ups Disables C/CN clock at power up
All data, address, clocks must have equal length lines
Samsung K7R323684C-EC250** OUTPUTS **
** INPUTS **
SRAM Read Data
SRAM Read Clock
QDR II SRAM JTAG Interface
Use 0 Ohm Resistors in casewe use Cypress CY7C1415AV18,Renesas R1Q3A3636ABG, orNEC uPD44325364F5-E40-EQ2-A
SRAM Write Data
SRAM Control
A B QDR-II SRAM AddressAll data, address, clocks must have equal length lines
QDR-II SRAM Read/Write Data
QDR-II SRAM - Address, Data, Control
SRAM Clocks
FPGA_SRAM_C_CLK_N
U70
FPGA_SRAM_C_CLK_P
FPGA_SRAM_K_CLK_PFPGA_SRAM_K_CLK_N
R59
1
FPGA_SRAM_CQ_CLK_PFPGA_SRAM_CQ_CLK_N R
711
R71
2
R71
3
R16
2
R59
0
TP
277
R589
U70
FPGA_SRAM_DLL_OFFN
FPGA_SRAM_DLL_OFFN
24-C3,24-E5,28-B4,28-E229-C4,29-E1
TDO_SRAMTDI_SRAM
TCK_SRAMTMS_SRAM
TDO_SRAM
TP276
24-D3,24-D5,28-A2,28-D229-C3,29-E1
24-D3,24-D5,28-A2,28-D229-C3,29-E1
TP250
TP206
24-C3,24-D3,24-E5,28-C728-E2,29-C3,29-E1
23-B3,23-C3,23-D5,23-E524-D3,24-E5,28-A2,28-B2
28-E2,29-C4,29-E1
23-B3,23-C3,23-C5,23-D524-D3,24-E5,28-B2,28-C2
28-E2,29-C4,29-E1
24-C3,24-E5,28-B2,28-E229-C4,29-E1
FPGA_SRAM_RDATA[35:0]23-D4,23-E1,23-E4,28-B428-C4,28-E7
23-D4,23-E1,28-A4,28-E723-D4,23-E1,28-A4,28-E7
P1V8D_SRAM
P1V8D_SRAM
FPGA_SRAM_WDATA[35:0]
FPGA_SRAM_ADDR0
FPGA_SRAM_BWN[3:0]
FPGA_SRAM_RDN
FPGA_SRAM_WRN
FPGA_SRAM_RDATA0FPGA_SRAM_RDATA1
TMS_SRAMTDI_SRAMTCK_SRAM
R675
FPGA_SRAM_RDNFPGA_SRAM_WRN
FPGA_SRAM_WDATA0FPGA_SRAM_WDATA1FPGA_SRAM_WDATA2FPGA_SRAM_WDATA3FPGA_SRAM_WDATA4FPGA_SRAM_WDATA5FPGA_SRAM_WDATA6FPGA_SRAM_WDATA7FPGA_SRAM_WDATA8
FPGA_SRAM_WDATA24FPGA_SRAM_WDATA25
FPGA_SRAM_WDATA27FPGA_SRAM_WDATA26
FPGA_SRAM_WDATA29FPGA_SRAM_WDATA28
FPGA_SRAM_WDATA31FPGA_SRAM_WDATA30
FPGA_SRAM_WDATA32
FPGA_SRAM_WDATA34FPGA_SRAM_WDATA33
FPGA_SRAM_WDATA20FPGA_SRAM_WDATA19
FPGA_SRAM_WDATA22FPGA_SRAM_WDATA21
FPGA_SRAM_WDATA10
FPGA_SRAM_WDATA12FPGA_SRAM_WDATA11
FPGA_SRAM_WDATA14FPGA_SRAM_WDATA13
FPGA_SRAM_WDATA16FPGA_SRAM_WDATA15
FPGA_SRAM_WDATA18FPGA_SRAM_WDATA17
FPGA_SRAM_BWN0
FPGA_SRAM_BWN3FPGA_SRAM_BWN2FPGA_SRAM_BWN1
FPGA_SRAM_WDATA23
FPGA_SRAM_WDATA35
FPGA_SRAM_WDATA9
FPGA_SRAM_RDATA2FPGA_SRAM_RDATA3FPGA_SRAM_RDATA4FPGA_SRAM_RDATA5FPGA_SRAM_RDATA6FPGA_SRAM_RDATA7FPGA_SRAM_RDATA8
FPGA_SRAM_RDATA23
FPGA_SRAM_RDATA25FPGA_SRAM_RDATA24
FPGA_SRAM_RDATA27FPGA_SRAM_RDATA26
FPGA_SRAM_RDATA32FPGA_SRAM_RDATA31FPGA_SRAM_RDATA30FPGA_SRAM_RDATA29FPGA_SRAM_RDATA28
FPGA_SRAM_RDATA33
FPGA_SRAM_RDATA16
FPGA_SRAM_RDATA22
FPGA_SRAM_RDATA20FPGA_SRAM_RDATA19FPGA_SRAM_RDATA18FPGA_SRAM_RDATA17
FPGA_SRAM_RDATA15FPGA_SRAM_RDATA14FPGA_SRAM_RDATA13FPGA_SRAM_RDATA12FPGA_SRAM_RDATA11FPGA_SRAM_RDATA10FPGA_SRAM_RDATA9
FPGA_SRAM_RDATA21
FPGA_SRAM_RDATA34FPGA_SRAM_RDATA35
FPGA_SRAM_ADDR17FPGA_SRAM_ADDR16FPGA_SRAM_ADDR15FPGA_SRAM_ADDR14FPGA_SRAM_ADDR13FPGA_SRAM_ADDR12
FPGA_SRAM_ADDR10
FPGA_SRAM_ADDR9FPGA_SRAM_ADDR8FPGA_SRAM_ADDR7FPGA_SRAM_ADDR6FPGA_SRAM_ADDR5FPGA_SRAM_ADDR4FPGA_SRAM_ADDR3FPGA_SRAM_ADDR2FPGA_SRAM_ADDR1
FPGA_SRAM_ADDR11
FPGA_SRAM_CQ_CLK_NFPGA_SRAM_CQ_CLK_P
FPGA_SRAM_K_CLK_N
FPGA_SRAM_K_CLK_P
FPGA_SRAM_ADDR[17:0]
342
JEREMY W. WEBB
MEAS_MAIN_BOARD
QDR-II SRAM - ADDRESS, DATA, CONTROL
43
4-20-2009_13:35
28 001
TP251
24-D3,24-E5,28-C5,28-D2
1U
2
1U
2
1U
2
1U
2
1U
2
1U
2
1U
2
1U
2
0.022UFA B
G1 G2
0.022UFA B
G1 G2
0.022UFA B
G1 G2
0.022UFA B
G1 G2
0.022UFA B
G1 G2
0.022UFA B
G1 G2
0.022UFA B
G1 G2
0.022UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
100U 2
100U 2
100U 2
56-OHM
1 2
56-OHM
1 20.1U
3
5
6
7
8
2
1
4
ECJ-TVB1A104M
0.1U
3
5
6
7
8
2
1
4
ECJ-TVB1A104M
0.1U
3
5
6
7
8
2
1
4
ECJ-TVB1A104M
0.1U
3
5
6
7
8
2
1
4
ECJ-TVB1A104M
0.1U
3
5
6
7
8
2
1
4
ECJ-TVB1A104M
0.1U
3
5
6
7
8
2
1
4
ECJ-TVB1A104M
0.1U
3
5
6
7
8
2
1
4
ECJ-TVB1A104M
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.022UFA B
G1 G2
0.1UFA B
G1 G2
E4 VDDQ_D0E8 VDDQ_D1
J4 VDDQ_D10J8 VDDQ_D11K4 VDDQ_D12K8 VDDQ_D13L4 VDDQ_D14L8 VDDQ_D15
F4 VDDQ_D2F8 VDDQ_D3G4 VDDQ_D4G8 VDDQ_D5H3 VDDQ_D6H4 VDDQ_D7
H8 VDDQ_D8H9 VDDQ_D9
F5 VDD_D0F7 VDD_D1G5 VDD_D2G7 VDD_D3H5 VDD_D4H7 VDD_D5J5 VDD_D6J7 VDD_D7
K5 VDD_D8K7 VDD_D9
H2 VREF_D0H10 VREF_D1
C4VSS_D0C8VSS_D1
F6VSS_D10G6VSS_D11H6VSS_D12J6VSS_D13K6VSS_D14L5VSS_D15L6VSS_D16L7VSS_D17M4VSS_D18M5VSS_D19
D4VSS_D2
M6VSS_D20M7VSS_D21M8VSS_D22N4VSS_D23N8VSS_D24
D5VSS_D3D6VSS_D4D7VSS_D5D8VSS_D6E5VSS_D7E6VSS_D8E7VSS_D9
k7r323684c-ec25(1 of 3)
P P
P P
P P
P P
P P
P P
P P
P P
P P
P P P P
P P
P P
P P
P P
P P P P P
P P P
P
P
P
P
P
P P P
P P P P P
P P
56-OHM
1 2
0.1U
3
5
6
7
8
2
1
4
ECJ-TVB1A104M
0.022UFA B
G1 G2
1U
2
1U
2
These terminations must be close to the SRAM
** INPUTS **
VTT
SRAM Termination Placement:
QDR II+ VTT
1.8V
Place parallel terminations just beyond the SRAM and FPGA.
FPGA
Virtex 5SRAMDCI
CQ Clock
These terminations must be close to the SRAM These terminations must be close to the SRAM
SRAM Clocks
SRAM Control
SRAM Write Data
A
B
C
D
QDR-II SRAM Write Data, Address Terminations
QDR-II SRAM Termination Decoupling QDR-II Power Inputs
QDR-II SRAM - Power and TerminationsSamsung K7R323684C-EC250
QDR-II SRAM DecouplingPlace close to QDR II SRAM Power Pins
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
at Virtex 5 FPGA using DCI HSTL_I_DCI_18.SRAM Read Data and CQ Clock are terminated
R587 49.9 NO_LOAD=1
49.9R586 NO_LOAD=1
R469 49.9
C83
C80
C216
C354
L118
FPGA_SRAM_C_CLK_PFPGA_SRAM_C_CLK_N
FPGA_SRAM_WDATA23FPGA_SRAM_WDATA22FPGA_SRAM_WDATA21FPGA_SRAM_WDATA20FPGA_SRAM_WDATA19FPGA_SRAM_WDATA18FPGA_SRAM_WDATA17FPGA_SRAM_WDATA16
49.9R468FPGA_SRAM_K_CLK_PFPGA_SRAM_K_CLK_N
R463 49.9
49.9R462FPGA_SRAM_ADDR16FPGA_SRAM_ADDR17
FPGA_SRAM_WDATA24FPGA_SRAM_WDATA25FPGA_SRAM_WDATA26FPGA_SRAM_WDATA27FPGA_SRAM_WDATA28FPGA_SRAM_WDATA29FPGA_SRAM_WDATA30FPGA_SRAM_WDATA31
FPGA_SRAM_WDATA32FPGA_SRAM_WDATA33FPGA_SRAM_WDATA34FPGA_SRAM_WDATA35
FPGA_SRAM_WDATA0FPGA_SRAM_WDATA1FPGA_SRAM_WDATA2FPGA_SRAM_WDATA3FPGA_SRAM_WDATA4FPGA_SRAM_WDATA5FPGA_SRAM_WDATA6FPGA_SRAM_WDATA7
P0V9D_SRAM_VTT
FPGA_SRAM_WDATA15FPGA_SRAM_WDATA14FPGA_SRAM_WDATA13FPGA_SRAM_WDATA12FPGA_SRAM_WDATA11FPGA_SRAM_WDATA10FPGA_SRAM_WDATA9FPGA_SRAM_WDATA8
P0V9D_SRAM_VTT
FPGA_SRAM_ADDR0FPGA_SRAM_ADDR1FPGA_SRAM_ADDR2FPGA_SRAM_ADDR3FPGA_SRAM_ADDR4FPGA_SRAM_ADDR5FPGA_SRAM_ADDR6FPGA_SRAM_ADDR7
FPGA_SRAM_ADDR8FPGA_SRAM_ADDR9FPGA_SRAM_ADDR10FPGA_SRAM_ADDR11FPGA_SRAM_ADDR12FPGA_SRAM_ADDR13FPGA_SRAM_ADDR14FPGA_SRAM_ADDR15
49.9R197
R48 49.9
P0V9D_SRAM_VTTP0V9D_SRAM_VTT
P0V9D_SRAM_VTT P0V9D_SRAM_VTT
P1V8D_SRAM
P0V9D_SRAM_VTT
FPGA_SRAM_C_CLK_NFPGA_SRAM_C_CLK_P
FPGA_SRAM_ADDR[17:0]
U70
C335C110
C547
C336
23-B3,23-C3,23-C5,23-D524-D3,24-E5,28-B2,28-C228-E1,28-E2,29-C4,29-E1
24-C3,24-E5,28-B2,28-E128-E2,29-C4,29-E1
24-C3,24-E5,28-B4,28-E128-E2,29-C4,29-E1
23-B3,23-C3,23-D5,23-E524-D3,24-E5,28-A2,28-B228-E1,28-E2,29-C4,29-E124-C3,24-D3,24-E5,28-C728-E1,28-E2,29-C3,29-E1
29-B4,29-D129-C4,29-D1
24-D3,24-D5,28-A2,28-D128-D2,29-C3,29-E1
24-D3,24-D5,28-A2,28-D128-D2,29-C3,29-E1
FPGA_SRAM_K_CLK_N
FPGA_SRAM_K_CLK_P
FPGA_SRAM_BWN[3:0]
FPGA_SRAM_RDN
FPGA_SRAM_WRN
FPGA_SRAM_WDATA[35:0]
P0V9D_SRAM_VTT
P0V9D_SRAM_VTT
P0V9D_SRAM_VTT
P0V9D_SRAM_VTT
P1V8D_SRAM
P0V9D_SRAM_VTT
P1V8D_SRAM
P0V9D_SRAM_VTT
P0V9D_SRAM_VTT
P0V9D_SRAM_VTTP0V9D_SRAM_VTTP0V9D_SRAM_VTT
C355
C353 C352
C351C350C348
C347
P0V9D_SRAM_VTT
P0V9D_SRAM_VTT
P1V8D_SRAM
P1V8D_SRAM
FPGA_SRAM_RDNFPGA_SRAM_WRN
FPGA_SRAM_BWN0
FPGA_SRAM_BWN3FPGA_SRAM_BWN2FPGA_SRAM_BWN1
P1V8D
P0V9D_VTT
P0V9D_VREF
L117
L116
C862
P0V9D_SRAM_VREF
C861
C860
43
4-20-2009_13:35
29 001
QDR II SRAM - POWER AND TERMINATIONS
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
C337C334C333
C550 C549 C548C338
C555C554 C553C552C551
C572 C571 C558C557 C556
P1V8D_SRAM
C111 C112 C113
C221 C220C219C218C217
49.9R151R152 49.9
49.9R193R194 49.9
49.9R195R196 49.9
49.9R432
R431 49.949.9R430
R429 49.949.9R201
R200 49.949.9R199
R198 49.9 49.9R440R439 49.9
49.9R438R437 49.9
49.9R436R435 49.9
49.9R434
R433 49.9
49.9R448
R447 49.949.9R446
R445 49.949.9R444
R443 49.949.9R442
R441 49.9 49.9R460R459 49.9
49.9R458R457 49.9
49.9R456R455 49.9
49.9R454
R453 49.9
R452 49.949.9R451
R450 49.949.9R449
R461 49.9
49.9R551R550 49.9
49.9R549R509 49.9
49.9R481R471 49.9
49.9R470
R674 49.949.9R673
R588 49.9
49.9R694R693 49.9
49.9R692
C85
C88
C87
C86
C89
C84
C81
C82
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
1
18
VERT
0.1U
2
0.1U
2
0.1U
2
10U
2
42-OHM
1 2
22.1
1
22.1
1
0.1U
2
10K
1
20P
2
FQ1045A-6
1 X1 2X2XTAL
6.000MHz
20P
2
1
2
3
4 5
6
7
8
AT93C46-10SU-1.8
SKDIDO
NCNC
VCC
GND
SP
I EE
PR
OMCS
2.21K
1
0.1U
2
4751
10K
1
0.22U
2
10U
2
42-OHM
1 2
1
2.2U2
10K
1
2.2U2
LN
J308G8L
RA
1
GR
EE
N301
1
10K
1
LN
J308G8L
RA
1
GR
EE
N
3011
LN
J308G8L
RA
1
GR
EE
N
3011
3011
LN
J308G8L
RA
1
GR
EE
N
1
LN
J308G8L
RA
1
GR
EE
N301
1
0.1U
2
0.1U
2
1
2
3 4
5
6
GND
Enable/Disable
NC
OUT
Comp OUT
Vcc
100.000MHz
OSC
4.75K1
1
Vert
1
10
11
12
14
15
16
18
19
2
20
22
24
25
27
28
32
4
5 21
23
8
7
6
31
9 17 29
30263 13
D6D5D4D3D2D1
VCC VCCIO AVCC
GND
D0
AGND
EEDATAEESKEECS
TEST
D7
RD#WR
TXE#RXF#
SI/WUPWREN#
RESET#RSTO#
XTIN
XTOUT
USB-2-Parallel
FT245BL
FIFO
USBDM
USBDP
3V3OUT
1.50K
1
42-OHM
1 2
10U
2
4.7U
2
0.1U2
1
Vert
301
1
LN
J308G8L
RA
1
GR
EE
N
9
8
7
6
5
4
3
2827262524
222120
2
19181716151413
12
11
10
1
23
3029
QFN
CP21025x5mm
REGIN
VDD
D-
D+
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RTSRXDTXDDSRDTR
RIDCD
SUSPEND
SUSPEND
RST
GND
VBUS
CTS
GNDPADDLE
SHIE
LD
(SDcard)microSD
CD/CE
CLK
DATO/MISO
GN
D
VC
C
RSV
1
RSV
0
DATI/MOSI
1U
2
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
Momentary ButtonsActive Low
** OUTPUTS **** INPUTS **
USB to RS-232 Interface
Debug LEDs
Debug Push Buttons
MicroSD Interface
100MHz FPGA Clock
USB to RS-232
MicroSD Interface
FT245BL USB Interface
USB Type-B Peripheral (Back-Up)DEBUG LEDsPUSH-BUTTONs
100MHz Digital Clock micro SD Card (2GB)
A B C
E FD LA HEADER
FT245BL USB Interface
Logic Analyzer
G
Xilinx Virtex-5 SX50T FPGA Peripherals
USB-to-RS-232 Debug InterfaceUSB Bus-Powered
C28
8
TP224
P3V3D_V5_CP2102
TP
223
V5_USB_D_N
V5_USB_D_P
TP219TP220TP221TP222
FPGA_V5_SD_CARD_DETECTFPGA_V5_SD_TXDFPGA_V5_SD_CLK
6 9
2
3
5
7
4 1 8J65
U68
P5VD_V5_USB
V5_FTDI_XTAL_IN
V5_FIFO_USB_P
V5_FIFO_USB_N
V5_FTDI_POWER
D29
R10
4
FPGA_V5_RS232_TX
J60
C56
0
C10
9
C131
L32
R213
U2J61
V5_FTDI_XTAL_OUT
R220
V5_FTDI_RESETN
V5_USB_D_NV5_USB_D_P
FPGA_V5_LA_CLK
FPGA_V5_LA_DATA[7:0]22-C2,22-D2,22-D5,30-B5
30-E1
22-D2,22-D5,30-B5,30-E1
FPGA_V5_LA_DATA7FPGA_V5_LA_CLK
P3V3D_V5_SD
FPGA_V5_FTDI_RSTOUTN
P5VA_V5_USBP5VD_V5_USB
FPGA_V5_FTDI_DATA[7:0]
FPGA_V5_FTDI_DATA0
FPGA_V5_FTDI_DATA7FPGA_V5_FTDI_DATA6FPGA_V5_FTDI_DATA5FPGA_V5_FTDI_DATA4FPGA_V5_FTDI_DATA3FPGA_V5_FTDI_DATA2FPGA_V5_FTDI_DATA1
P3V3D
22-D3,22-E5,30-E122-D3,22-E5,30-E1
P3V3D
U82 C562
C561
P3V3D_V5_SDP3V3D
R109
D34
P3V3D
S8
D33
R108
R107
D32
R106
D31
R13
8
R105
D30
C15
3
R13
7
C15
2
S7
FPGA_V5_CLK100MHZ_N
FPGA_V5_CLK100MHZ_PNC
FP
GA
_V5_
SD
_BU
SY
_LE
D
FPGA_V5_SD_RXD
FPGA_V5_RS232_CTSFPGA_V5_RS232_RTS
FPGA_V5_RS232_RX
NC
FP
GA
_V5_
LE
DS
1
FP
GA
_V5_
LE
DS
2
FP
GA
_V5_
LE
DS
3
FPGA_V5_LEDS[3:0]FP
GA
_V5_
LE
DS
0
FPGA_V5_PUSHBUTTON0
FPGA_V5_PUSHBUTTON1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
FPGA_V5_RS232_RTS
FPGA_V5_RS232_RX
FPGA_V5_LEDS[3:0]
FPGA_V5_PUSHBUTTON[1:0]
FPGA_V5_CLK100MHZ_PFPGA_V5_CLK100MHZ_N
FPGA_V5_SD_RXD
22-D1,22-D3,30-B3,30-D522-D1,22-D3,30-B3,30-E5
22-C3,22-D1,30-E5
22-C2,22-D1,30-C2,30-E5
22-D1,22-D3,30-C2,30-E5
22-D1,22-D3,30-E5
22-D1,22-D3,30-E5
FPGA_V5_RS232_CTS
FPGA_V5_RS232_TX
FPGA_V5_SD_CARD_DETECTFPGA_V5_SD_CLKFPGA_V5_SD_TXD
FPGA_V5_SD_BUSY_LED22-C3,22-E5,30-B4,30-E1
22-C3,22-E5,30-E122-C3,22-E5,30-E122-C3,22-E5,30-E1
L34
C133
P5VD
P5VD_V5_USB P5VA_V5_USB
P3V3D_V5_USB
C312
R14
0
R652
C56
7
P5VD_V5_USB
R338
U100
C62
5
U13
C62
4
R139
C56
6
R641
R640
P3V3D
L33
C132 C
565
C564
C563
V5_FTDI_USBDP
V5_FTDI_XTAL_IN
FPGA_V5_FTDI_SI_WU
FPGA_V5_FTDI_RXFN
FPGA_V5_FTDI_WRNFPGA_V5_FTDI_RDN
V5_FTDI_EESDIO
V5_FTDI_EECSV5_FTDI_EESCK
V5_FTDI_XTAL_OUT
FPGA_V5_FTDI_TXEN
FPGA_V5_FTDI_PWRENN
NCV5_FTDI_EECSV5_FTDI_EESCK
NCV5_FTDI_EESDIO
V5_FTDI_USBDM
22-D5,22-E3,30-C4,30-E1
22-D5,22-E3,30-C4,30-E122-D5,22-E3,30-C4,30-E1
22-C1,22-D3,22-E3,30-C530-D5
22-C1,22-E3,30-D5
22-C1,22-E3,30-C4,30-D522-C1,22-E3,30-C4,30-D522-C1,22-E3,30-C4,30-D5
FPGA_V5_FTDI_SI_WU
FPGA_V5_FTDI_RDNFPGA_V5_FTDI_WRN
FPGA_V5_FTDI_RSTOUTN
FPGA_V5_FTDI_DATA[7:0]FPGA_V5_FTDI_TXENFPGA_V5_FTDI_RXFNFPGA_V5_FTDI_PWRENN
J68
FPGA_V5_LA_DATA3FPGA_V5_LA_DATA2FPGA_V5_LA_DATA1FPGA_V5_LA_DATA0
FPGA_V5_LA_DATA4FPGA_V5_LA_DATA5FPGA_V5_LA_DATA6
43
4-20-2009_13:35
30 001
XILINX VIRTEX-5 SX50T FPGA PERIPHERALS
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
P3V3D_V5_SDTP210
TP209
TP208TP207
TP216TP215
TP212TP211TP214TP213
TP
218
TP
217
V5_USB_VBUS
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
+5.2V
71nH76nH71nHA = -3 dB
16
2
sub-phase 0
sub-phase 1
ODDR
CLK CLK
250MH
z DD
R
250MH
z DD
R
333MH
z DD
R
64-bit D
ata, 16-bit A
dd
ress
CLK
+
-
NL
NL
15p
F
499
270 62
-
+
500MS/s
A = -2.4 dB
Analog
39.6pF500MS/s
59.9pF 59.9pF39.6pF
A = -2.4 dB
12-bit
500MS/s
OVRDRDY
SamplingClock Input
500 MHz
+
-
THS4509
100
100
5.2pF
AD9516
Spectrum Analyzer IF and Signal Source Block Diagrams
Devices
DAC5682
16-bit
SamplingClock Input
500 MHz
500MS/s16-bit LVDS
250MHz DDR
250MHz DDR
DCLK
fc = 140 MHz, BW = 120 MHz, Ripple = 0.5 dB7th Order Chebyshev Lowpass Filter
62270
226
OPA695226
15pF
49.9110
49.9NL
THS4302
-
+
49.9 A = 8 dBZi = 50 Ohm
Zo = 100 Ohm
Zi = 200 Ohm
ADS5463 12-bit LVDS
CLK
DI[15:0]
DA[15:0]
DB[15:0]
sub-phase 1
2x Polyphase Decimation Filter
2x Polyphase Decimation Filter
sub-phase 0
DB[15:0]
DA[15:0]
DO[15:0]
CLK
XC5VSX50T-3FF1136C
Xilinx Virtex 5 SX50TAsAP v2
AsAP v2
ODDR
Write D
ata
Read
Data
DISPLAY
FFT
Co-processor
RF Input
Spectrum Analyzer
DC to 120 MHzZi = 50 Ohm
Zo = 50 Ohm
IDDR
BW: 120 MHz
2
DO[15:0]
DB[15:0]
DA[15:0]
BW: 120 MHz
2x Polyphase Interpolation Filter
2x Polyphase Interpolation Filter
DI[15:0]DO[15:0]
CLK
IFF0
1
IN
X2
Generator
Waveform
Arbitrary
SDRAM Controller
499
SamsungQDR-II SRAM
K7R323684C-EC250
MicronDDR2 SDRAM
SODIMM
MT16HTF25664H – 2GB
16
-5.2V
+5.2V
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
A = 14 dB
Zo = 50 Ohm
DC to 120 MHz
Signal Source
RF Output
A = -1 dB
A = -3 dB
A = -9 dBm
A = 11 dBm
71nH 76nH 71nH
71nH 76nH 71nH
19.8pF 30pF 30pF 19.8pF
+2.5V
-2.5V
A = -1 dB
+5.2V
fc = 140 MHz, BW = 120 MHz, Ripple = 0.5 dB7th Order Chebyshev Lowpass Filter
A = 14 dBZi = Zo = 50 Ohm
43
3-27-2009_12:24
31 001
SPECTRUM ANALYZER IF AND SIGNAL SOURCE BLOCK DIAGRAMS
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
Spectrum Analyzer IF Estimated Performance
UC Davis Confidential Copyright © 2008 VLSI Computation Lab43
3-27-2009_12:24
32 001
SPECTRUM ANALYZER IF ESTIMATED PERFORMANCE
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
524-001-11Shield
NL
1U2G
NDS
MP
NL
287
0.0
0.0
NL
0.1U
2
30.1
1
10U2
47P
2
1K-OHM
NL
NL
49.9
68.11
0.01
0.01
49.91
68.11
0.01
0.1U 2
0.1U 2
1
1
1
100
1
100
1
182
182
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
10U
2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
49.91
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
22NH 22NH 22NH 22NH27NH 27NH 27NH
3.9P2
56P2
56P2
3.9P2
0.1U
2
1K-OHM
1K-OHM
1K-OHM
30.1
1
47P
2
36P
2
3.6P
2
1K-OHM
10U
2
10U
2
1
100
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
1K-OHM
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
1367-000-G91P-61
6.8
6.8
17
15
14
8
6
5
7
1 2 3 4 13
PD16 9101112
THS4302RGT14dB
Vout
Vs+
Vin+Vin-
PMH Vs- NC
THS4509RGTT
NC
PD
Vs-PMH
Vin-
Vin+ Vout-
Vout+
WB OP-AMPCM
Vs+
NL
1
0.0
17.4
287
NL 1U
2GND
SMP
GND
SMP
1U
2
NL
49.9
1
3.6P
2 36P
2
5.1P 2
1
10
11
1213 14
15
16
17
1819
2 2021
2223
2425
2627
28
29
3
30
31
32
33
34
35
36
37
38
39
4
40
41
42
43
44
45
46
47
48
49
5
50
5152
53
54
55
56
57
58
59
6
60
61
62
63
64
6566
67
68
69
7
70
71
72
73
74
75
76
77
78
79
8
80
9
ADS5463IPFP
81
CLKCLK
AINAIN
VREF
RESVD1RESVD2
NC5
NC4NC3
NC2NC1
NC6
NC7NC8
OVR
D11D11D10D10
D9D9D8D8D7D7D6D6D5D5D4D4
D0D0D1D1D2D2D3D3
DRYDRY
NC10
OVR
NC9
PMHGND
AVDD5 AVDD3 DVDD3
27NH 22NH
GND
SMP
1U
2
Swap Pos and Neg at ADC Input for LayoutInvert ADC data in Virtex-5 FPGA
Place NL right on the transmission line.
Place NL right on the transmission line.
A = +14 dB
NF = 16 dB
IIP3 = 30 dBm
-2.5V Analog: I = 190mA Max+2.5V Analog: I = 190mA Max
Pre-Amplifier DecouplingI
R_F
R_G
R_T
F Pre-Amplifier (+8 dBm)P
lace
ho
lder
fo
r0.
22u
F c
apac
ito
rsif
nee
ded
.
A = -1.6 dB
NF = 1.6 dB
Distortion Filter (Low Pass)
fc = 126 MHzBW = 120 MHz
R_TR_S
R_G
R_F
A = +8 dB
NF = 17.1 dB
IIP3 = 38 dBm
+5V Analog: I = 50mA Max
R_PU R_PU
L = 71 nHL = 76 nHL = 71 nH
7th order Chebyshev Lowpass Filter
fc = 140 MHz, BW = 120 MHz, and Ripple = 0.5 dBA = -2.4 dB
NF = 2.4 dB
+3.3V Digital: I = 88mA Max
+3.3V Analog: I = 138mA Max
+5V Analog: I = 330mA Max
1. Place a 6-by-6 array of thermal vias in the thermal pad area.These holes should be 13 mils in diameter. The small sizeprevents wicking of the solder through the holes.
2. It is recommended to place a small number of 25-mil-diameterholes under the package, but outside the thermal pad area toprovide an additional heat path.
3. Connect all holes (both those inside and outside the thermal padarea) to an internal copper plane (such as a ground plane).
4. Do not use the typical web or spoke via-connection pattern whenconnecting the thermal vias to the ground plane. Flood the via,rather than using a spoke pattern.
ADC PC Layout Notes:
(Rated @ 400mA)
(Rated @ 400mA)
MMZ1608Y102B
(Rated @ 400mA)
MMZ1608Y102B
(Rated @ 400mA)
MMZ1608Y102B
MMZ1608Y102B
Zi=Zo=50 OhmsA = -1 dB +/- 0.3 dBNF = 1 dB +/- 0.3 dB
SPECTRUM ANALYZER IF
Future Bit Additions
IIP3 = 44.8 dBm
NF = 18.9898 dB
A = +13.9 dB
Pin = +3.9 dBm
A B LNA (+14 dBm) C 1dB PAD D Anti-Alias Filter
E 1dB PAD
(Rated @ 400mA)
High-Speed ADC (12-bit, 500MS/s)G
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
High-Speed ADC Decoupling
FS = 2Vpp
3dB Pad
Zi=Zo=50 OhmsA = -3 dB +/- 0.3 dBNF = 3 dB +/- 0.3 dB
H
MMZ1608Y102B
AD9516 LVPECL Output (Sheet 12)
Place 100 Ohm Term near ADC Clk Pins
Place NL right on the transmission line.
NF = 1 dB +/- 0.3 dBA = -1 dB +/- 0.3 dBZi=Zo=50 Ohms
Pla
ce N
L r
igh
t o
n t
he
tran
smis
sio
n li
ne.
C199
IF_AAF_OUT
IF_AAF_OUT
J10
ADC_IN_N
ADC_IN_N
ADC_IN_P
ADC_IN_P
IF_PREAMP_OUT_P
L122L74
IF_PREAMP_CM
IF_PREAMP_OUT_NIF_PREAMP_IN
IF_IN
U58
C339
C21
C16
ADC_VREF
ADC_VREF
R86
R402C197
J8
IF_AAF_IN
J9C198
R403
IF_LNA_IN
R40
6
R395
12-B2,12-E5
12-B2,12-E5
AIF_ADC_CLKIN_P
AIF_ADC_CLKIN_N
R398
R306 133
R40
0
10
13 14 15 1617
2 3
4
5 6 7 8
9
1
12
11
U83
U74
P2V5A_AIF
R37
0
R37
1
NC
P5V2A_PREAMP
J40
C584
C589
P3V3A_ADC
C586
C578
L8
C573 C575C574
R12
P3V3D_AIF
P5V2A_ADC
C136
C13
4
L7
NC
C17
C22
24-C3,24-E1
24-D3,24-E1
P2V5A_IFLNA
C317
R369
FPGA_ADC_DATA_RDY_P
FPGA_ADC_DATA_N15FPGA_ADC_DATA_P15FPGA_ADC_DATA_N14FPGA_ADC_DATA_P14FPGA_ADC_DATA_N13FPGA_ADC_DATA_P13
FPGA_ADC_DATA_P12FPGA_ADC_DATA_N12
FPGA_ADC_OVR_PFPGA_ADC_OVR_N
L11
P3V3D_ADC
L10
P3V3A_AIF P3V3A_ADC
L9
C598
TP232
TP233
TP231
FPGA_ADC_DATA_P11FPGA_ADC_DATA_N11
FPGA_ADC_DATA_N10
FPGA_ADC_DATA_N9
FPGA_ADC_DATA_N8
FPGA_ADC_DATA_N7
FPGA_ADC_DATA_N6
FPGA_ADC_DATA_N5
FPGA_ADC_DATA_N4
FPGA_ADC_DATA_N3
FPGA_ADC_DATA_N2
FPGA_ADC_DATA_N1
FPGA_ADC_DATA_N0FPGA_ADC_DATA_P0
FPGA_ADC_DATA_P1
FPGA_ADC_DATA_P2
FPGA_ADC_DATA_P3
FPGA_ADC_DATA_P4
FPGA_ADC_DATA_P5
FPGA_ADC_DATA_P6
FPGA_ADC_DATA_P7
FPGA_ADC_DATA_P8
FPGA_ADC_DATA_P9
FPGA_ADC_DATA_P10
C14
3
C27
C26
C14
4
FPGA_ADC_DATA_RDY_N
TP234
P5V2A
P5V2A
24-D3,24-E1
24-C3,24-E124-C3,24-E1
24-C3,24-E124-C3,24-E1
24-C3,24-E124-C3,24-E1
24-C3,24-E124-C3,24-E1
24-C3,24-E1
24-D3,24-E1
24-D3,24-E124-D3,24-E1
24-D3,24-E124-D3,24-E1
24-C3,24-E124-C3,24-E1
24-D3,24-E1
24-D3,24-E1
24-D3,24-E124-D3,24-E1
24-D3,24-E124-D3,24-E1
24-D3,24-E124-D3,24-E1
24-D3,24-E1
24-D3,24-E1
24-D3,24-E124-D3,24-E1
24-D3,24-E124-D3,24-E1
24-D3,24-E124-D3,24-E1
24-D3,24-E1
L71L72L73 L121L123L124L125
NC
43
4-20-2009_13:35
33 001
SPECTRUM ANALYZER IF
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
R85
C576
C577 C579 C580 C581
C585C583 C582
P5V2A_ADC
C13
5
C588 C587C592C591C590
P3V3D_ADC
R46
4
P5V2A_PREAMP
R46
5
R645348
R702
R703
R646348
P5V2A_PREAMP
R305 133
TP
235
C568
C569
R147
R112
R87
R166
R167
R113
R372
R38
8
R38
7
L6C58
N2V5A_AIF
C57
R377C146
N2V5A_IFLNA
R40
1
R397
R399
R40
7
R404
IF_LNA_OUT
J11
C20
0R
405
2 3 4 5 61SH2
287
17.4
287
15P2
15P2
27NH27NH27NH27NH 22NH 22NH22NH22NH22NH
4700PFA B
G1 G2
42-OHM
1 2
10U2
10U
2
0.1UFA B
G1 G2
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
10U
2
42-OHM
1 2
270
1
62
1
1
49.9
1
49.9
1
499
1
42-OHM
1 2
47U
2
49.9
1
NL
1
110
1
1
100
0.01U
2
NL2
NL2
0.01U
2
226
1
226
1
62
1
270
1
499
1
NL
2
1367-000-G91P-61
NL
1
2
56
4
1
3
OPA695IDBV
42-OHM
1 2
47U
2 1U2
47U
2
4700PFA B
G1 G2
0.1UFA B
G1 G2
42-OHM
1 2
4700PFA B
G1 G2
4700PFA B
G1 G2
18P2
1.8P2
18P2
1.8P2
15P2
15P2
22NH27NH22NH27NH22NH27NH22NH27NH22NH
DAC5682ZIRGCT
RESETB 49
65
CLKIN2
CLKINC3
DCLKP25
DCLKN26
D15P7
D15N8
D14P11
D14N12
D13P13
D13N14
D12P15
D12N16
D11P17
D11N18
D10P19
D10N20
D9P21
D9N22
D8P23
D8N24
D7P27
D7N28
D6P29
D6N30
D5P31
D4P33
D4N34
D3P35
D3N36
D2P37
D2N38
D1P40
D1N41
D0P42
D0N43
SYNCP5
SYNCN6
IOUTB1 61
IOUTA1 52
EXTIO 56
EXTLO 58
BIASJ 57
GND
4
IOVDD
9
SDENB 48
SDO 45
SDIO 46
DVDD
10395063
AVDD
5154555962
CLKVDD
1
VFUSE
44
LPF 64
D5N32SCLK 47
IOUTA2 53
IOUTB2 60
PMH
4700PFA B
G1 G2
4700PFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
4700PFA B
G1 G2
4700PFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.022UFA B
G1 G2
0.0
1
0.0
1
524-001-11Shield
953
1
NL
1
1
100
0.1U
2
L = 71 nHL = 76 nHL = 71 nH
Zi=Zo=50 Ohms
From AD9516 (LVPECL)
Place Jumper on 2-3
Loop Filter
Place Holder+3.3V Analog: I = 300mA Max
+1.8V Analog: I = 800mA Max
D Amplifier-5V Analog: I = 100mA Max
+5V Analog: I = 100mA Max
A
B C Anti-Image Filter
Signal SourceOutput
E
IIP3 = 20 dBm
NF = 14 dB
fc = 140 MHz, BW = 120 MHz, and Ripple = 0.5 dB
7th order Chebyshev Lowpass Filter
A = -2.4 dB
NF = 2.4 dB
A = +14 dB
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
DAC5682 Decoupling
A = -3 dB +/- 0.3 dBNF = 3 dB +/- 0.3 dB
F
G H OPA695 Decoupling
3dB PAD
L = 76 nH L = 71 nHL = 71 nH
Output Stage
High-Speed DAC (16-bits, 1GS/s) SIGNAL SOURCE
SS_AIF_OUT_PSS_AIF_IN_P
SS_AIF_OUT_NSS_AIF_IN_N
SS_OUT
SS_AMP_OUT
SS_AMP_OUT
DAC_SS_NDAC_SS_P
C616
FPGA_DAC_SYNC_PFPGA_DAC_SYNC_N
DAC5682_UNUSED_NDAC5682_UNUSED_P
R14
R594
DAC5682_EXTLOR538
FPGA_DAC5682_SCLK
FPGA_DAC5682_SDO
2 3 4 5 61SH3
R530
R531
C222
C610C607C609C608C223C224
C602C599C600C601C225C226
FPGA_DAC_CLK_NFPGA_DAC_CLK_P
FPGA_DAC_DATA_N0FPGA_DAC_DATA_P0FPGA_DAC_DATA_N1FPGA_DAC_DATA_P1FPGA_DAC_DATA_N2FPGA_DAC_DATA_P2FPGA_DAC_DATA_N3FPGA_DAC_DATA_P3FPGA_DAC_DATA_N4FPGA_DAC_DATA_P4FPGA_DAC_DATA_N5FPGA_DAC_DATA_P5FPGA_DAC_DATA_N6FPGA_DAC_DATA_P6FPGA_DAC_DATA_N7FPGA_DAC_DATA_P7FPGA_DAC_DATA_N8FPGA_DAC_DATA_P8FPGA_DAC_DATA_N9FPGA_DAC_DATA_P9FPGA_DAC_DATA_N10FPGA_DAC_DATA_P10FPGA_DAC_DATA_N11FPGA_DAC_DATA_P11FPGA_DAC_DATA_N12FPGA_DAC_DATA_P12FPGA_DAC_DATA_N13FPGA_DAC_DATA_P13FPGA_DAC_DATA_N14FPGA_DAC_DATA_P14FPGA_DAC_DATA_N15FPGA_DAC_DATA_P15
FPGA_DAC5682_SDIO
FPGA_DAC5682_SDENB
FPGA_DAC5682_RSTB
DAC5682_UNUSED_PDAC5682_UNUSED_N
U18
L82 L61 L87 L75 L88 L76 L90 L77 L89
C18
C19
C50
C29
C49
C28
C229
P5V2A_SS_AMPF
N5V2A_SS_AMPF
C227
L37
N5V2A_SS
P5V2A
C594C228
C37
9
23-B3,23-B523-B3,23-B5
12-A2,12-E5
12-A2,12-E5SS_DAC_CLKIN_N
P1V8A_SSF
P1V8A_SS
P3V3A_SSF P3V3A_SSF
P3V3A_SSF
P3V3A_SSF
P3V3A_SSF
P5V2A_SS_FILT
C32
4
C38
0
P5V2A
L36
U73
R59
2
N5V2A_SS_AMPF
P5V2A_SS_AMPF
J41
C92
R50
R30
0
R65
4
R502
R501
23-B3,23-B5
C325
23-B5,23-C323-B5,23-C3
23-B5,23-C3
23-B5,23-C323-B5,23-C323-B5,23-C323-B5,23-C323-B5,23-C3
15-C5,15-D3
15-C5,15-D315-D1,15-D3
C91
C90
C326R13
DAC5682_EXTLO
P1V8A_SSF
R5
R59
3
R90
C37
8
L35
R49
R89
R88
P1V8A_SSFP1V8A_SSF
J66
15-C5,15-D3
15-C5,15-D3
SS_DAC_CLKIN_P
23-B3,23-B5
23-B3,23-B523-B3,23-B5
23-B3,23-B523-B3,23-B5
23-B3,23-B523-B3,23-B5
23-B3,23-B523-B3,23-B5
23-B3,23-B523-B3,23-B5
23-B3,23-B523-B3,23-B5
23-B3,23-B523-B3,23-B5
23-B3,23-B523-B3,23-B5
23-B5,23-C323-B5,23-C3
23-B5,23-C323-B5,23-C323-B5,23-C3
23-B5,23-C3
23-B5,23-C323-B5,23-C3
R65
5
R30
1
L39
P5V2A_SS_FILT
C14
1
P3V3A_SS
43
4-20-2009_13:35
34 001
SIGNAL SOURCE
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
C593
P5V2A_SS_AMPF
C13
8
N5V2A_SS_AMPF
C14
0
L38
C230
L95 L94 L93 L92L91L81 L80 L79 L78
C24
C23
R42
6
R396
R42
5
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
1U2
1367-000-G91P-61
1367-000-G91P-61
1U
2
1367-000-G91P-61
SN65LVDS1DBVR
VCC 1
GND 2
3Z4 Y
D5
10K
1
5 432
I/O I/OI/O
6I/O V
NV
P
1
NU
P43
01M
R6T
1G
0.0
1
49.9
1
0.1U
2
0.1U
2
0.0
1
1
100
1
100
5 432
I/O I/OI/O
6I/O V
NV
P
1
NU
P43
01M
R6T
1G
1U
2
5 432
I/O I/OI/O
6I/O V
NV
P
1
NU
P43
01M
R6T
1G
SN65LVDS1DBVR
VCC 1
GND 2
3Z4 Y
D5VT2
VREF-AC3
4 /IN
IN1
6/Q7Q
VCC 8
GND 5
SY58601UMG TR
9PMH
1U
2
1U2 N
L
1
NL
1
49.91
49.9
1
49.9
1
TPS73701DRB
5 EN
OUT 1
3FB
IN8
4
GND NC
29 6 7
1
36.5
K
34K
1
5.62K1
2.2U
2
390-OHM
390-OHM
390-OHM
.01
1
10UH
10U
2
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
~ 60 mA
R1 R2 Vout
1.2V
ShieldedIsat: 9.36A
** INPUTS ** ** OUTPUTS **
Trigger Output Auxiliary Input
Trigger Input
Trigger Output BufferTrigger Input BufferA
Auxillary InputE
Trigger Input/Output and Auxiliary Input
36.5k39.62k +2.51V
B
C D
2.5V, 80mA
~ 10 mA
~ 10 mA
+5.5V Filter +2.5V Trigger Analog Supply Regulation
DCR: 21.8mOhm
Place R159 near J42Place R158 near U52
FPGA_TRIG_OUT_N
FPGA_TRIG_OUT_PTRIG_OUT
TRIG_INTOUTPTOUTN
AUX_IN
FP_TRIG_IN
FP_AUX_IN
P2V5F_TRIG_IN P2V5F_TRIG_OUT
P2V5F_TRIG_OUT
C14
2
L70 R366
L102
1.2A, 390R
L101
1.2A, 390R
L100
1.2A, 390R
C12
R714R302
R69
0
U97
R159R158
R261
R65
0
R64
9
C447
C448
U52U41
D38
C449
D40
R17
R16
R533
FPGA_TRIG_IN_NFPGA_TRIG_IN_P
C619
C618
R91
R532
D39
R14
1
U40
J44
P2V5F_TRIG_OUT
P2V5F_TRIG_IN
FPGA_AUX_IN_P
P2V5F_TRIG_IN
FPGA_AUX_IN_N
22-D3,22-D5,35-D3,35-E122-D3,22-D5,35-D3,35-E1
NC
NC
NC
C446
NC
P2V5F_AUX_IN
FPGA_TRIG_OUT_NFPGA_TRIG_OUT_P
J42
J43
P2V5F_AUX_IN
FPGA_AUX_IN_NFPGA_AUX_IN_P
22-D1,22-D3,35-B3,35-E522-D1,22-D3,35-B3,35-E5
22-C1,22-D3,35-D3,35-E522-C1,22-D3,35-D3,35-E5
FPGA_TRIG_IN_PFPGA_TRIG_IN_N
NC
NC
NC
NC
NC
TP
108
TP
107
TP
106
P2V5A_TRIGP5V5AF_TRIG
C45
0
NC
NC
NC
P5V5A
P2V5F_AUX_IN
43
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TRIGGER INPUT/OUTPUT AND AUXILIARY INPUT
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
NCNC
0.1U
2
294
3SN74LVC1G07DBV
2
5
4
1
294
1
402
1
294
1
294
1
294
1
294
1
294
1
294
0.1U
2
0.1U
2
0.1U
2
0.1U
2
0.1U
2
0.1U
2
0.1U
2
0.1U
2
3SN74LVC1G07DBV
2
5
4
3SN74LVC1G07DBV
2
5
4
3SN74LVC1G07DBV
2
5
4
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
142-0701-231
0.0
1
30.1
1 30.1
130.1
1 30.1
1
30.1
1
30.1
1
30.1
1
30.1
1 30.1
1
49.9
1
1
10
PBC05DAAN
VERT
121K
1
0.0
1
3SN74LVC1G07DBV
2
5
4
3SN74LVC1G07DBV
2
5
4
3SN74LVC1G07DBV
2
5
4
3SN74LVC1G07DBV
2
5
4
3SN74LVC1G07DBV
2
5
4
N2 B0_IN_CLKC2 B0_IN_DATA0D3 B0_IN_DATA1D2 B0_IN_DATA2E4 B0_IN_DATA3G3 B0_IN_DATA4J2 B0_IN_DATA5K1 B0_IN_DATA6K2 B0_IN_DATA7N3 B0_IN_DATA8
R1 B0_IN_DATA9T1 B0_IN_DATA10U1 B0_IN_DATA11V1 B0_IN_DATA12
AA1 B0_IN_DATA13Y3 B0_IN_DATA14
AC3 B0_IN_DATA15P4 B0_IN_REQUESTN1 B0_IN_VALID
AC10 B0_EXTERNAL_CLK
K20B1_OUT_CLKE20B1_OUT_DATA0E21B1_OUT_DATA1E22B1_OUT_DATA2F20B1_OUT_DATA3H20B1_OUT_DATA4H21B1_OUT_DATA5F23B1_OUT_DATA6G23B1_OUT_DATA7J22B1_OUT_DATA8
P21B1_OUT_DATA9P20B1_OUT_DATA10P23B1_OUT_DATA11T23B1_OUT_DATA12W22B1_OUT_DATA13Y23B1_OUT_DATA14Y20B1_OUT_DATA15L22B1_OUT_REQUESTL21B1_OUT_VALID
vcl-asapv2-sbga304(2 of 9)
1
1 1 1
1
1 1
1
1
1
11 1
1
1
11
11
0
0
00
0
0
0
0 0
0
0
0
0
0
0
0
0
0
0
0
Y11 B2_RESET_COLDAC11 B2_CFG_CLKAB11 B2_CFG_VALIDAB7 B2_SPI_CLKAB5 B2_SPI_SELAB6 B2_SPI_LOADAA7 B2_SPI_MISOAC5 B2_SPI_MOSI
AB14B3_TEST_OUT0AA14B3_TEST_OUT1Y14B3_TEST_OUT2AC15B3_TEST_OUT3Y17B3_TEST_OUT4AB18B3_TEST_OUT5AA18B3_TEST_OUT6AC19B3_TEST_OUT7AC21B3_TEST_OUT8
vcl-asapv2-sbga304(3 of 9)
3
3
3
3
3
3
3
3 3
2
2
222 2
2
2
A8 B14_ANAG1A9 B14_ANAG2
A10 B14_ANAG3A11 B14_ANAG4
B11B15_TEMP_DIODEC11B15_ANAREXTD11B15_SPECIALGNDJ3B15_NC_00J4B15_NC_01AA11B15_RESET_COUNTCLK
vcl-asapv2-sbga304(9 of 9)
15
15
15
15 15
15
14 14 14 14
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
AsAP 1 Data Output
** INPUTS **** OUTPUTS **
AsAP 1 Data Output
AsAP 1 Data Input
AsAPv2 #1 Data In/Out, Config, Analog, Test
AsAP 1 Config Output
AsAP Main Data Input and Output
AsAP Analog and Miscellaneous I/O
Place 30.1 Ohm Series Resistors on all other SPI, CFG, and Reset Cold signals near FPGA Outputs
Place 30.1 Ohm Series Resistor on AsAP SPI_MISO near AsAP IC.
AsAP 1 Data Input
AsAP Configuration and Test Port
A B
C D
AsAP Config Level Translate
AsAP 1 Config Input
ASAP1_EXT_CLK_IN
ASAP1_ANLG1ASAP1_ANLG2
U43U43
U43
ASAP1_ANLG4ASAP1_ANLG3
P2V5DP2V5D
P2V5DP2V5D
P2V5D P2V5D
P2V5DP2V5D
ASAP1_CFG_CLK
ASAP1_SPI_CLK
ASAP1_SPI_LOAD
ASAP1_SPI_MOSI
P2V5D
ASAP1_CFG_VALID
P2V5D
ASAP1_SPI_CLK FPGA_ASAP1_MOSI
ASAP1_SPI_MISO
FPGA_ASAP1_SPI_LOAD
FPGA_ASAP1_SPI_CSNFPGA_ASAP1_RESET_COLD
FPGA_ASAP1_CFG_CLK
FPGA_ASAP1_CFG_VALID
FPGA_ASAP1_SPI_CLK
ASAP1_SPI_MISO
ASAP1_SPI_CSN
ASAP1_CFG_VALID
ASAP1_RESET_COLD
U108
U106
U104
U103
U102
FPGA_ASAP1_VLD_INFPGA_ASAP1_CLK_IN
FPGA_ASAP1_DATA_IN[15:0]
ASAP1_RST_CNTCLK
TP
264
TP
256
FPGA_ASAP1_RST_CNTCLK15-B5,15-D3,36-C2,36-E1
FPGA_ASAP1_MISO15-C1,15-D3,36-C2,36-E5
FPGA_ASAP1_MOSIFPGA_ASAP1_SPI_LOADFPGA_ASAP1_SPI_CSNFPGA_ASAP1_SPI_CLKFPGA_ASAP1_CFG_VALIDFPGA_ASAP1_CFG_CLKFPGA_ASAP1_RESET_COLD
23-C5,23-D3,36-C4,36-E1
23-C5,23-D3,23-E3,36-D336-E1,37-C2,37-C4,37-D1
37-D223-C5,23-D3,36-D3,36-E137-C4,37-D1,37-D223-B5,23-D3,36-C3,36-E137-B2,37-D1,37-D2
23-D3,23-E1,36-D4,36-E5
FPGA_ASAP1_REQ_IN
R53
4
TP254R367
NCASAP1_TEST0
ASAP1_TEST2
ASAP1_TEST4ASAP1_TEST6
ASAP1_TEST8ASAP1_TEST7
ASAP1_TEST5
J62
ASAP1_TEST3
ASAP1_TEST1
ASAP1_TEST8ASAP1_TEST7ASAP1_TEST6ASAP1_TEST5ASAP1_TEST4ASAP1_TEST3ASAP1_TEST2ASAP1_TEST1ASAP1_TEST0
FPGA_ASAP1_REQ_OUTFPGA_ASAP1_VLD_OUT
FPGA_ASAP1_DATA_IN7
FPGA_ASAP1_DATA_IN9
ASAP1_EXT_CLK_IN
FPGA_ASAP1_REQ_IN
FPGA_ASAP1_CLK_OUTFPGA_ASAP1_DATA_OUT0FPGA_ASAP1_DATA_OUT1FPGA_ASAP1_DATA_OUT2FPGA_ASAP1_DATA_OUT3FPGA_ASAP1_DATA_OUT4FPGA_ASAP1_DATA_OUT5FPGA_ASAP1_DATA_OUT6FPGA_ASAP1_DATA_OUT7FPGA_ASAP1_DATA_OUT8
FPGA_ASAP1_DATA_OUT9FPGA_ASAP1_DATA_OUT10FPGA_ASAP1_DATA_OUT11FPGA_ASAP1_DATA_OUT12FPGA_ASAP1_DATA_OUT13FPGA_ASAP1_DATA_OUT14FPGA_ASAP1_DATA_OUT15
R92
FPGA_ASAP1_DATA_IN14
FPGA_ASAP1_DATA_IN12
FPGA_ASAP1_DATA_IN10
FPGA_ASAP1_DATA_IN8
FPGA_ASAP1_DATA_IN6
FPGA_ASAP1_DATA_IN4
FPGA_ASAP1_DATA_IN2
FPGA_ASAP1_DATA_IN0FPGA_ASAP1_CLK_IN
FPGA_ASAP1_DATA_IN1
FPGA_ASAP1_DATA_IN3
FPGA_ASAP1_DATA_IN5
FPGA_ASAP1_DATA_IN11
FPGA_ASAP1_VLD_IN
FPGA_ASAP1_DATA_IN15
FPGA_ASAP1_DATA_IN13
R418R417
R416
R420R419
R422R421
R424R423
TP255
R53
5
FPGA_ASAP1_VLD_OUTFPGA_ASAP1_CLK_OUT
FPGA_ASAP1_DATA_OUT[15:0]FPGA_ASAP1_REQ_OUT
23-D3,23-E1,36-D4,36-E523-D3,23-E1,36-C4,36-E5
23-D3,23-E1,36-C3,36-E5
15-B5,15-D3,36-D1,36-E115-B5,15-D3,36-C1,36-E115-B5,15-D3,36-C1,36-E115-B5,15-D3,36-C1,36-E115-B5,15-D3,36-D2,36-E115-B5,15-D3,36-C2,36-E1
15-B5,15-D3,36-D1,36-E1
J25
TP
257
TP
258
TP
259
TP
260
TP
261
TP
262
TP
263
ASAP1_TEST_OUT0ASAP1_TEST_OUT1ASAP1_TEST_OUT2ASAP1_TEST_OUT3ASAP1_TEST_OUT4ASAP1_TEST_OUT5ASAP1_TEST_OUT6ASAP1_TEST_OUT7ASAP1_TEST_OUT8
43
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36 001
ASAPV2 #1 DATA IN/OUT, CONFIG, ANALOG, TEST
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
U101 U105
U107
ASAP1_SPI_MOSI
P2V5D
FPGA_ASAP1_MISO
P3V3D
ASAP1_CFG_CLK
P2V5D
ASAP1_SPI_LOAD
P2V5D
ASAP1_SPI_CSN
P2V5D
ASAP1_RESET_COLD
P2V5D
C194 C195
C356C357
C358C359
C362C611
R40
8R
351
R35
0R
349
R30
4R
294
R84
R16
8
TP65TP230
TP229TP228TP227
TP64
U63
R16
0
C51
P2V5DP2V5D
ASAP1_RST_CNTCLKFPGA_ASAP1_RST_CNTCLK
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
21 3 4 5
A
B
C
D
E
21 3 4 5
A
B
C
D
E
C
P1CLK
P1D0P1D1
P1D10P1D11
P1D12P1D13
P1D14P1D15
P1D2P1D3
P1D4P1D5
P1D6P1D7
P1D8P1D9
P1G1 P1G2
P1G3 P1G4
P1G5 P1G6
P1G7 P1G8
P1NCLK
P2CLK
P2D0P2D1
P2D10P2D11
P2D112P2D13
P2D14P2D15
P2D2P2D3
P2D4P2D5
P2D6P2D7
P2D8P2D9
P2G1
P2G10
P2G2
P2G3 P2G4
P2G5 P2G6
P2G7 P2G8
P2G9
P2NCLK
** INPUTS **
A SOFT-TOUCH SINGLE-ENDED PROBE (E5390A)
AsAP 1 Data Input to Logic Analyzer
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
AGILENT 16902A Logic Analyzer E5390A SOFT-TOUCH CONNECTOR
FPGA_ASAP1_CLK_IN
FPGA_ASAP1_DATA_IN14
FPGA_ASAP1_DATA_IN10FPGA_ASAP1_DATA_IN8
FPGA_ASAP1_DATA_IN6FPGA_ASAP1_DATA_IN4
FPGA_ASAP1_DATA_IN2FPGA_ASAP1_DATA_IN0
FPGA_ASAP1_VLD_IN
FPGA_ASAP1_DATA_IN15FPGA_ASAP1_DATA_IN13
FPGA_ASAP1_DATA_IN11FPGA_ASAP1_DATA_IN9
FPGA_ASAP1_DATA_IN7FPGA_ASAP1_DATA_IN5
FPGA_ASAP1_DATA_IN3FPGA_ASAP1_DATA_IN1
FPGA_ASAP1_VLD_INFPGA_ASAP1_CLK_IN
FPGA_ASAP1_DATA_IN[15:0]
NC
NC
FPGA_ASAP1_DATA_IN12
23-B5,23-D3,36-C3,36-E137-B2,37-D2
J1
23-C5,23-D3,36-D3,36-E137-C4,37-D2
23-C5,23-D3,23-E3,36-D336-E1,37-C2,37-C4,37-D2
NC
NCNC
NCNC
NCNC
NC
NCNC
NCNC
NCNC
NCNC
342
JEREMY W. WEBB
MEAS_MAIN_BOARD
AGILENT 16902A LOGIC ANALYZER E5390A SOFT-TOUCH CONNECTOR
43
4-20-2009_13:35
37 001
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
A13 B10_VDDIO_00B15 B10_VDDIO_01B23 B10_VDDIO_02
C4 B10_VDDIO_03C12 B10_VDDIO_04C20 B10_VDDIO_05
D4 B10_VDDIO_06D16 B10_VDDIO_07H22 B10_VDDIO_08
K3 B10_VDDIO_09
K23 B10_VDDIO_10L3 B10_VDDIO_11M2 B10_VDDIO_12
M23 B10_VDDIO_13N21 B10_VDDIO_14
P3 B10_VDDIO_15U23 B10_VDDIO_16W1 B10_VDDIO_17W4 B10_VDDIO_18
AA6 B10_VDDIO_19
AA10 B10_VDDIO_20AA13 B10_VDDIO_21AA20 B10_VDDIO_22AA22 B10_VDDIO_23AA23 B10_VDDIO_24AB12 B10_VDDIO_25AB17 B10_VDDIO_26
AC4 B10_VDDIO_27AC7 B10_VDDIO_28
AC20 B10_VDDIO_29
B14B11_GNDIO_00D12B11_GNDIO_01D15B11_GNDIO_02E23B11_GNDIO_03F1B11_GNDIO_04F3B11_GNDIO_05G1B11_GNDIO_06J21B11_GNDIO_07K4B11_GNDIO_08L1B11_GNDIO_09
L4B11_GNDIO_10N20B11_GNDIO_11N23B11_GNDIO_12R4B11_GNDIO_13T2B11_GNDIO_14U4B11_GNDIO_15U20B11_GNDIO_16V21B11_GNDIO_17V23B11_GNDIO_18Y5B11_GNDIO_19
Y7B11_GNDIO_20Y10B11_GNDIO_21Y13B11_GNDIO_22Y16B11_GNDIO_23Y19B11_GNDIO_24AA5B11_GNDIO_25AA8B11_GNDIO_26AB15B11_GNDIO_27AB23B11_GNDIO_28
vcl-asapv2-sbga304(7 of 9)
11
11 11
11
11 11
11
11
11
11 11
11 11
11
11
11 11
11 11
11 11 11 11 11 11
11 11
11 11
10
10 10
10 10 10
10 10
10
10 10
10
10 10
10
10
10
10 10
10 10 10 10 10 10
10 10
10 10 10
A6 B8_VDDON_00B20 B8_VDDON_01C13 B8_VDDON_02
E1 B8_VDDON_03G21 B8_VDDON_04N22 B8_VDDON_05
R2B9_VDDON_06T20B9_VDDON_07V3B9_VDDON_08AA16B9_VDDON_09AB9B9_VDDON_10AB20B9_VDDON_11
vcl-asapv2-sbga304(6 of 9)
9
9
9
9
9 9
8
8
8
8
8
8
A14 B6_VDDL_00A17 B6_VDDL_01A18 B6_VDDL_02A20 B6_VDDL_03A21 B6_VDDL_04B6 B6_VDDL_05
B13 B6_VDDL_06B17 B6_VDDL_07C15 B6_VDDL_08D6 B6_VDDL_09
D7 B6_VDDL_10D19 B6_VDDL_11
F2 B6_VDDL_12G20 B6_VDDL_13J23 B6_VDDL_14M1 B6_VDDL_15
M21 B6_VDDL_16
M22B7_VDDL_17N4B7_VDDL_18P1B7_VDDL_19R3B7_VDDL_20U21B7_VDDL_21W2B7_VDDL_22Y1B7_VDDL_23Y21B7_VDDL_24AA9B7_VDDL_25AA19B7_VDDL_26
AB8B7_VDDL_27AB13B7_VDDL_28AB16B7_VDDL_29AB19B7_VDDL_30AC13B7_VDDL_31AC22B7_VDDL_32
vcl-asapv2-sbga304(5 of 9)
7
7
7
7
7
7
7 7
7 7
7 7 7 7
7 7
6 6 6 6 6
6 6 6
6
6 6 6
6
6
6
6 6
A1 B4_VDDH_00A2 B4_VDDH_01A4 B4_VDDH_02
A15 B4_VDDH_03A19 B4_VDDH_04A23 B4_VDDH_05B2 B4_VDDH_06B7 B4_VDDH_07B9 B4_VDDH_08
B18 B4_VDDH_09
B22 B4_VDDH_10C3 B4_VDDH_11C5 B4_VDDH_12C7 B4_VDDH_13C9 B4_VDDH_14
C14 B4_VDDH_15C17 B4_VDDH_16C18 B4_VDDH_17C21 B4_VDDH_18D1 B4_VDDH_19
D5 B4_VDDH_20D8 B4_VDDH_21
D10 B4_VDDH_22D14 B4_VDDH_23D17 B4_VDDH_24D18 B4_VDDH_25D20 B4_VDDH_26
E3 B4_VDDH_27
F22B5_VDDH_28G4B5_VDDH_29H4B5_VDDH_30J20B5_VDDH_31M20B5_VDDH_32P2B5_VDDH_33R20B5_VDDH_34R21B5_VDDH_35R22B5_VDDH_36R23B5_VDDH_37
V4B5_VDDH_38V20B5_VDDH_39W20B5_VDDH_40W21B5_VDDH_41Y4B5_VDDH_42Y9B5_VDDH_43Y12B5_VDDH_44Y15B5_VDDH_45AA3B5_VDDH_46AA12B5_VDDH_47
AA17B5_VDDH_48AA21B5_VDDH_49AB2B5_VDDH_50AB22B5_VDDH_51AC1B5_VDDH_52AC14B5_VDDH_53AC23B5_VDDH_54
vcl-asapv2-sbga304(4 of 9)
5
5
5
5
5
5
5 5 5 5
5 5
5 5
5 5 5 5
5 5 5 5
5 5
5 5 5
4 4 4 4 4 4
4 4 4 4 4
4 4 4 4 4 4 4 4
4 4 4 4 4 4 4 4
4
A3GND_D0A5GND_D1A7GND_D2A12GND_D3A16GND_D4A22GND_D5B1GND_D6B3GND_D7B4GND_D8B5GND_D9
B8GND_D10B10GND_D11B16GND_D12B19GND_D13B21GND_D14C1GND_D15C6GND_D16C8GND_D17C10GND_D18C16GND_D19
C19GND_D20C22GND_D21C23GND_D22D9GND_D23D21GND_D24D22GND_D25E2GND_D26F21GND_D27G2GND_D28G22GND_D29
H1GND_D30H2GND_D31H3GND_D32H23GND_D33J1GND_D34K22GND_D35P22GND_D36T3GND_D37T4GND_D38T21GND_D39
T22GND_D40U2GND_D41U3GND_D42U22GND_D43V2GND_D44V22GND_D45W3GND_D46W23GND_D47Y2GND_D48Y6GND_D49
Y8GND_D50Y18GND_D51Y22GND_D52AA2GND_D53AA4GND_D54AA15GND_D55AB1GND_D56AB3GND_D57AB4GND_D58AB21GND_D59
AC2GND_D60AC6GND_D61AC8GND_D62AC12GND_D63AC16GND_D64AC17GND_D65AC18GND_D66
vcl-asapv2-sbga304(1 of 9)
P P P P P P
P P P P P P P P P
P P P P P P P P
P P P
P
P
P P
P P P P
P
P
P
P P P P
P P P
P P
P P
P P P P P
P P P
P P P P
P P P P P P P
B12 B12_VDDOSC_00D13 B12_VDDOSC_01D23 B12_VDDOSC_02
F4 B12_VDDOSC_03AB10 B12_VDDOSC_04
AC9 B12_VDDOSC_05
K21B13_GNDOSC_00L2B13_GNDOSC_01L20B13_GNDOSC_02L23B13_GNDOSC_03M3B13_GNDOSC_04M4B13_GNDOSC_05
vcl-asapv2-sbga304(8 of 9)
13
13 13 13
13 13
12
12 12
12
12
12
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
AsAPv2 #1 Power Supply Inputs
U43
U43
U43 U43 U43 U43
VDDIO_ASAP1VDDL_ASAP1 VDDON_ASAP1 VDDON_ASAP1VDDH_ASAP1 VDDH_ASAP1 VDDL_ASAP1 VDDOSC_ASAP1
43
3-27-2009_12:24
38 001
ASAPV2 #1 POWER SUPPLY INPUTS
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
47U
2
47U
2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
42-OHM
1 2
47U
2
42-OHM
1 2
42-OHM
1 2
47U
2
42-OHM
1 2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
47U
2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
47U
2
47U
2
47U
2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
42-OHM
1 2
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
Rated @ 6A
Rated @ 6A
Rated @ 6A
Rated @ 6A
X2Y
TA
NT
TA
NT
TA
NT
TA
NT
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
0402 0402 0402 0402 0402 0402
0402
0402
0402
0402
0402
0402
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2YX2Y
X2Y
Capacitor Placement
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
Capacitor Placement(top side)
TA
NT
TA
NT
TA
NT
TA
NT
X2Y
Tantalum/O402 Via Placement
X2Y Capacitor Via Placement
(3.3V)
(2.5V)
(3.3V)(3.3V)
(bottom side)
(3.3V) (3.3V)
(3.3V)
(2.5V)
Rated @ 6A
AsAPv2 #1 Power Supply Decoupling
C23
8
C24
0
C24
1
C24
2
C23
9
C24
3
C20
9
C20
2
C23
6
C23
7
C20
8
C20
1
L40
VDDIO_ASAP1
C801
VDDOSC_ASAP1
VDDH_ASAP1
P1V3D_ASAP
C777 C776 C775 C774 C773
C383
C382
C381
C772
C771 C770C769C768C767C766
C789 C788 C787 C786 C785C784
C783
C384
C782C781C780C779C778
L41
P1V0D_ASAP
VDDL_ASAP1
C385
L42
P1V3D_ASAP
VDDON_ASAP1
P1V3D_ASAP
L43
C386
P2V5D
L44
C807 C806 C805 C804 C803
C388
C387
C802
C800C799C798C797C796
43
3-27-2009_12:24
39 001
ASAPV2 #1 POWER SUPPLY DECOUPLING
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
C606 C605 C604 C603 C597C596
C900 C899 C898 C897 C896C895
C906 C905 C904 C903 C902C901
C912 C911C910C909C908C907
C26
1
C26
0
C25
9
C25
8
C25
7
C25
6
0.1U
2
294
1
294
1
294
1
294
1
294
1
294
0.1U
2
0.1U
2
0.1U
2
0.1U
2
0.1U
2
0.1U
2
3SN74LVC1G07DBV
2
5
4
3SN74LVC1G07DBV
2
5
4
3SN74LVC1G07DBV
2
5
4
3SN74LVC1G07DBV
2
5
4
3SN74LVC1G07DBV
2
5
4
3SN74LVC1G07DBV
2
5
4
3SN74LVC1G07DBV
2
5
4
3SN74LVC1G07DBV
2
5
4
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
142-0701-231
0.0
1
30.1
1 30.1
130.1
1 30.1
1
30.1
1
30.1
1
30.1
1
30.1
1 30.1
1
49.9
1
1
10
PBC05DAAN
VERT
121K
1
0.0
1
0.1U
2
0.1U
2
1
294
1
402
1
294
Y11 B2_RESET_COLDAC11 B2_CFG_CLKAB11 B2_CFG_VALIDAB7 B2_SPI_CLKAB5 B2_SPI_SELAB6 B2_SPI_LOADAA7 B2_SPI_MISOAC5 B2_SPI_MOSI
AB14B3_TEST_OUT0AA14B3_TEST_OUT1Y14B3_TEST_OUT2AC15B3_TEST_OUT3Y17B3_TEST_OUT4AB18B3_TEST_OUT5AA18B3_TEST_OUT6AC19B3_TEST_OUT7AC21B3_TEST_OUT8
vcl-asapv2-sbga304(3 of 9)
3
3
3
3
3
3
3
3 3
2
2
222 2
2
2
A8 B14_ANAG1A9 B14_ANAG2
A10 B14_ANAG3A11 B14_ANAG4
B11B15_TEMP_DIODEC11B15_ANAREXTD11B15_SPECIALGNDJ3B15_NC_00J4B15_NC_01AA11B15_RESET_COUNTCLK
vcl-asapv2-sbga304(9 of 9)
15
15
15
15 15
15
14 14 14 14
N2 B0_IN_CLKC2 B0_IN_DATA0D3 B0_IN_DATA1D2 B0_IN_DATA2E4 B0_IN_DATA3G3 B0_IN_DATA4J2 B0_IN_DATA5K1 B0_IN_DATA6K2 B0_IN_DATA7N3 B0_IN_DATA8
R1 B0_IN_DATA9T1 B0_IN_DATA10U1 B0_IN_DATA11V1 B0_IN_DATA12
AA1 B0_IN_DATA13Y3 B0_IN_DATA14
AC3 B0_IN_DATA15P4 B0_IN_REQUESTN1 B0_IN_VALID
AC10 B0_EXTERNAL_CLK
K20B1_OUT_CLKE20B1_OUT_DATA0E21B1_OUT_DATA1E22B1_OUT_DATA2F20B1_OUT_DATA3H20B1_OUT_DATA4H21B1_OUT_DATA5F23B1_OUT_DATA6G23B1_OUT_DATA7J22B1_OUT_DATA8
P21B1_OUT_DATA9P20B1_OUT_DATA10P23B1_OUT_DATA11T23B1_OUT_DATA12W22B1_OUT_DATA13Y23B1_OUT_DATA14Y20B1_OUT_DATA15L22B1_OUT_REQUESTL21B1_OUT_VALID
vcl-asapv2-sbga304(2 of 9)
1
1 1 1
1
1 1
1
1
1
11 1
1
1
11
11
0
0
00
0
0
0
0 0
0
0
0
0
0
0
0
0
0
0
0
3SN74LVC1G07DBV
2
5
4
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
A
** INPUTS **** OUTPUTS **AsAPv2 #2 Data In/Out, Config, Analog, Test
AsAP 2 Data Output
AsAP 2 Data Input
AsAP 2 Data Output
AsAP 2 Config Output
AsAP 2 Data Input
AsAP Main Data Input and Output
AsAP Configuration and Test Port AsAP Analog and Miscellaneous I/OPlace 30.1 Ohm Series Resistor on AsAP SPI_MISO near AsAP IC.
Place 30.1 Ohm Series Resistors on all other SPI, CFG, and Reset Cold signals near FPGA Outputs
B
DC
AsAP 2 Config Input
AsAP Config Level Translate
U64
ASAP2_RST_CNTCLKFPGA_ASAP2_RST_CNTCLK
U44
U44U44
TP225TP246
TP249TP248TP247
R41
5R
95
R40
9
P2V5DP2V5D
P2V5DP2V5D
P2V5D
C614
P2V5D
P2V5D
C612
P2V5D
FPGA_ASAP2_CFG_VALID
ASAP2_CFG_CLK
ASAP2_SPI_CLKASAP2_CFG_VALID
ASAP2_SPI_LOAD
ASAP2_SPI_MOSI
ASAP2_SPI_CSN
ASAP2_SPI_MISO
ASAP2_SPI_CSN
ASAP2_RST_CNTCLK
TP
275
ASAP2_ANLG1ASAP2_ANLG2ASAP2_ANLG3ASAP2_ANLG4
FPGA_ASAP2_RST_CNTCLK15-A5,15-B3,40-C2,40-E1
FPGA_ASAP2_MISO15-C1,15-C3,40-C2,40-E5
FPGA_ASAP2_MOSIFPGA_ASAP2_SPI_LOADFPGA_ASAP2_SPI_CSNFPGA_ASAP2_SPI_CLKFPGA_ASAP2_CFG_VALIDFPGA_ASAP2_CFG_CLKFPGA_ASAP2_RESET_COLD
24-D1,24-E5,40-D4,40-E1
24-D1,24-E5,40-D3,40-E141-C2,41-C4,41-E1,41-E224-D1,24-E5,40-D3,40-E1
41-C4,41-D1,41-D224-D1,24-E5,40-C3,40-E141-C2,41-D1,41-D2
24-C1,24-D1,24-E1,40-D440-E5
FPGA_ASAP2_REQ_IN
R53
6
TP265R368
NCASAP2_TEST0
ASAP2_TEST2
ASAP2_TEST4ASAP2_TEST6
ASAP2_TEST8ASAP2_TEST7
ASAP2_TEST5
J63
ASAP2_TEST3
ASAP2_TEST1
ASAP2_TEST8ASAP2_TEST7ASAP2_TEST6ASAP2_TEST5ASAP2_TEST4ASAP2_TEST3ASAP2_TEST2ASAP2_TEST1ASAP2_TEST0
ASAP2_TEST_OUT6ASAP2_TEST_OUT5
ASAP2_TEST_OUT0
FPGA_ASAP2_REQ_OUTFPGA_ASAP2_VLD_OUT
ASAP2_EXT_CLK_IN
FPGA_ASAP2_CLK_OUTFPGA_ASAP2_DATA_OUT0FPGA_ASAP2_DATA_OUT1FPGA_ASAP2_DATA_OUT2FPGA_ASAP2_DATA_OUT3FPGA_ASAP2_DATA_OUT4FPGA_ASAP2_DATA_OUT5FPGA_ASAP2_DATA_OUT6FPGA_ASAP2_DATA_OUT7FPGA_ASAP2_DATA_OUT8
FPGA_ASAP2_DATA_OUT9FPGA_ASAP2_DATA_OUT10FPGA_ASAP2_DATA_OUT11FPGA_ASAP2_DATA_OUT12FPGA_ASAP2_DATA_OUT13FPGA_ASAP2_DATA_OUT14FPGA_ASAP2_DATA_OUT15
R93
R474R473ASAP2_TEST_OUT2
ASAP2_TEST_OUT1R472
ASAP2_TEST_OUT3ASAP2_TEST_OUT4 R476
R475
R478R477
R480R479ASAP2_TEST_OUT8
ASAP2_TEST_OUT7
TP266
R53
7
FPGA_ASAP2_VLD_OUTFPGA_ASAP2_CLK_OUT
FPGA_ASAP2_DATA_OUT[15:0]
FPGA_ASAP2_VLD_INFPGA_ASAP2_CLK_IN
FPGA_ASAP2_DATA_IN[15:0]
FPGA_ASAP2_REQ_OUT
24-D1,24-E1,40-D4,40-E524-D1,24-E1,40-C4,40-E5
24-D1,24-E1,40-D3,40-E5
15-B5,15-C3,40-D1,40-E115-B3,15-B5,40-C1,40-E115-A5,15-B3,40-C1,40-E115-A5,15-C3,40-C1,40-E115-A5,15-C3,40-D2,40-E115-A5,15-C3,40-C2,40-E1
14-D4,14-E5,40-D1,40-E1
J30
TP
274
TP
273
TP
272
TP
271
TP
270
TP
269
TP
268
TP
267
ASAP2_RESET_COLD
43
4-20-2009_13:35
40 001
ASAPV2 #2 DATA IN/OUT, CONFIG, ANALOG, TEST
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
P2V5D
P2V5D
U116
U115
U114
U113
U112
U111 U110
U109
P2V5D
P3V3D
P2V5D P2V5D
P2V5DP2V5D
ASAP2_CFG_VALID
ASAP2_SPI_CLK FPGA_ASAP2_MOSI
ASAP2_SPI_MISO
FPGA_ASAP2_SPI_LOAD
FPGA_ASAP2_SPI_CSNFPGA_ASAP2_RESET_COLD
FPGA_ASAP2_CFG_CLK
FPGA_ASAP2_SPI_CLK ASAP2_SPI_MOSI
FPGA_ASAP2_MISO
ASAP2_CFG_CLK ASAP2_SPI_LOAD
ASAP2_RESET_COLD
C613
C615
C617C620
C644
C645
R41
0R
411
R41
2R
413
R41
4
TP226
ASAP2_EXT_CLK_INFPGA_ASAP2_VLD_INFPGA_ASAP2_REQ_INFPGA_ASAP2_DATA_IN15FPGA_ASAP2_DATA_IN14FPGA_ASAP2_DATA_IN13FPGA_ASAP2_DATA_IN12FPGA_ASAP2_DATA_IN11FPGA_ASAP2_DATA_IN10FPGA_ASAP2_DATA_IN9
FPGA_ASAP2_DATA_IN8FPGA_ASAP2_DATA_IN7FPGA_ASAP2_DATA_IN6FPGA_ASAP2_DATA_IN5FPGA_ASAP2_DATA_IN4FPGA_ASAP2_DATA_IN3FPGA_ASAP2_DATA_IN2FPGA_ASAP2_DATA_IN1FPGA_ASAP2_DATA_IN0FPGA_ASAP2_CLK_IN
R16
1
C52
P2V5DP2V5D
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
21 3 4 5
A
B
C
D
E
21 3 4 5
A
B
C
D
E
C
P1CLK
P1D0P1D1
P1D10P1D11
P1D12P1D13
P1D14P1D15
P1D2P1D3
P1D4P1D5
P1D6P1D7
P1D8P1D9
P1G1 P1G2
P1G3 P1G4
P1G5 P1G6
P1G7 P1G8
P1NCLK
P2CLK
P2D0P2D1
P2D10P2D11
P2D112P2D13
P2D14P2D15
P2D2P2D3
P2D4P2D5
P2D6P2D7
P2D8P2D9
P2G1
P2G10
P2G2
P2G3 P2G4
P2G5 P2G6
P2G7 P2G8
P2G9
P2NCLK
A SOFT-TOUCH SINGLE-ENDED PROBE (E5390A)
** INPUTS **
AsAP 2 Data Input to Logic Analyzer
AGILENT 16902A Logic Analyzer E5390A SOFT-TOUCH CONNECTOR
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
FPGA_ASAP2_DATA_IN12
FPGA_ASAP2_DATA_IN10
FPGA_ASAP2_DATA_IN4
FPGA_ASAP2_DATA_IN0
FPGA_ASAP2_VLD_IN
FPGA_ASAP2_DATA_IN15
FPGA_ASAP2_DATA_IN11FPGA_ASAP2_DATA_IN9
FPGA_ASAP2_DATA_IN7FPGA_ASAP2_DATA_IN5
FPGA_ASAP2_DATA_IN3FPGA_ASAP2_DATA_IN1
FPGA_ASAP2_VLD_IN
FPGA_ASAP2_DATA_IN[15:0]
FPGA_ASAP2_CLK_IN
24-D1,24-E5,40-C3,40-E141-C2,41-D2
24-D1,24-E5,40-D3,40-E141-C4,41-D2
24-D1,24-E5,40-D3,40-E141-C2,41-C4,41-E2
J2
NC
NC FPGA_ASAP2_CLK_IN
FPGA_ASAP2_DATA_IN13FPGA_ASAP2_DATA_IN14
FPGA_ASAP2_DATA_IN8
FPGA_ASAP2_DATA_IN6
FPGA_ASAP2_DATA_IN2
NC
NCNC
NCNC
NCNC
NC
NCNC
NCNC
NCNC
NCNC
342
JEREMY W. WEBB
MEAS_MAIN_BOARD
AGILENT 16902A LOGIC ANALYZER E5390A SOFT-TOUCH CONNECTOR
43
4-20-2009_13:35
41 001
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
A3GND_D0A5GND_D1A7GND_D2A12GND_D3A16GND_D4A22GND_D5B1GND_D6B3GND_D7B4GND_D8B5GND_D9
B8GND_D10B10GND_D11B16GND_D12B19GND_D13B21GND_D14C1GND_D15C6GND_D16C8GND_D17C10GND_D18C16GND_D19
C19GND_D20C22GND_D21C23GND_D22D9GND_D23D21GND_D24D22GND_D25E2GND_D26F21GND_D27G2GND_D28G22GND_D29
H1GND_D30H2GND_D31H3GND_D32H23GND_D33J1GND_D34K22GND_D35P22GND_D36T3GND_D37T4GND_D38T21GND_D39
T22GND_D40U2GND_D41U3GND_D42U22GND_D43V2GND_D44V22GND_D45W3GND_D46W23GND_D47Y2GND_D48Y6GND_D49
Y8GND_D50Y18GND_D51Y22GND_D52AA2GND_D53AA4GND_D54AA15GND_D55AB1GND_D56AB3GND_D57AB4GND_D58AB21GND_D59
AC2GND_D60AC6GND_D61AC8GND_D62AC12GND_D63AC16GND_D64AC17GND_D65AC18GND_D66
vcl-asapv2-sbga304(1 of 9)
P P P P P P
P P P P P P P P P
P P P P P P P P
P P P
P
P
P P
P P P P
P
P
P
P P P P
P P P
P P
P P
P P P P P
P P P
P P P P
P P P P P P P
A1 B4_VDDH_00A2 B4_VDDH_01A4 B4_VDDH_02
A15 B4_VDDH_03A19 B4_VDDH_04A23 B4_VDDH_05B2 B4_VDDH_06B7 B4_VDDH_07B9 B4_VDDH_08
B18 B4_VDDH_09
B22 B4_VDDH_10C3 B4_VDDH_11C5 B4_VDDH_12C7 B4_VDDH_13C9 B4_VDDH_14
C14 B4_VDDH_15C17 B4_VDDH_16C18 B4_VDDH_17C21 B4_VDDH_18D1 B4_VDDH_19
D5 B4_VDDH_20D8 B4_VDDH_21
D10 B4_VDDH_22D14 B4_VDDH_23D17 B4_VDDH_24D18 B4_VDDH_25D20 B4_VDDH_26
E3 B4_VDDH_27
F22B5_VDDH_28G4B5_VDDH_29H4B5_VDDH_30J20B5_VDDH_31M20B5_VDDH_32P2B5_VDDH_33R20B5_VDDH_34R21B5_VDDH_35R22B5_VDDH_36R23B5_VDDH_37
V4B5_VDDH_38V20B5_VDDH_39W20B5_VDDH_40W21B5_VDDH_41Y4B5_VDDH_42Y9B5_VDDH_43Y12B5_VDDH_44Y15B5_VDDH_45AA3B5_VDDH_46AA12B5_VDDH_47
AA17B5_VDDH_48AA21B5_VDDH_49AB2B5_VDDH_50AB22B5_VDDH_51AC1B5_VDDH_52AC14B5_VDDH_53AC23B5_VDDH_54
vcl-asapv2-sbga304(4 of 9)
5
5
5
5
5
5
5 5 5 5
5 5
5 5
5 5 5 5
5 5 5 5
5 5
5 5 5
4 4 4 4 4 4
4 4 4 4 4
4 4 4 4 4 4 4 4
4 4 4 4 4 4 4 4
4
A14 B6_VDDL_00A17 B6_VDDL_01A18 B6_VDDL_02A20 B6_VDDL_03A21 B6_VDDL_04B6 B6_VDDL_05
B13 B6_VDDL_06B17 B6_VDDL_07C15 B6_VDDL_08D6 B6_VDDL_09
D7 B6_VDDL_10D19 B6_VDDL_11
F2 B6_VDDL_12G20 B6_VDDL_13J23 B6_VDDL_14M1 B6_VDDL_15
M21 B6_VDDL_16
M22B7_VDDL_17N4B7_VDDL_18P1B7_VDDL_19R3B7_VDDL_20U21B7_VDDL_21W2B7_VDDL_22Y1B7_VDDL_23Y21B7_VDDL_24AA9B7_VDDL_25AA19B7_VDDL_26
AB8B7_VDDL_27AB13B7_VDDL_28AB16B7_VDDL_29AB19B7_VDDL_30AC13B7_VDDL_31AC22B7_VDDL_32
vcl-asapv2-sbga304(5 of 9)
7
7
7
7
7
7
7 7
7 7
7 7 7 7
7 7
6 6 6 6 6
6 6 6
6
6 6 6
6
6
6
6 6
A6 B8_VDDON_00B20 B8_VDDON_01C13 B8_VDDON_02
E1 B8_VDDON_03G21 B8_VDDON_04N22 B8_VDDON_05
R2B9_VDDON_06T20B9_VDDON_07V3B9_VDDON_08AA16B9_VDDON_09AB9B9_VDDON_10AB20B9_VDDON_11
vcl-asapv2-sbga304(6 of 9)
9
9
9
9
9 9
8
8
8
8
8
8
B12 B12_VDDOSC_00D13 B12_VDDOSC_01D23 B12_VDDOSC_02
F4 B12_VDDOSC_03AB10 B12_VDDOSC_04
AC9 B12_VDDOSC_05
K21B13_GNDOSC_00L2B13_GNDOSC_01L20B13_GNDOSC_02L23B13_GNDOSC_03M3B13_GNDOSC_04M4B13_GNDOSC_05
vcl-asapv2-sbga304(8 of 9)
13
13 13 13
13 13
12
12 12
12
12
12
A13 B10_VDDIO_00B15 B10_VDDIO_01B23 B10_VDDIO_02
C4 B10_VDDIO_03C12 B10_VDDIO_04C20 B10_VDDIO_05
D4 B10_VDDIO_06D16 B10_VDDIO_07H22 B10_VDDIO_08
K3 B10_VDDIO_09
K23 B10_VDDIO_10L3 B10_VDDIO_11M2 B10_VDDIO_12
M23 B10_VDDIO_13N21 B10_VDDIO_14
P3 B10_VDDIO_15U23 B10_VDDIO_16W1 B10_VDDIO_17W4 B10_VDDIO_18
AA6 B10_VDDIO_19
AA10 B10_VDDIO_20AA13 B10_VDDIO_21AA20 B10_VDDIO_22AA22 B10_VDDIO_23AA23 B10_VDDIO_24AB12 B10_VDDIO_25AB17 B10_VDDIO_26
AC4 B10_VDDIO_27AC7 B10_VDDIO_28
AC20 B10_VDDIO_29
B14B11_GNDIO_00D12B11_GNDIO_01D15B11_GNDIO_02E23B11_GNDIO_03F1B11_GNDIO_04F3B11_GNDIO_05G1B11_GNDIO_06J21B11_GNDIO_07K4B11_GNDIO_08L1B11_GNDIO_09
L4B11_GNDIO_10N20B11_GNDIO_11N23B11_GNDIO_12R4B11_GNDIO_13T2B11_GNDIO_14U4B11_GNDIO_15U20B11_GNDIO_16V21B11_GNDIO_17V23B11_GNDIO_18Y5B11_GNDIO_19
Y7B11_GNDIO_20Y10B11_GNDIO_21Y13B11_GNDIO_22Y16B11_GNDIO_23Y19B11_GNDIO_24AA5B11_GNDIO_25AA8B11_GNDIO_26AB15B11_GNDIO_27AB23B11_GNDIO_28
vcl-asapv2-sbga304(7 of 9)
11
11 11
11
11 11
11
11
11
11 11
11 11
11
11
11 11
11 11
11 11 11 11 11 11
11 11
11 11
10
10 10
10 10 10
10 10
10
10 10
10
10 10
10
10
10
10 10
10 10 10 10 10 10
10 10
10 10 10
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
AsAPv2 #2 Power Supply Inputs
U44U44
U44U44U44
U44
VDDIO_ASAP2VDDL_ASAP2 VDDON_ASAP2 VDDON_ASAP2VDDH_ASAP2 VDDH_ASAP2 VDDL_ASAP2 VDDOSC_ASAP2
43
3-27-2009_12:24
42 001
ASAPV2 #2 POWER SUPPLY INPUTS
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
Date:
Sheet of
Date:
Created by:
Size: REV:PCB NO:
Modified by:
File:
Title:
541 2 3
B
A
C
D
E
541 2 3
A
B
C
D
E
E
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
47U
2
47U
2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
42-OHM
1 2
47U
2
42-OHM
1 2
42-OHM
1 2
47U
2
42-OHM
1 2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
47U
2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
47U
2
47U
2
47U
2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
42-OHM
1 2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1UFA B
G1 G2
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
0.1U2
UC Davis Confidential Copyright © 2008 VLSI Computation Lab
Rated @ 6A
Rated @ 6A
Rated @ 6A
Rated @ 6A
X2Y
TA
NT
TA
NT
TA
NT
TA
NT
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
0402 0402 0402 0402 0402 0402
0402
0402
0402
0402
0402
0402
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2YX2Y
X2Y
Capacitor Placement
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
X2Y
Capacitor Placement(top side)
TA
NT
TA
NT
TA
NT
TA
NT
X2Y
Tantalum/O402 Via Placement
X2Y Capacitor Via Placement
(3.3V)
(2.5V)
(3.3V)(3.3V)
(bottom side)
(3.3V) (3.3V)
(3.3V)
(2.5V)
Rated @ 6A
AsAPv2 #2 Power Supply Decoupling
C25
5
C25
4
C25
3
C25
2
C25
1
C25
0
C925
C814
C844
VDDIO_ASAP2
VDDOSC_ASAP2
VDDH_ASAP2
P1V3D_ASAP
L45
C819 C818 C817 C816 C815
C391
C390
C389
C813 C812C811C810C809C808
C831 C830 C829 C828 C827C826
C825
C392
C824C823C822C821C820
L46
P1V0D_ASAP
VDDL_ASAP2
C393
L47
P1V3D_ASAP
VDDON_ASAP2
P1V3D_ASAP
L48
C394
P2V5D
L49
C849 C848 C847 C846 C845
C396
C395
C843 C842C841C840C839C838
43
3-27-2009_12:24
43 001
ASAPV2 #2 POWER SUPPLY DECOUPLING
MEAS_MAIN_BOARD
JEREMY W. WEBB
342
C924C923C922C921C920C919
C930 C929 C928 C927 C926
C936 C935 C934 C933 C932C931
C942C941C940C939C938C937
C24
9
C24
8
C24
7
C24
6
C24
5
C24
4
C26
7
C26
6
C26
5
C26
4
C26
3
C26
2
![A Continuous-Flow Mixed-Radix Dynamically-Configurable FFT ...vcl.ece.ucdavis.edu/pubs/theses/2007-3/toney_fft_rotated.pdf · 600 nW [13]. FFT sizes capable of being performed range](https://static.fdocuments.net/doc/165x107/5e906b2509823070b129a791/a-continuous-flow-mixed-radix-dynamically-conigurable-fft-vclece-600-nw-13.jpg)
