I

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APPLICATION NOTE

A NEW INTEGRATED CIRCUIT FORCURRENT MODE CONTROL

AbstractThe inherent advantages of current-mode control over conventional PWM approaches to switching powerconverters read like a wish list from a frustrated power supply design engineer. Features such as automatic feedforward, automatic symmetry correction, inherent current limiting, simple loop compensation, enhanced loadresponse, and the capability for parallel operation all are characteristics of current-mode conversion. This paperintroduces the first control integrated circuit specifically designed for this topology, defines its operation anddescribes practical examples illustrating its use and benefits.

1.0 IntroductionOver the past several years an increased interest incurrent-mode control of switching inverters hassurfaced in the literature. Originally invented in thelate 1960s this scheme was not publicly reporteduntil 1977(1) and has seen rapid development bymany authors to date.(2-6) In short, current-modecontrol uses an inner or secondary loop to directlycontrol peak inductor current with the error signalrather than controlling duty ratio of the pulse widthmodulator as in conventional converters. Practi-cally, this means that instead of comparing the errorvoltage to a voltage ramp, it is compared to ananalogue of the inductor current forcing the peakcurrent to follow the error voltage.

FIGURE 1. A FIXED FREQUENCY CURRENT-MODE CONTROLLEDREGULATOR.

Figure 1 illustrates a simplified block diagram of afixed frequency buck regulator employing current-mode control. As shown, the error signal, V,, iscontrolling peak switch current which, to a goodapproximation, is proportional to average inductorcurrent. Since the average inductor current canchange only if the error signal changes, the inductormay be replaced by a current source, and the orderof the system reduced by one. This results in anumber of performance advantages includingimproved transient response, a simpler, more easilydesigned control loop, and line regulation compara-ble to conventional feed-forward schemes. Peakcurrent sensing will automatically provide fluxbalancing thereby eliminating the need for complexbalance schemes in push-pull systems. Addition-ally, by simply limiting the peak swing of the errorvoltage Ve, instantaneous peak current limiting isaccomplished. Lastly, by feeding identical powerstages with a common error signal, outputs may beparalleled while maintaining equal current sharing.

Although the advantages of current-mode controlare abundant, wide acceptance of this techniquehas been hampered by a lack of suitable integratedcircuits to perform the associated control functions.This paper introduces a new integrated circuitdesigned specifically for control of current-modeconverters. Circuit function and features are des-cribed in detail, and a comparative design exampleis used to illustrate the numerous advantages of thisapproach.

UC1846 Chip ArchitectureIn addition to all the functions required of conven-tional PWM controllers, a current-mode controller t93-1

reference recalculator

APPLICATION NOTE U-93

FIGURE 2. UC1846 BLOCK DIAGRAM

must be able to sense switch or inductor currentand compare it on a pulse-by-pulse basis with theoutput of the error amplifier. As may be seen in theblock diagram of Figure 2, this is accomplished inthe UC1846 by using a differential current senseamplifier with a fixed gain of 3. The amplifier allowssensing of low level voltages while maintaining highnoise immunity. A list of other features, while notunique to current-mode conversion, demonstratesthe advanced, state-of-the-art architecture of theUC1846:

A ± 1%, 5.1V trimmed bandgap reference usedboth as an external voltage reference and inter-nal regulated power source to drive low levelcircuitry.

A fixed frequency sawtooth oscillator with varia-ble deadtime control and external synchroniza-tion capability. Circuitry features an all NPNdesign capable of producing low distortionwaveforms well in excess of 1 MHz.

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An error amplifier with common mode range fromground to V,=-2V.

Current limiting through clamping of the errorsignal at a user-programmed level.

A shutdown function with built in 350mV thresh-old. May be used in either a latching, or non-latching mode. Also capable of initiating a“hiccup” mode of operation.

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Under-voltage lockout with hysteresis to guaran-tee outputs will stay “off” until reference is inregulation.

Double pulse suppression logic to eliminate thepossibility of consecutively pulsing either output.

Totem pole output stages capable of sinking orsourcing 100mA continuous, 400mA peakcurrents.

These various features, along with their interrela-tionships and applications to switched-mode regu-lators, will be further discussed in the followingsections.

UC1846 Functional Description3.1 Current Sense AmplifierThe current sense amplifier may be used in a var-iety of ways to sense peak switch current for com-parison with an error voltage. Referring to Figure 2,maximum swing on the inverting input of the PWMcomparator is limited to approximately 3.5V by theinternal regulated supply. Accordingly, for a fixedgain of 3, maximum differential voltages must bekept below 1.2V at the current sense inputs. Figure 3depicts several methods of configuring senseschemes. Direct resistive sensing is simplest, how-ever, a lower peak voltage may be required to min-imize power loss in the sense resistor. Transformercoupling can provide isolation and increase effi-

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APPLICATION NOTE U-93

ciency at the cost of added complexity. Regardlessof scheme, the largest sense voltage consistentwith low power losses should be chosen for noiseimmunity. Typically, this will range from severalhundred millivolts in some resistive sense circuits tothe maximum of 1.2V in transformer coupledcircuits.

A.) RESISTIVE SENSING WITH GROUND REFERENCE

OUTPUT RSENSE

B.) RESISTIVE SENSING ABOVE GROUND

CURRENTXFORMER

C.) ISOLATED CURRENT SENSING

FIGURE 3. VARIOUS CURRENT SENSE SCHEMES

In addition, caution should be exercised when usinga configuration that senses switch current (Figure3A) instead of inductor current (Figure 3B). As theswitch is turned on, a large instantaneous currentspike can be generated in the sense resistor as thecollector capacitance of the switch is discharged.This spike will often be of sufficient magnitude andduration to trip the current sense latch and result inerratic operation of the PWM circuit, particularly atlower duty cycles. A small RC filter (Figure 4) in

series with the input is generally all that is requiredto reduce the spike to an acceptable level.

FIGURE 4. RC FILTER FOR REDUCING SWITCH TRANSIENTS

3.2 OscillatorAlthough many data sheets tout 300 to 500kHzoperation, virtually all PWM control chips suffer fromboth poor temperature characteristics and wave-form distortions at these frequencies. Practicalusage is generally limited to the 100 to 200kHzrange. This is a direct consequence of having slow(ft = 2MHz) PNP transistors in the oscillator signalpath. By implementing the oscillator using all NPNtransistors, the UC1846 achieves excellent temper-ature stabillity and waveform clarity at frequenciesin excess of 1MHz.

OUTPUT DEADTIME (rd)

FIGURE 5. OSCILLATOR CIRCUIT

Referring to Figure 5, an external resistor RT is usedto generate a constant current into a capacitor CT to

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APPLICATION NOTE U-93

produce a linear sawtooth waveform. Oscillator fre-quency may be approximated by selecting RT andCT such that:

2.2f -OS’ = RT CT (1)

Where RT can range from 1K to 500K and CT isabove 100pF. For quick reference a plot of fre-quency versus RT and CT is given in Figure 6.

FREQUENCY - KILOHERTZ

FIGURE 6. OSCILLATOR FREQUENCY AS A FUNCTION OFRr AND Cr

Again referring to Figure 5, the oscillator generatesan internal clock pulse used, among other things, toblank both outputs and prevent simultaneous crossconduction during switching transitions. This output“deadtime” is controlled by the oscillator fall time.Fall time, in turn, is controlled by CT according to theformula:

For large values of RT:

(2)

Td = 145 CT (3)

A plot of output deadtime versus CT for two values ofRT is given in Figure 7.

Although timing capacitors as small as 100pF canbe used successfully in low noise environments, it isgenerally recommended that CT be kept above1000pF to minimize noise effects on the oscillatorfrequency (see Section 4.0).

Synchronization of one or more devices to either anexternal time base or another UC1846 is accomp-lished via the bi-directional SYNC pin. To synchron-ize devices, first, CT must be grounded to disable theinternal oscillator on all slaved devices. Second, anexternal synchronization pulse must be applied tothe SYNC terminal. This pulse can come directlyfrom the SYNC terminal of a master UC1846 or,alternatively, from an external time base as shownin Figure 8.

OUTPUT DEAD TIME, 7, - MICROSECONDS

FIGURE 7. OUTPUT DEADTIME AS A FUNCTION OF TIMINGCAPACITOR CT

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FIGURE 8. SYNCHRONIZING THE 1846 TO AN EXTERNALTIME BASE

3.3 Current LimitOne of the most attractive features of a current-mode converter is its ability to limit peak switchcurrents on a pulse-by-pulse basis by simply limit-ing the error voltage to a maximum value. Referringto Figure 9, peak current limiting in the UC1846 isaccomplished using a divider network, RI and RP, toset a pre-determined voltage at pin 1.

FIGURE 9. PEAK CURRENT LIMIT SET UP

APPLICATION NOTE U-93

This voltage, in conjunction with Q1, acts to clampthe output of the error amplifier at a maximum value.Since the base emitter drop of QI and the forwarddrop of diode DI very nearly cancel, the negativeinput of the comparator will be clamped at the valueVPIN 1 -0.5V. Following this through to the input ofthe current sense amplifier yields:

(4)

Where Vcs is the differential input voltage of thecurrent sense amplifier. Using this relationship, avalue for maximum switch current in terms of exter-nal programming resistors can be derived, resultingin:

(5)

While still on the subject of resistor selection, itshould be pointed out that RI also supplies holdingcurrent for the shutdown circuit, and thereforeshould be selected prior to selecting RP as outlinedin the next section.

One last word on the current limit circuit. As may beseen from equation 5, any signal less than 0.5V atthe current limit input will guarantee both outputs tobe off, making pin 1 a convenient point for bothshutting down and slow starting the PWM circuit.For example, both the under-voltage lockout andshutdown functions are connected internally to thispoint. If a capacitor is used to hold pin 1 low (Figure10) then as the input voltage increases above theunder-voltage lockout level, the capacitor willcharge and gradually increase the PWM duty cycleto its operating point. In a similar manner if theshutdown amplifier is pulsed, the shutdown SCR willbe fired and the capacitor discharged, guarantee-ing a shutdown and soft restart cycle independentof input pulse width.

FIGURE 10. USING UNDER-VOLTAGE LOCKOUT AND SHUTDOWNTO INITIATE A SLOW START.

3.4 ShutdownThe shutdown circuit, shown in Figure 11, wasdesigned to provide a fast acting general purposeshutdown port for use in implementing both protec-tion circuitry and remote shutdown functions. Thecircuit may be divided into an input section consist-ing of a comparator with a 350mV temperaturecompensated offset, and an output section consist-ing of a three transistor latch. Shutdown is accomp-lished by applying a signal greater than 350mV topin 16, causing the output latch to fire, and settingthe PWM latch to provide an immediate signal to theoutputs. At this point, several things can happen. Q,requires a minimum holding current, IH, of approxi-mately 1.5mA to remain in the latched state. There-fore, if RI is chosen greater than 5kS2, QI willdischarge any capacitance, CS, on pin 1 to groundand commutate the output latch, allowing CS torecharge. If RI is chosen less than 2.5kR, Q1 willdischarge CS and remain in the latched state untilpower is externally cycled off. In either case, CS isrequired only if a soft-start or soft-restart function isdesired.

FIGURE 11. SHUTDOWN CIRCUITRY

For example, the shutdown circuit of Figure 12,operating in a nonlatched mode, will protect thesupply from overcurrent fault conditions. Manytimes, if the output of a supply is shorted, circulatingcurrents in the output inductor will build to danger-ous levels. Pulse-by-pulse current limiting with itsinherent time delay, will in general not be able tolimit these currents to acceptable levels. Figure 12details a circuit which will provide shutdown andsoft-restart if the overcurrent threshold set by Rsand Rd is exceeded. This level should be greaterthan the peak current limit value determined by RIand RP (see equation 5). Sometimes called a “hic-cup mode”, this overcurrent function will limit bothpower and peak current in the output stages untilthe fault is removed.

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APPLICATION NOTE

FIGURE 12. OVER CURRENT SENSING WITH THE SHUTDOWNCIRCUIT PRODUCES A SHUTDOWN - SOFT RESTARTCYCLE TO PROTECT OUTPUT DRIVERS

4.0 Noise Immunity

5.0

As in all PWM circuits, some simple precautionsshould be observed to prevent switching noise fromprematurely triggering the oscillator as itapproaches its upper threshold. This is most evi-dent when large capacitive loads - such as thegates of power FETS - are directly driven fromoutputs A and B. As the duty cycle approaches100%, the current spike associated with this outputcapacitance can cause the oscillator to prema-turely trigger with a resulting shift upward in fre-quency. By separating high current ground pathsfrom low level analog grounds, using CT valuesgreater than 1000pF grounded directly to pin 12,and decoupling both VIN and VREF with good qualitybypass capacitors, noise problems can be avoided.

Comparative Design ExampleTo more vividly illustrate the advantages of current-mode control, a relatively simple push-pull forwardconverter was designed using two interchangeablecontrol sections, as shown in Figure 13. The controlmodules consist of (a) a UC1846 current-modecontroller with associated circuitry, and (b) a con-ventional UC1525A PWM controller with its supportcircuitry. Loop compensation of the UC1525A wasimplemented by placing a zero in the feedback loopto cancel one of the poles in the output stage,resulting in a unity gain bandwidth of approximately3kHz - a commonly used technique. Compensat-ing the current-mode converter requires somewhatof a different approach. Since the output stage con-tains only a single pole, in theory closing the loopwill produce a stable system with no additionalcompensation. In practice, however, it has beenshown that subharmonic oscillation will result fromexcess gain at half the switching frequency”!Therefore, a pole-zero combination has been

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placed in the feedback loop to reduce high fre-quency gain and allow the output capacitor (lowESR) to roll off loop gain to OdB at 3kHz.

While not demonstrated in Figure 13, fixed fre-quency current-mode converters are known to beunstable above 50% duty cycle without some formof slope compensation(4? By injecting a small cur-rent from the sawtooth oscillator into the positiveterminal of the current sense amplifier, slope com-pensation is accomplished, and the converter canbe operated in excess of 50% duty cycle. An alter-nate, but just as effective, scheme would be to injectthe signal into the negative terminal of the erroramplifier.

As may be seen, a similar parts count for bothsupplies was encountered. Topologically, using theUC1525A shutdown terminal provided only a crudecurrent limit in contrast to the UC1846. Further-more, internal double pulse suppression circuitry ofthe UC1846 gave an added level of protectionagainst core saturation - important if your regula-tor is prone to subharmonic oscillations. Since bothregulators were over-designed to withstand a shortcircuit on the output with resultant high peak cur-rents, the shutdown-restart mode of the UC1846was not used.

It should be pointed out at this time that one of themain features of a current-mode converter of thistype is its ability to be paralleled with similar units.By disabling the oscillator and error amplifiers (CTgrounded, +E/A to VREF, -E/A grounded) of one ormore slave modules, and connecting SYNC andCOMP pins of the slave(s) respectively, the outputsmay be connected together to provide a modularapproach to power supply design.

Starting with Figure 14, a comparison of line andload step responses is made between the two con-verters. As a result of the feed-forward effect of thecurrent-mode converter, response to a step inputchange shows more than an order of magnitudeimprovement (Figure 14a) when compared to theconventional converter (Figure 14b). Although notas pronounced, response to a step load changeleaves the UC1846 converter (Figure 15) with aclear advantage in output response - 40mV ascompared to 70mV for the UC1525A.

Virtually all conventional push-pull converters areprone to flux imbalance caused by mismatchedstorage delays etc., in the output stage. Figure 16shows both converters operating with the samepower stage. No effort was made to match outputdevices. As may be seen, there is little noticeable

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APPLICATION NOTE U-93

difference between switch currents of the UC1846.However, the UC1525A - with identical output

transistors - shows phase B driving the core closeto saturation with 50% more current than phase A.

(A) UC1846 CURRENT-MODE CONTROLLED REGULATOR

(B) UC1525A VOLTAGE MODE CONTROLLER

FIGURE 13. PUSH-PULL FORWARD CONVERTER WITH (A) CURRENT-MODE CONTROL AND (B) VOLTAGE MODE CONTROL

t = 2ms/DIV

4 OUTPUT *RESPONSE50mV/DIV

(A) (B)

FIGURE 14. RESPONSE TO A STEP INPUT CHANGE OF 25 TO 35V BY (A) UC1846 and (B) UC1525A CONVERTERS

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APPLICATION NOTE U-93

(A)

t = 0.2ms/DIV

RESPONSE20mV/DIV

(B)

FIGURE 15. RESPONSIVE TO A STEP LOAD CHANGE OF 1 AMP BY (A) UC1846 AND (B) UC1525A CONVERTERS

t = Sps’DIV

CURRENTS(0.2A/DIV)

FIGURE 16. SWITCH CURRENTS SHOWING FLUX IMBALANCE IN (A) UC1846 AND (B) UC1525A CONVERTERS

6.0 ConclusionRarely do new design techniques evolve that canpromise as much as current-mode control for thepower supply engineer. We have shown this to be asimple technique easily extended from presentconverter topologies, that will increase dynamicperformance and provide a higher degree of relia-bility while permitting new approaches to modular

design. Until recently, current-mode converterscould not compete with the economics of conven-tional converters designed with I.C. controllers.Now, with the UC1846 designed specifically for thistask, current-mode control can provide all of theabove performance advantages on a cost competi-tive basis.

UNITRODE CORPORATION7 CONTINENTAL BLVD. MERRIMACK. NH 03054TEL (603) 424-2410 FAX (603) 424-3460

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