Design of benchmark circuit s5378 for reduced scan mode activity
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Transcript of Design of benchmark circuit s5378 for reduced scan mode activity
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Nelson Sunwoo
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Modify s5378 to full scan design
Modify scan flip flops to prevent switching in combination logic
Compare average power consumption of original and enhanced design
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Scan shift causes redundant switching in combination logic.
Power dissipation during the test mode is up to three times higher than normal mode.
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DFFmux
SE
SI
DQ
SO0
1
Scan flip-flop
Combinational logic
Scan flip- flops
Primary inputs
Primary outputs
SI
SO
SE
DQ
Scan flip- flops
Scan flip- flops
. .
.
Scan Flip Flop
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technology: TSMC 0.18umVdd: 1.8Vclock speed: 1GHz1000 random vector sets- inputs (0.5 activity)
- Scan in (random)
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Original design
Modified design
Power reduction
Average Power 52.559mW 36.252mW 31 %
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S. Gerstendrfer and H. J. Wunderlich, Minimized Power Consumption for Scan-based BIST, International Test Conference, 1999, pp 77-84.