Trams 6
Transcript of Trams 6
-
7/31/2019 Trams 6
1/18
Carbon Nanotube Technology
An Alternative in Future SRAM memories
UPC
CASTNESS11 WORKSHOP ON TERACOMP FET Projects, Rome , January17th-18th 2011
-
7/31/2019 Trams 6
2/18
Introduction
CASTNESS11 WORKSHOP ON TERACOMP FET Projects, Rome , January17th-18th 2011
OBJECTIVE: to evaluate the variability in Carbon nanotube Field Effect
Transistor (CNFET) as well as its real capability to be a promisingalternative to Si-CMOS technology.
1. Impact of carbon nanotube (CNT) diameter variations and the presence of
metallic CNTs in the transistor (device level).
2. Comparison between Si-CMOS and CNFET 6T SRAM cells (circuit level).
In Si-bulk CMOS technology the variability of the device parameters is a key
drawback and it may be a limiting factor for further miniaturizing nodes.
-
7/31/2019 Trams 6
3/18
CASTNESS11 WORKSHOP ON TERACOMP FET Projects, Rome , January17th-18th 2011
Carbon Nanotubes (CNTs)
Graphene
Carbon
nanotube
(nm) /3[ ] = 0
(nm) /3[ ] 0
Metallic
Semiconducting
Diameter
DCNT =3a0
n2 +m2 + nm
a0 = 0.142nm
Behaviour
Rest of
Rest of
Ch = na1 +ma2 (n,m)
Chiral vector
angle of the atom
arrangement along
the tube
Device level
-
7/31/2019 Trams 6
4/18
CASTNESS11 WORKSHOP ON TERACOMP FET Projects, Rome , January17th-18th 2011
Carbon Nanotube Field Effect Transistors
(CNFETs)An Ideal MOSFET-like CNFET is formed by 1 or more semiconductingCNTs perfectly aligned and well-positioned whose section under the gate is
intrinsic and the s/d extension regions are n/p doped.
Promising candidates to replace silicon CMOS due to its high performance
There are some imperfections inherent to CNT
synthesis and CNFET manufacturing process that
may eclipse the expectations
Device level
-
7/31/2019 Trams 6
5/18
SOURCES OF VARIATION
CNT growth process CNFET manufacturing process
Percentage of m-CNTs Diameter variations
S/D doping variations
Mispositioned and misaligned CNTs
NO control of chirality
CASTNESS11 WORKSHOP ON TERACOMP FET Projects, Rome , January17th-18th 2011
Metallic CNTs
Semiconducting CNTs
Device level
-
7/31/2019 Trams 6
6/18
CASTNESS11 WORKSHOP ON TERACOMP FET Projects, Rome , January17th-18th 2011
Fixeddparameterss
Powerrsupplyy 0.9VV
Oxideethicknessss 4nmm
Gate/Source/Drainnlengthh(CNT)) 16nmm
Widthhoff theemetall gatee 36nmm
CNTTpitchhh 4nmmmm
Variableeparameterss
Numberroff CNTSSperrdevicee(N)) Nominal:888888
Range:4-122
CNTTdiameterr(D)) 1-66nmm
Chii distributionn
MetalliccCNTTproportionn(TM)) 0%%-- 33%%
CNFET device model [1]
[1] J. Deng and H.-S. Wong, A compact spice model for carbon-nanotube field-effect transistors including nonidealities
and its application part II: Full device model and circuit performance benchmarking, Electron Devices, IEEE Transactions
on, vol. 54, no. 12, pp. 31953205, 2007.
Device level
-
7/31/2019 Trams 6
7/18
CASTNESS11 WORKSHOP ON TERACOMP FET Projects, Rome , January17th-18th 2011
Monte Carlo experiment
Example of IDS VDS distribution for 50 CNFET samples.
Device level
-
7/31/2019 Trams 6
8/18
CASTNESS11 WORKSHOP ON TERACOMP FET Projects, Rome , January17th-18th 2011
STD () of VTH and K
Percentage of variation (100x3/)
Device level
-
7/31/2019 Trams 6
9/18
CASTNESS11 WORKSHOP ON TERACOMP FET Projects, Rome , January17th-18th 2011
Variability analysis and performance in CMOS and CNFET SRAM 6T cells
Circuit level
PTMM TRAMSSWP11 CNFETT
Technologyy 32nmm 22nmm 16nmm 18nmm 13nmm 88tubess
TT 16nmm 11nmm 8nmm 9nmm 6.5nmm W=32nm,, L=16nmm
VDDD 1VV 1VV 1VV 0.7VV 0.7VV 1VV
-
7/31/2019 Trams 6
10/18
PTM TRAMS WP1 CNFET32nm 22nm 16nm 18nm 13nm 8 tubes
Static Power (pW) 109.60 112.40 279.60 11.39x106 8.11x106 5.82
Dynamic power ( W) 7.17 4.91 3.94 1.53 1.26 3.06
Read SNM (mV) 296 262.90 218 202.80 195.50 302.50
Cell area ( m2) 0.29 0.14 0.09 0.07 0.045 0.09
CASTNESS11 WORKSHOP ON TERACOMP FET Projects, Rome , January17th-18th 2011
Circuit level
CNFET SRAM cell versus Si-MOSFET SRAM cell (nominal comparison)
22.288 19.444 16.73323.422 20.977
7.777
1055
87.011
73.155
139.88
95.766
57.422
00
200
400
600
800
1000
1200
1400
1600
32nmm 22nmm 16nmm 18nmm 13nmm CNFETT
Writee mee (ps))
Accesss mee(ps))
-
7/31/2019 Trams 6
11/18
CASTNESS11 WORKSHOP ON TERACOMP FET Projects, Rome , January17th-18th 2011
Circuit level
CNFET SRAM cell versus Si-MOSFET SRAM cell (variability comparison)
CNFETTTechnologyy
NCNFETTVTHH
PCNFETTVTHH
Randomm6TTcelllllllll
1000xx1 /averagee
(V)) (V)) (V)) (V)) VTHH0.122 0.01877 -0.122 0.01877 15.58%%%
-
7/31/2019 Trams 6
12/18
CASTNESS11 WORKSHOP ON TERACOMP FET Projects, Rome , January17th-18th 2011
Circuit level
CNFET SRAM cell versus Si-MOSFET SRAM cell (variability comparison)
-
7/31/2019 Trams 6
13/18
CASTNESS11 WORKSHOP ON TERACOMP FET Projects, Rome , January17th-18th 2011
Circuit level
CNFET SRAM cell versus Si-MOSFET SRAM cell (variability comparison)
-
7/31/2019 Trams 6
14/18
CASTNESS11 WORKSHOP ON TERACOMP FET Projects, Rome , January17th-18th 2011
Device level
Conclusions
CNFETs are promising candidates to replace Si-MOSFETs due to their high
current driving capability, tolerance to temperature and low leakage currents.
Manufacturing variability, that is one of the key limiting factors in silicon-MOS
technology, has been investigated for such CNFET devices.
Considering a range of metallic tubes from 33% (current growth methods) to 0%
(perfection) and a realistic distribution of diameters, it has been shown that the
variability of both K factor and VTH is lower than CMOS for transistors with just 8
nanotubes, and much better for 12 tubes.
In a future scenario with a narrower distribution of CNT diameters, variation forboth parameters could reach levels from 15% to 25%, fact that would allow a
design procedure without the stress caused by variability in current
conventional technology.
-
7/31/2019 Trams 6
15/18
CASTNESS11 WORKSHOP ON TERACOMP FET Projects, Rome , January17th-18th 2011
Circuit level
Conclusions
CNFETs can be also considered as a potential alternative to CMOS in memory
systems.
CNT technology presents better performance than CMOS technologies.
However the implementation maturity of CNFET is still pending of several years
of development.
Variability analysis shows as a promising prospect, that even for todays
CNFETs performance, its variability is comparable with that of Si-MOS
technology in a scenario which we have called moderated.
Therefore, improvements in the control of chirality, the variability of CNFETscould be lower than in that moderated scenario.
-
7/31/2019 Trams 6
16/18
Thanks for your attention!
CASTNESS11 WORKSHOP ON TERACOMP FET Projects, Rome , January17th-18th 2011
-
7/31/2019 Trams 6
17/18
CASTNESS11 WORKSHOP ON TERACOMP FET Projects, Rome , January17th-18th 2011
Carbon Nanotubes (CNTs)
Graphene
Carbon
nanotube Diameter & VTH
DCNT =3a0
n2 +m2 + nm
a0 = 0.142nm
Vth Eg
2q=
3
3
aV
eDCNT
a 2.49 A
V 3.033eV
Device level
-
7/31/2019 Trams 6
18/18
CASTNESS11 WORKSHOP ON TERACOMP FET Projects, Rome , January17th-18th 2011
Mean () of VTH and K
Mean of Vth as Tm
Mean of Vth as N
Vth Eg
2q=
3
3
aV
eDCNT
Mean of K as Tm
Mean of K as N
Device level