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TB6560AHQ/AFG

2007-11-13 1

TOSHIBA BiCD Integrated Circuit Silicon Monolithic

TB6560AHQ,TB6560AFG PWM Chopper-Type bipolar Stepping Motor Driver IC The TB6560AHQ/AFG is a PWM chopper-type sinusoidal micro-step bipolar stepping motor driver IC. It supports both 2-phase/1-2-phase/2W1-2-phase/4W1-2-phase excitation mode and forward/reverse mode and is capable of low-vibration, high-performance drive of 2-phase bipolar type stepping motors using only a clock signal.

Features • Single-chip bipolar sinusoidal micro-step stepping motor

driver • Uses high withstand voltage BiCD process:

Ron (upper lower) = 0.6 Ω (typ.) • Forward and reverse rotation control available • Selectable phase drive (2, 1-2, 2W1-2, and 4W1-2) • High output withstand voltage: VDSS = 40 V • High output current: IOUT = AHQ: 3.5 A (peak)

AFG: 2.5 A (peak) • Packages: HZIP25-P-1.27/HQFP64-P-1010-0.50 • Built-in input pull-down resistor: 100 kΩ (typ.) • Output monitor pin equipped: MO current (IMO (max) = 1 mA) • Equipped with reset and enable pins • Built-in overheat protection circuit

*: Since this product has a MOS structure, it is sensitive to electrostatic discharge. These ICs are highly sensitive to electrostatic discharge. When handling them, please be careful of electrostatic discharge, temperature and humidity conditions.

TB6560AHQ

TB6560AFG

Weight: HZIP25-P-1.27: 9.86 g (typ.) HQFP64-P-1010-0.50: 0.26 g (typ.)

The TB6560AFG is RoHS compatible. The TB6560AHQ is a Sn-plated product including Pb which is RoHS exempted. The following conditions apply to solderability: *Solderability 1. Use of Sn-37Pb solder bath

*solder bath temperature = 230°C *dipping time = 5 seconds *number of times = once *use of R-type flux

2. Use of Sn-3.0Ag-0.5Cu solder bath *solder bath temperature = 245°C *dipping time = 5 seconds *the number of times = once *use of R-type flux

TB6560AHQ/AFG

2007-11-13 2

Block Diagram

M1

M2

CW/CCW

CLK

RESET

ENABLE

DCY1

DCY2

OSC

Input circuit

OSC

VDD

Maximum current setting circuit

Current selectorcircuit B

Overheat protectioncircuit

Protect MO

+

+

Bridge

driver A

Decoder

VMA

OUT_AP

OUT_AM

NFA

VMB

Bridge

driver B B Decoder

OUT_BP

OUT_BM

NFB

TQ1 TQ2

SGND PGNDA PGNDB

Current selectorcircuit A

10/64 1/42 2/43

11/2, 4

9/61, 62

12/6, 7

8/55, 56

14/13, 14

13/10, 11

16/19, 20

18/25, 26 17/2319/2820/30, 31

23/36

22/35

21/33

3/45

5/48

4/47

25/39

24/38

7/53

15/166/50, 51

TB6560AHQ/TB6560AFG

TB6560AHQ/AFG

2007-11-13 3

Pin Functions

Pin No.

AHQ AFG I/O Symbol Functional Description

1 42 Input TQ2 Torque setting input (current setting)

2 43 Input TQ1 Torque setting input (current setting)

3 45 Input CLK Step transition, clock input

4 47 Input ENABLE H: Enable; L: All output OFF

5 48 Input RESET L: Reset (output is reset to its initial state)

6 50/51 ⎯ SGND Signal ground (control side) (Note 1)

7 53 ⎯ OSC Connects to and oscillates CR. Output chopping.

8 55/56 Input VMB Motor side power pin (B phase side) (Note 1)

9 61/62 Output OUT_BM OUT_B output (Note 1)

10 64(*) ⎯ PGNDB Power ground

11 2/4(*) ⎯ NFB B channel output current detection pin (resistor connection). Short the two pins for AFG. (Note 1)

12 6/7 Output OUT_BP OUT_B output (Note 1)

13 10/11 Output OUT_AM OUT_A output (Note 1)

14 13/14(*) ⎯ NFA A channel output current detection pin (resistor connection). Short the two pins for AFG. (Note 1)

15 16 ⎯ PGNDA Power ground

16 19/20 Output OUT_AP OUT_A output (Note 1)

17 23 Output MO Initial state detection output. ON when in initial state

18 25/26 Input VMA Motor side power pin (A phase side) (Note 1)

19 28 Output Protect When TSD, ON. Normal Z.

20 30/31 Input VDD Control side power pin. (Note 1)

21 33 Input CW/CCW Forward/Reverse toggle pin. L: Forward; H: Reverse

22 35 Input M2 Excitation mode setting input

23 36 Input M1 Excitation mode setting input

24 38 Input DCY2 Current Decay mode setting input

25 39 Input DCY1 Current Decay mode setting input

・(*) : Pin assignment of TB6560AFG is different from that of TB6560FG.

・TB6560AHQ: No Non-connection (NC)

・TB6560AFG: Other than the above pins, all are NC. Pin numbers of NC are 1, 3, 5, 8, 9, 12, 15, 17, 18, 21, 22, 24, 27, 29, 32, 34, 37, 40, 41, 44, 46, 49, 52, 54, 57, 58, 59, 60, and 63.

・No problem to apply the voltage because of no connection of NC and Pin internally.

・All control input pins: Pull-down resistor 100 kΩ (typ.)

Note 1: If the TB6560AFG pin number column indicates more than one pin, the indicated pins should be tied to each other at a position as close to the pins as possible. (The electrical characteristics of the relevant pins in this document refer to those when they are handled in that way.)

TB6560AHQ/AFG

2007-11-13 4

<Terminal circuits>

Input pins (M1, M2, CLK, CW/CCW, ENABLE and RESET)

Output ins (MO, PROTECT)

VDD

100

kΩ

100 Ω

100 Ω

TB6560AHQ/AFG

2007-11-13 5

Pin Assignment

RE

SE

T

EN

AB

LE

(NC

)

CL

K

(NC

)

TQ

1

TQ

2

(NC

)

(NC

)

DC

Y1

DC

Y2

(NC

)

M1

M2

(NC

)

CW

/C

CW

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

(NC) 49 32 (NC)

SGND 50 31 VDD

SGND 51 30 VDD

(NC) 52 29 (NC)

OSC 53 28 Pro tec t

(NC) 54 27 (NC)

VMB 55 26 VMA

VMB 56 25 VMA

(NC) 57 24 (NC)

(NC) 58 23 MO

(NC) 59 22 (NC)

(NC) 60 21 (NC)

OUT＿BM 61 20 OUT＿AP

OUT＿BM 62 19 OUT＿AP

(NC) 63 18 (NC)

PGNDB 64 17 (NC)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

(NC

)

NF

B

(NC

)

NF

B

(NC

)

OU

T＿

BP

OU

T＿

BP

(NC

)

(NC

)

OU

T＿

AM

OU

T＿

AM

(NC

)

NF

A

NF

A

(NC

)

PG

ND

A

TB6560AFG

(Top View)TB6560AFG　　　（Top　View）

TB6560AHQ 　　（Top　View）

1 3 5 7 9 11 13 15 17 19 21 23 25

2 4 6 8 10 12 14 16

TQ

2

CL

K

RE

SE

T

OS

C

NF

B

OU

T＿

AM M1

CW

/C

CW

Pro

tec

t

MO

M2

DC

Y2

PG

ND

A

DC

Y1

NF

A

OU

T＿

AP

1 8 20 22 24

TQ

1

VM

A

VD

D

EN

AB

LE

SG

ND

VM

B

PG

ND

B

OU

T＿

BP

OU

T＿

BM

TB6560AHQ/AFG

2007-11-13 6

Absolute Maximum Ratings (Ta = 25°C)

Characteristic Symbol Rating Unit

VDD 6 Power supply voltage

VMA/B 40 V

AHQ 3.5 Output current Peak

AFG IO (PEAK)

2.5 A/phase

MO drain current I (MO) 1 mA

Input voltage VIN 5.5 V

5 (Note 1)AHQ

43 (Note 2)

1.7 (Note 3)Power dissipation

AFG

PD

4.2 (Note 4)

W

Operating temperature Topr −30 to 85 °C

Storage temperature Tstg −55 to 150 °C

Note 1: Ta = 25°C, No heat sink.

Note 2: Ta = 25°C, with infinite heat sink (HZIP25).

Note 3: Ta = 25°C, with soldered leads.

Note 4: Ta = 25°C, when mounted on the board (4-layer board).

Operating Range (Ta = −30 to 85°C)

Characteristic Symbol Test Condition Min Typ. Max Unit

VDD ⎯ 4.5 5.0 5.5 V Power supply voltage

VMA/B VMA/B > = VDD 4.5 ⎯ 34 V

AHQ ⎯ ⎯ ⎯ 3 Output current

AFG IOUT

⎯ ⎯ 1.5 A

Input voltage VIN ⎯ 0 ⎯ 5.5 V

Clock frequency fCLK ⎯ ⎯ ⎯ 15 kHz

OSC frequency fOSC ⎯ ⎯ ⎯ 600 kHz

TB6560AHQ/AFG

2007-11-13 7

Electrical Characteristics (Ta = 25°C, VDD = 5 V, VM = 24 V)

Characteristic Symbol Test

Circuit Test Condition Min Typ. Max Unit

High VIN (H) 2.0 ⎯ VDDInput voltage

Low VIN (L)

1 −0.2 ⎯ 0.8

V

Input hysteresis voltage VH 1

M1, M2, CW/CCW, CLK, RESET ,ENABLE, DECAY, TQ1, TQ2, ISD

⎯ 400 ⎯ mV

IIN (H)

M1, M2, CW/CCW, CLK, RESET ,ENABLE, DECAY, TQ1, TQ2, ISDVIN = 5.0 V Built-in pull-down resistor

30 55 80 Input current

IIN (L)

1

VIN = 0 V ⎯ ⎯ 1

μA

IDD1

Output open, RESET : H, ENABLE: H (2, 1-2 phase excitation)

⎯ 3 5

IDD2

Output open, RESET : H, ENABLE: H (W1−2, 2W1-2 phase excitation)

⎯ 3 5

IDD3 RESET : L, ENABLE: L ⎯ 2 5

Consumption current VDD pin

IDD4

1

RESET : H, ENABLE: L ⎯ 2 5

mA

IM1 RESET : H/L, ENABLE: L ⎯ 0.5 1 Consumption current VM pin

IM2 1

RESET : H/L, ENABLE: H ⎯ 0.7 2 mA

Output channel margin of error ΔVO ⎯ B/A, COSC = 330 μF −5 ⎯ 5 %

VNFHH TQ1 = H, TQ2 = H 10 20 30

VNFHL TQ1 = L, TQ2 = H 47 50 55

VNFLH TQ1 = H, TQ2 = L 70 75 80 VNF level Level differential

VNFLL

⎯

TQ1 = L, TQ2 = L 100

%

Minimum clock pulse width tW (CLK) ⎯ C = 330 pF 30 ⎯ ⎯ μs

MO output residual voltage VOL MO ⎯ IOL = 1 mA ⎯ ⎯ 0.5 V

TSD (Note) TSD ⎯ ⎯ 170 ⎯ °C

TSD hysteresis (Note) TSDhys ⎯ ⎯ 20 ⎯ °C

Oscillating frequency fOSC ⎯ C = 330 pF 60 130 200 kHz

Note: No shipping test

TB6560AHQ/AFG

2007-11-13 8

Electrical Characteristics (Ta = 25°C, VDD = 5 V, VM = 24 V)

Characteristic Symbol Test

Circuit Test Condition Min Typ. Max Unit

Ron U1H ⎯ 0.3 0.4 AHQ

Ron L1H

IOUT = 1.5 A ⎯ 0.3 0.4

Ron U1F ⎯ 0.35 0.5 Output ON resistor

AFG Ron L1F

4

IOUT = 1.5 A ⎯ 0.35 0.5

Ω

2W1-2- phase excitation

1-2- phase excitation

θ = 0 ⎯ 100 ⎯

⎯ ⎯ θ = 1/16 ⎯ 100 ⎯ 2W1-2- phase

excitation

⎯ θ = 2/16 93 98 100

⎯ ⎯ θ = 3/16 91 96 1002W1-2- phase

excitation

⎯ θ = 4/16 87 92 97

⎯ ⎯ θ = 5/16 83 88 93 2W1-2- phase

excitation

⎯ θ = 6/16 78 83 88

⎯ ⎯ θ = 7/16 72 77 82 2W1-2- phase

excitation

1-2- phase

excitation

θ = 8/16 66 71 76

⎯ ⎯ θ = 9/16 58 63 68

2W1-2- phase

excitation ⎯ θ = 10/16 51 56 61

⎯ ⎯ θ = 11/16 42 47 52

2W1-2- phase

excitation ⎯ θ = 12/16 33 38 43

⎯ ⎯ θ = 13/16 24 29 34

2W1-2- phase

excitation ⎯ θ = 14/16 15 20 25

4W1-2- phase excitation

⎯ ⎯ θ= 15/16 5 10 15

A-B

cho

ppin

g cu

rren

t (N

ote

1)

2-phase excitation

Vector ⎯

⎯

TQ1 = L, TQ2 = L

⎯ 100 ⎯

%

Reference voltage VNF ⎯ TQ1, TQ2 = L (100%) OSC = 100 kHz 450 500 550 mV

tr ⎯ 1 ⎯ Output transistor switching characteristics (Note 2) tf

RL = 10 Ω, VNF = 0.5 V ⎯ 1 ⎯

tpLH RESET to output ⎯ 1 ⎯

tpLH ⎯ 3 ⎯ Delay time (Note 2)

tpHL

7

ENABLE to output ⎯ 2 ⎯

μs

Upper side ILH ⎯ ― 1 Output leakage current

Lower side ILL

6 VM = 40 V ⎯ ― 1

μA

Note 1: Maximum current (θ = 0): 100% Note 2: No shipping test.

TB6560AHQ/AFG

2007-11-13 9

Description of Functions

1. Excitation Settings You can use the M1 and M2 pin settings to configure four different excitation settings. (The default is 2-phase excitation using the internal pull-down.)

Input

M2 M1

Mode (Excitation)

L L 2-phase

L H 1-2-phase

H L 4W1-2-phase

H H 2W1-2-phase

2. Function

When the ENABLE signal goes Low level, it sets an OFF on the output. The output changes to the Initial mode shown in the table below when the RESET signal goes Low level. In this mode, the status of the CLK and CW/CCW pins are irrelevant.

Input

CLK CW/CCW RESET ENABLE Output Mode

L H H CW

H H H CCW

X X L H Initial mode

X X X L Z

X: Don’t care

3. Initial Mode When RESET is used, the phase currents are as follows. In this instance, the MO pin is L (connected to open drain).

Excitation Mode A Phase Current B Phase Current

2-phase 100% −100%

1-2-phase 100% 0%

W1-2-phase 100% 0%

2W1-2-phase 100% 0%

4. Decay Mode Settings

Discharging time of PWM operation corresponds to four cycles of OSC frequency. 25% decay is created by inducing decay during the last cycle in Fast mode; 50% decay is created by inducing decay during the last two cycles in Fast mode; and 100% decay is created by inducing all four cycles in Fast mode. If there is no input with the pull-down resistor connection then the setting is Normal.

Dcy2 Dcy1 Current Decay Setting

L L Normal 0%

L H 25% Decay

H L 50% Decay

H H 100% Decay

TB6560AHQ/AFG

2007-11-13 10

5. Torque Settings (Current Value) The current ratio used in actual operations is determined in regard to the current setting due to resistance. Configure this for extremely low torque scenarios such as when Weak Excitation mode is stopped. If there is no input with the pull-down resistor connection then the setting is 100% torque.

TQ2 TQ1 Current Ratio

L L 100%

L H 75%

H L 50%

H H 20% (weak excitation)

6. Calculating Formula of Setting Current

To drive at constant current, the reference current should be setup by the external resistance. The current can not be charged when the voltage applied to NFA (B) terminal is 0.5 V or more (in case torque is 100%). Iout(A)=0.5V/RNF(Ω)

(Ex.) Maximum current is 1A : External resistance of 0.5Ω is used.

7. Protect and MO (Output Pins) There is an open-drain connection for the output pins. Connect the pull-up resistance in using. When a given pin is in its designated state it will go ON and output at Low level.

Pin State Protect MO

Low Overheat protection operation Initial state

Z Normal operation Other than initial state

8. OSC (Setting External Condenser)

Triangle-waves are generated internally by connecting the external condenser to the OSC terminal and having the CR oscillation. fosc = 1/(Cosc × 1.5 × (10/Cosc + 1)/66) × 1000 kHz The approximate values are as shown below.

Condenser Oscillating Frequency

1000 pF 44 kHz

330 pF 130 kHz

100 pF 400 kHz

Open-drain connection

TB6560AHQ/AFG

2007-11-13 11

Relationship between Enable, RESET and Output (OUT and MO)

Ex-1: ENABLE 1-2-Phase Excitation (M1: H, M2: L)

The ENABLE signal at Low level disables only the output signals. Internal logic functions proceed in

accordance with input clock signals and without regard to the ENABLE signal. Therefore output current is initiated by the timing of the internal logic circuit after release of disable mode.

Ex-2: RESET 1-2-Phase Excitation (M1: H, M2: L)

When the RESET signal goes Low level, output goes Initial state and the MO output goes Low level (Initial

state: A Channel output current is 100%). Once the RESET signal returns to High level, output continues from the next state after Initial from the

next raise in the Clock signal.

CLK

ENABLE

RESET

MO

100 (%)

0

−100

t0 t1 t2 t3 t7 t8 t9 t10 t11 t12 OFF

71

−71

IA

CW

CLK

ENABLE

RESET

MO

100(%)

0

−100

t0 t1 t2 t3 t7 t8 t4 t5t2 t3

71

−71

t6

IA

CW

TB6560AHQ/AFG

2007-11-13 12

2-Phase Excitation (M1: L, M2: L, CW Mode)

1-2-Phase Excitation (M1: H, M2: L, CW Mode)

CLK

MO

100(%)

0

−100

t0 t1 t2 t3 t7t4 t5 t6

IA

CW

100(%)

0

−100

IB

CLK

MO

100(%)

0

−100

t0 t1 t2 t3 t7 t8t4 t5 t6

71

−71

IA

100(%)

0

−100

71

−71

IB

CW

TB6560AHQ/AFG

2007-11-13 13

4W1-2-Phase Excitation (M1: L, M2: H, CW Mode)

−100 STE−98

0

−96−88−92

−77−71

−56−63

−47−38

−29

−20

−10

−83

10

20

29

3847566371778388929698100

[%]

A 相

B 相

TB6560AHQ/AFG

2007-11-13 14

2W1-2-Phase Excitation (M1: H, M2: H, CW Mode)

IB

IA

CLK

t0 t1 t2 t3 t7 t8 t4 t5 t12 t13t6

CW

MO

100(%)

98928371

56

38

20

0

−20

−38

−56

−71−83−92−98

−100

100(%)

98928371

56

38

20

0

−20

−38

−56

−71−83−92−98

−100

t9 t10 t11 t14 t17 t18t15 t16 t19 t20 t21 t22 t23 t27 t28 t24 t25 t26 t29 t30 t31 t32

TB6560AHQ/AFG

2007-11-13 15

<Input Signal Example>

As for the change of M1 and M2, it is recommended that M1 and M2 signals be changed after setting the RESET signal Low during the Initial state (MO is Low). Even when the MO is Low, changing the RESET signal without setting the RESET signal Low may cause the discontinuity in the current waveform.

CK

MO

M2

100 (%)

0

1-2-phase excitation

91

IA

71.4

40

−40

−71.4 −91

−100

M1

RESET

Other excitation

TB6560AHQ/AFG

2007-11-13 16

1. Current Waveform and Settings of Mixed Decay Mode You can configure the points of the current’s shaped width (current’s pulsating flow) using 1-bit input in

Decay mode for constant-current control. “NF” refers to the point at which the output current reaches its setting current value and “RNF” refers to

the monitoring timing of the setting current. The smaller the MDT value, the smaller the current ripple (current wave peak), and the current’s decay

capability will fall.

NF Normal Mode RNF

Setting Current Value

OSC Pin Internal Waveform

fchop

NF 25% Decay Mode

RNFMDT


NF 50% Decay Mode

RNF

MDT


NF 100% Decay Mode

RNF


Charge mode → NF: Setting current value reached → Slow mode → Current monitoring → (When setting current value > Output current) Charge mode

Charge mode → NF: Setting current value reached → Slow mode → Mixed decay timing → Fast mode → Current monitoring → (When setting current value > Output current) Charge mode

Charge mode → NF: Setting current value reached → Slow mode → Mixed decay timing → Fast mode → Current monitoring → (When setting current value > Output current) Charge mode

Charge mode → NF: Setting current value reached → Fast mode → Current monitoring → (When setting current value > Output current) Charge mode

TB6560AHQ/AFG

2007-11-13 17

2. Current Control Modes (Decay Mode effect) • Direction in which current value increases (sine wave)

• Direction in which sine wave decreases

(when a high decay ratio (MDT%) is used in Mixed Decay mode)

• Direction in which sine wave decreases

(when a low decay ratio (MDT%) is used in Mixed Decay mode)

During Mixed Decay mode and Fast Decay mode, if the setting current value < output current at RNF:

current monitoring point, the Charge mode at the next chopping cycle will disappear and the pattern will change to Slow Fast Mode (Slow → Fast occurs at MDT). (In reality, a charge is applied momentarily to confirm the current.)

Note: These figures are intended for illustrative purposes only. If designed more realistically, they would show transient response curves.

Slow Slow

Slow Slow

Fast FastCharge

Charge

FastCharge Fast Charge



Slow Slow

FastCharge

Fast Charge

Slow

Fast

Slow

FastCharge

Since the current’s rate of decay is fast, its compliance with the setting current value is also fast.



Slow

Fast Charge

Slow

FastCharge

FastSlow

Fast

Slow

Since the current’s rate of decay is slow, its compliance with the setting current value takes a long time (or may not follow at all).



TB6560AHQ/AFG

2007-11-13 18

3. Mixed Decay Mode Waveform (Current Waveform)

• When the NF points come after mixed decay timing

• When the output current value > Setting current value in mixed decay mode

*: Even if the output current rises above the setting current at the RNF point, a charge is applied momentarily to confirm the current.

NF

NF

25% Mixed Decay Mode


IOUT

fchop fchop



RNF

MDT (Mixed Decay Timing) Points

NF

NF


IOUT

fchop fchop


Setting current value

RNF


CLK Signal Input

Switches to Fast mode after Charge mode

RNF

NF

NF

25% MIXED DECAY MODE

IOUT

fchop fchop Setting Current Value

CLK Signal Input

fchop



RNF

RNF

TB6560AHQ/AFG

2007-11-13 19

4. Fast Decay Mode Waveform After the current value set by RNF, torque or other means is attained, the output current to load will

make the transition to full regenerative mode.

fchop

CLK Signal Input

Fast Decay Mode (100% Decay Mode)

Setting Current Value IOUT

NF

Since the setting current value > output current, charge mode → NF → Fast Decay mode transition will take place at even the next cycle.

RNF

RNF

RNF


Transition to Charge mode for a brief moment

TB6560AHQ/AFG

2007-11-13 20

5. CLK Signal and Internal CR CK Output Current Waveform (when the CLK signal is input in the middle of Slow mode)

When the CLK signal is input, the Chopping Counter (OSC Counter) is forcibly reset at the timing of the

OSC. As a result, the response to input data is fast in comparison to methods that don’t reset the counter. The delay time is one OSC cycle: 10 μs @100 kHz Chopping using the Logic Block logic value. After the OSC Counter is reset by CLK signal input, the transition is invariably made to Charge mode

for a brief moment to compare the current.

Note: Even in Fast Decay Mode, the transition is invariably made to Charge mode for a brief moment to compare the current.


CLK Signal Input


RNF


fchop



The CR counter is reset here.

NF

RNF

MDT

NF

MDT

fchop fchop

TB6560AHQ/AFG

2007-11-13 21

6. CLK Signal and Internal OSC Output Current Waveform (when the CLK signal is input in the middle of Charge mode)


CLK Signal Input


IOUT

RNF


fchop



The OSC Counter is reset here.

NF

RNF

MDT

MDT

fchop fchop

TB6560AHQ/AFG

2007-11-13 22

7. CLK Signal AND Internal OSC Output Current Waveform (when the CLK signal is input in the middle of Fast mode)

NF


CLK Signal Input


RNF


fchop




fchop fchop

MDT

NF

RNF

MDT

TB6560AHQ/AFG

2007-11-13 23

8. Internal OSC Output Current Waveform when Setting Current is Reverse (when the CLK signal is input using 2-phase excitation)


CLK Signal Input

fchop


fchop fchop


IOUT

RNF


NF

RNF

0

MDT

NF

TB6560AHQ/AFG

2007-11-13 24

Current Draw-out Path when ENABLE is Input in Mid Operation When all the output transistors are forced OFF during Slow mode, the coil energy is drawn out in the

following modes:

Note: Parasitic diodes are indicated on the designed lines. However, these are not normally used in Mixed Decay mode.

As shown in the figure above, an output transistor has parasitic diodes. Normally, when the energy of the coil is drawn out, each transistor is turned ON and the power flows in the

opposite-to-normal direction; as a result, the parasitic diode is not used. However, when all the output transistors are forced OFF, the coil energy is drawn out via the parasitic diode.

U1

L1

U2

L2

PGND

OFF

OFF

U1

L1

U2

L2

OFF

ON

Note

Load

PGND

U1

L1

U2

L2

OFF

OFF

Note

Load

PGND

Note

RNF

VM

ON

ON

Load

Charge Mode Slow Mode Force OFF Mode

ON

RNF

VM

RNF

VM

OFF

OFF

ENABLE is input

OFF

TB6560AHQ/AFG

2007-11-13 25

Output Stage Transistor Operation Mode

Output Stage Transistor Operation Functions

CLK U1 U2 L1 L2

CHARGE ON OFF OFF ON

SLOW OFF OFF ON ON

FAST OFF ON ON OFF

Note: The above chart shows an example of when the current flows as indicated by the arrows in the above figures. If the current flows in the opposite direction, refer to the following chart:

CLK U1 U2 L1 L2

CHARGE OFF ON ON OFF

SLOW OFF OFF ON ON

FAST ON OFF OFF ON

Upon transitions of above-mentioned functions, a dead time of about 300 ns is inserted respectively.

U1

L1

U2

L2

PGND

OFF

OFF

U1

L1

U2

L2

OFF

ON

Note

Load

PGND

U1

L1

U2

L2

Note

Load

PGND

Note

RNF

VM

ON

ON

Load

Charge Mode Slow Mode Fast Mode

ON

RNF

VM

RNF

VM

OFF

OFFOFF

ON

ON

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Measurement Waveform

Figure 1 Timing Waveforms and Names

OSC-Charge DELAY:

The conversion from the OSC waveform to the internal OSC waveform is done by recognizing the level of chopping wave. The voltages of 2 V or above are considered as a High level, and voltages of 0.5 V or below are considered as a Low level as designed values. However, there is a response delay and that there occurs the peak-to-peak voltage variation.

Figure 2 Timing Waveforms and Names (CR and Output)

CLK tCLK tCLK

tpLH

tpHL

VM

GND tr tf

10%

50%

90% 90%

50%

10%

OSCWaveform


2 V

0.5 V

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Power Dissipation

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1. How to Turn on the Power and Input the Signal Turn on VDD. When the voltage has stabilized, turn on VMA/B. In addition, set the Control Input pins to Low when inputting the power. (All the Control Input pins are pulled down internally.)

After VDD and VMA/B reach the specified voltage completely, RESET and ENABLE can be set high. If you skip any of this process, the IC may not drive correctly and the IC and the peripheral parts may be destroyed. Once the power is on, the CLK signal is received and excitation advances when RESET goes high and excitation is output when ENABLE goes high. If only RESET goes high, excitation won't be output and only the internal counter will advance. Likewise, if only ENABLE goes high, excitation won't advance even if the CLK signal is input and it will remain in the initial state. The following is an example:

In shutdown the power, follow the inverse process.

<Recommended Control Input Sequence>

2. Power Dissipation

The IC power dissipation is determined by the following equation: P = VDD × IDD + IOUT × Ron × 2 drivers The higher the ambient temperature, the smaller the power dissipation. Check the PD-Ta curve, and be sure to design the heat dissipation with a sufficient margin.

3. Heat Sink Fin Processing

The IC fin (rear) is electrically connected to the rear of the chip. If current flows to the fin, the IC will malfunction. If there is any possibility of a voltage being generated between the IC GND and the fin, either ground the fin or insulate it.

4. Thermal Protection

When the temperature reaches 170°C (as standard value), the thermal protection circuit is activated switching the output to off. There is a variation of plus or minus about 20°C in the temperature that triggers the circuit operation.

OutputZ

ZOutput current setting

Internal current setting

OUT

ENABLE

HL

HL

RESETHL

CLK

Internal current setting: Invariable Output OFF

Internal current setting: Variable

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Application Circuit

Note: Connect the power condenser to the IC as near as possible.

• Utmost care is necessary in the design of the output, VDD, VM, and GND lines since the IC may be destroyed by short-circuiting between outputs, air contamination faults, or faults due to improper grounding, or by short-circuiting between contiguous pins.

• Follow the process of inputting power described in page 28.

NFCompA M

MCU or

External input

CLK

RESET

ENABLE

M1

M2

CW/CCW

DCY1

DCY2

TQ1

TQ2

Protect

MO

R1 R2

OSC

100 pF ∼ − 400 kHz

SGND

PGND

Fuse

10μF 5 V 1μF

VDD VMA VMB

1μF 47μF 24 V

Logic

CurrentControl

H-SW A

H-SW B

OUTAP

OUTAM

OUTBP

OUTBM

RNFA

RNFB

NFA

NFB

NFCompB

0.5Ω : Iout(max.)=1.0A

PWM control

circuit

PWM control

circuit

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Package Dimensions

Weight: 9.86 g (typ.)

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Package Dimensions

Weight: 0.26 g (typ.)

Note: The rear heat sink block will be 5.5 mm × 5.5 mm. (PROVISIONAL)

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Notes on Contents 1. Block Diagrams

Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes.

2. Equivalent Circuits

The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes.

3. Timing Charts

Timing charts may be simplified for explanatory purposes. 4. Application Circuits

The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required, especially at the mass production design stage. Toshiba does not grant any license to any industrial property rights by providing these examples of application circuits.

5. Test Circuits

Components in the test circuits are used only to obtain and confirm the device characteristics. These components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment.

IC Usage Considerations

Notes on handling of ICs [1] The absolute maximum ratings of a semiconductor device are a set of ratings that must not be

exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion.

[2] Use an appropriate power supply fuse to ensure that a large current does not continuously flow in

case of over current and/or IC failure. The IC will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required.

[3] If your design includes an inductive load such as a motor coil, incorporate a protection circuit into

the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power ON or the negative current resulting from the back electromotive force at power OFF. IC breakdown may cause injury, smoke or ignition. Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable, the protection function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke or ignition.

[4] Do not insert devices in the wrong orientation or incorrectly. Make sure that the positive and negative terminals of power supplies are connected properly. Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. In addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time.

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Points to remember on handling of ICs (1) Thermal Shutdown Circuit

Thermal shutdown circuits do not necessarily protect ICs under all circumstances. If the thermal shutdown circuits operate against the over temperature, clear the heat generation status immediately. Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the thermal shutdown circuit to not operate properly or IC breakdown before operation.

(2) Heat Radiation Design

In using an IC with large current flow such as power amp, regulator or driver, please design the device so that heat is appropriately radiated, not to exceed the specified junction temperature (TJ) at any time and condition. These ICs generate heat even during normal use. An inadequate IC heat radiation design can lead to decrease in IC life, deterioration of IC characteristics or IC breakdown. In addition, please design the device taking into considerate the effect of IC heat radiation with peripheral components.

(3) Back-EMF

When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motor’s power supply due to the effect of back-EMF. If the current sink capability of the power supply is small, the device’s motor power supply and output pins might be exposed to conditions beyond maximum ratings. To avoid this problem, take the effect of back-EMF into consideration in system design.

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RESTRICTIONS ON PRODUCT USE 20070701-EN

• The information contained herein is subject to change without notice.

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.

• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall be made at the customer’s own risk.

• The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations.

• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties.

• Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations.

• The products described in this document are subject to foreign exchange and foreign trade control laws.

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