Timing and Constraints “The software is the lens through which the user views the FPGA.” -Bill...
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Transcript of Timing and Constraints “The software is the lens through which the user views the FPGA.” -Bill...
![Page 1: Timing and Constraints “The software is the lens through which the user views the FPGA.” -Bill Carter.](https://reader036.fdocuments.net/reader036/viewer/2022062407/56649f425503460f94c612af/html5/thumbnails/1.jpg)
Timing and Constraints
“The software is the lens through which the user views the FPGA.”
-Bill Carter
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Outline• Basic Timing (comb. and sequential)• Block timing models
– LUTs– BRAM– Multipliers
• Some standard design timing tricks• Constraints
– Timing– Geometric (pinning & arrangement – Combinations
• Best tools– Experience– Insight
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Propagation Delay
LUT Tpd is called “Tilo”
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Flop Timing
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LUT Logic Timing Parameters
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Basic LUT Logic Timing
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Distributed RAM Timing Model
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Dist. RAM Parameters
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LUT SRL Timing Model
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SRL Timing Parameters
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LUT w. Carry Chain Focus
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Carry Chain Timing
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BRAM Timing Model
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BRAM Timing Params
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Multiplier Model & Delay Variation
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Multiplier Timing Params
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Routing Delays
• FPGA datasheets do not give details on routing delay. Hence:– Routing delays not known to designer until
design is placed and routed– Delays for early silicon are frequently still
under analysis– Software maintains best source for the real
timing
• FPGA datasheets do provide times associated with incremental silicon blocks
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Virtex style logic tile
Comment:CLE with IMUX and OMUX is what weCall the “CLB”
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What you may find inside the Interconnect block
Little black splotchesAre muxes or littlePIPs to make selectableAttachments….
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Some standard timing tricks
• Load splitting (aka fanout reduction)– Identify sites driving large number of loads– Insert buffered version of the signal with multiple
buffers each handling a piece of the total load– Result usually faster
• Pipelining– Insert flip flop stages to reduce setup time restrictions– Increases clocking speed, at expense of added
latency
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Pipelining Idea
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Pipeline solutionEach flip stage can operate at fasterRate than before, but result goes validAfter TWO clocks.
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Constraints
• More options than we will discuss today• High level, global constraints = big payoff• Will compare a couple of designs across
multiple constraints/combinations to illustrate:– 32 bit adder (inherent internal constraint)
• Combinational suggests tPD constraints
– 32 bit shifter (very malleable)• Sequential suggests Fmax or cycle constraints
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Spartan 3S50TQ144
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Big Adder
module Big_Adder1( input [31:0] A, input [31:0] B, output [32:0] SUM );
assign SUM = A + B;endmodule
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Big Adder (unconstrained)
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Adder with 20 nsec tPD constraint
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Change constraint
• Original unconstrained looks ~same as the nominal 20 nsec constraint.
• 20 nsec constraint came in at 11.83 nsec.
• Push it down a little, to say 11 nsec and see what happens……
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Adder with 11 ns constraint
original new
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Timing Improvement Wizard
Screen 1
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TIW
Screen 2
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TIW
Screen 3
Bad news ~78% of theDelay is due to logicSuggests need for fasterpart
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Note
Several bitsAre out of spec
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Interesting…
Faster designMeets timeWithoutShift to right?
Comment:RecompiledOn -5 version(original =-4)
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Comments
• Free pinning, free routing gave a result and revealed that 11.83 nsec possible
• Free pinning, constrained to 11 nsec revealed 11 nsec is NOT possible (for -4 part)~78% time spent in silicon delay
~22% time spent in routing delay
Faster part (-5) hits 11 nsec, with centered design.
Faster part won’t hit 10 nsec when constrained
(please experiment for yourself!)
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“Big_Shifter” Codemodule Big_Shifter( input C, input ALOAD, input SI, input [31:0] D, output SO );reg [31:0] tmp; always @(posedge C or posedge ALOAD) begin if (ALOAD) tmp = D; else begin tmp = {tmp[30:0], SI}; end end assign SO = tmp[31];endmodule
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Big Shifter (unconstrained)
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Run Failed….chunk of PAR report
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Revised Constraints
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Revised layout
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Constraint revised again
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Didn’t run: PAR report advice
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Hmmm…based on slack revise to:
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PAR report from revised setup/hold times
Bingo!
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clock
Clock net
Serial in
Serial out
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From “FloorPlan IO Pre-Synthesis”
Just defining at the BANK level(versus explicit PADs)
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Placing half pins on Bank 0
Shifted the design aroundBut still met timing…..
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Closing Comments• The ISE constraints guide is online• It has timing, placement, grouping, relational and
synthesis level constraints for both VHDL and Verilog
• MOST designers prefer to have a design.ucf file as a separate item.
• Best results most often by writing in RTL with .ucf file
• Best approach is to experiment using small designs to see what the results are– Examine various reports– Look at “world view”– Pay attention to advice from S/W
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Footnote: WebPack 11.1 v. of shifter