This document is the property of EADS Astrium and Aurelia Microelettronica. - Approved for limited...

This document is the property of EADS Astrium and Aurelia Microelettronica. - Approved for limited distribution only. No disclosure without written permission. CONFIDENTIAL

AMICSA 2008: Radiation Tests on SOIAMICSA 2008: Radiation Tests on SOI

11

A.Wagner EADS AstriumS. Chicca - Aurelia MicroelettronicaA.Colonna- Aurelia Microelettronica

Cascais, Portugal 1Cascais, Portugal 1stst September 2008 September 2008

A 1553 Transceiver ASIC for Space Embedded

Applications using a SOI Technology



22

Presentation ContentsPresentation Contents

• MIL 1553 Transceiver status

• Transceiver General Block Diagram and Features

• Technology selection for a latch up free design

• Architectural design choices to improve the transceiver robustness against TID

• TID degraded models extraction and degraded-transceiver simulation campaign

• Layout countermeasures to reduce effects of TID-induced leakage currents



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MIL STD 1553 TransceiverMIL STD 1553 Transceiver

The MIL STD 1553 IC transceiver has been designed by Aurelia and Astrium EADS, prime contractor, and placed and routed by Aurelia in the frame of the ESA Program

“Europeanisation of MIL SDT 1553 Data Products”

in X FAB 1.0m HV SOI technology.

Transceiver status:

• I First run silicon functional with parametric non compliances recovered by FIB repair in I silicon

• II Second run silicon showed recovery of all parametric non compliances

• Co60 TID irradiation tests performed on First run by EADS Astrium and are planned for the Second run



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Transceiver DesignTransceiver DesignThe transceiver design at architectural level has been conducted by taking

into account the following requirements:– The transceiver has to be compliant with the STD 1553 physical layer

specifications– The transceiver has to be latch-up free and it is used in space environment (TID

tests performed up to 100Krad (Si) TID showed no deviation of the Electrical Characteristics up to 50Krad

The rad-hardness of the design has been achieved by:– Technology selection: X-FAB SOI HV 1.0um CMOS process is latch up free– Architectural Design choices – Detailed Design and Layout choices– Extensive Simulation Campaign and Design Refining with TID-degraded models

(in house built) based on TID tests performed on basic components

We will present the transceiver design with special attention to the countermeasures undertaken to improve design rad-hardness and the results of the first run TID test campaign



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Transceiver Block Diagram & InterfaceTransceiver Block Diagram & Interface

COMPARATOR

COMPARATOR

FILTER

RX

RXB

RXBUS RXBUSB

RECEIVER SECTION

TRANSMITTER SECTION

TX TXB

TXBUS

TXBUSB

DRIVER

DRIVER

INHIBITION

DATA BUS

COUPLING

1553 DATABUS

TXINH

Va (Point A)

EXTERNAL ISOLATION

TRANSFORMER

RXSENS

PREAMPLIFIERSHAPING

NETWORK

VCC VANA GND

PREAMPLIFIERSHAPING

NETWORK



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Transceiver Key-FeaturesTransceiver Key-Features• Transmitter section designed to couple with center tapped (GND) transformers

according to MIL 1553 STD• High Impedance capability on transmitter (disable control pin TXINH)• Internal consistency check on digital control signals • Shaping network

• Receiver section compliant with MIL 1553 STD, with internally generated threshold• Outputs RX and RXB generation programmable through RXINHB and RXSENS input pins• Internal filtering on receiver input waveforms to improve S/N ratio

• 5V/3.3V compatible in/out digital interface thanks to dedicated power supply for digital outputs

• TTL and LVTTL digital inputs• CMOS or LVCMOS digital outputs (depending on digital power supply level)• Less than 10mA current consumption when not transmitting• Latch Up Immune (SOI X-FAB 1.0um technology)• Radiation Goal compliant with space missions (50Krad achieved)



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Architectural Design: transmitterArchitectural Design: transmitter

Input Logic comparator with threshold derived from power supply to avoid logic input threshold shift due to TID effects

Internal divers to provide the current capability to charge and discharge the power output transistor gate within the specified rise/fall times

HV p-type Power output transistors

Single blocking diode to block the current path towards the power supply related with high voltages induced from the bus

Proposal for discussion: discuss current limitation feature against cross conduction transients

Shift level Combinatorial logic

TX

TXB

Slope Control&

Driver

PowerStage

VANA

sense

TXBUS

Slope Control&

Driver

PowerStage

TXBUSB

TTL/LVTTLdiscrimination

Transmitter logic

Power Output Transistors

Current limitation



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Power Transistors SelectionPower Transistors Selection

Positive trapped charges in the field oxide (300nm) may induce inversion on pdrift region causing a channel stop

To comply with the grounded center tap of the transformer (and avoiding internal charge pump) a p-mos structure is selected for the transmitter driver section.

To comply with underground voltages at transmitter output pins, an HV structure (p-mos) is mandatory.

However, HV structures are intrinsically weaker than 5V structures with respect to TID effects (trapped charges) due to field oxide on drift regions.

Hence, design countermeasures to mitigate these effects have to be under taken.



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First Countermeasure: design First Countermeasure: design architecturalarchitectural

Gate level for out regulation

GATE

TXBUS

-4V

+4V

TXBUS

-4V

Trade-off between open-loop and closed loop configurations show that closed loop driving concept allows to keep electrical parameters more stable against a wide range of environmental conditions

(temperature, process spread, characteristics degradation as an effect of TID)



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Second Countermeasure: simulation Second Countermeasure: simulation methodologymethodology

TID-degraded models have been extracted for the most critical component in the design (p-mos HV driving transistor): for this purpose, TID irradiation test has been performed on basic structures provided by the foundry.

Different TID-levels models have been built to fit the measured electrical characteristics.

The main parameters inside the BSIM3V3 models which govern the characteristics degradation as an effect of TID are :

0 (cm2/Vsec): mobility factor

nFactor : sub threshold drain current factor to take in to account for interface states

We acted on both parameters to fit degraded models to the measured degraded characteristics.



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Third Countermeasure: H-type layout Third Countermeasure: H-type layout Extensive use of H-type structures

available in 1.0um HV SOI CMOS process reduces TID induced leakage.

In H-type structures, the bird’s beak regions are not located on the low-doped well, but just over an high doped region of the well.

This increases the potential needed to invert locally the well, as well the trapped charge amount needed to invert the channel and create the local leaking channel.

The H-type structure builds a channel-stop for the leaking channel.

Rectangular structure

H-type structure



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Receiver Architecture (Low Voltage Receiver Architecture (Low Voltage Section)Section)

The receiver discriminates if the input filtered differential waveforms are inside the thresholds, above both thresholds, less than both thresholds.

It acts as a window comparator.

On the base of comparator outputs, and depending on input signals RXINHB and RXSENS logic status, the decodify to RX and RXB logic outputs is generated.

Differential filter

TH_H

TH_L

+

+

-

-

RXBUS

RXBUSB

COMP_H

COMP_L

COMP_H, COMP_L= 11

COMP_H, COMP_L= 01

COMP_H, COMP_L= 00

TH_H

TH_L

Signal



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Receiver Block DiagramReceiver Block Diagram

ESD Protection

Filter &

Attenuator

+

-

RXBUS

RXBUSB

COMP_H

COMP_L

Input HV section

Codify CMOS/LCMOSCodify

CMOS/LCMOSCodify

RX

RXB

RXSENSE

RXINHB

HV levels

Filter &

Attenuator +

Window Comparator

Common Mode &

Thresholds generator

The input section of the receiver block needs to translate the input common mode from 0V (imposed by the transformer center tap to GND) to a 0V/5V input common mode, to allow that comparator operates correctly.



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Radiation TID tests on the first RUNRadiation TID tests on the first RUN• Test performed up to 100 Krads using a Co60 source in 2 steps:

– 0 to 28 Krads : 39 rads/h– 28 to 100 Krads : 94 rads/h

• Use of a test structure in order to characterize the TID influence:

• One sample (N°11: no irradiation)• 3 samples : (N°2,3,4 : power supplied)• 6 samples : not power supplied.



1515

Radiation TID test ResultsRadiation TID test Results• Test structure



1616

Radiation TID test ResultsRadiation TID test Results• Output Amplitude



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Radiation TID test ResultsRadiation TID test Results• Rise Time

150

170

190

210

230

250

270

290

0 20 40 60 80 100 120

Total Irradiation Dose (krads)

Ris

e ti

me

(ns)

2

3

4

5

6

7

8

9

10

11 (témoin)



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ConclusionConclusion

• XFAB SOI 1µ technology compliant with space mission environment.

• It is possible to take into account the radiation effects during the design and the simulations.

• It is possible to use a radiation structure to measure the TID in order to compensate the radiation effects by design.



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Wafer PhotoWafer Photo

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